diff options
Diffstat (limited to 'arch/sh/boards/renesas/sh7710voipgw/setup.c')
-rw-r--r-- | arch/sh/boards/renesas/sh7710voipgw/setup.c | 105 |
1 files changed, 46 insertions, 59 deletions
diff --git a/arch/sh/boards/renesas/sh7710voipgw/setup.c b/arch/sh/boards/renesas/sh7710voipgw/setup.c index e57e7afab8c6..180810b12107 100644 --- a/arch/sh/boards/renesas/sh7710voipgw/setup.c +++ b/arch/sh/boards/renesas/sh7710voipgw/setup.c | |||
@@ -13,6 +13,51 @@ | |||
13 | #include <asm/io.h> | 13 | #include <asm/io.h> |
14 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
15 | 15 | ||
16 | static struct ipr_data sh7710voipgw_ipr_map[] = { | ||
17 | { TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY }, | ||
18 | { WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY }, | ||
19 | |||
20 | /* SCIF0 */ | ||
21 | { SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
22 | { SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
23 | { SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
24 | { SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
25 | |||
26 | /* DMAC-1 */ | ||
27 | { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
28 | { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
29 | { DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
30 | { DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
31 | |||
32 | /* DMAC-2 */ | ||
33 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
34 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
35 | |||
36 | /* IPSEC */ | ||
37 | { IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY }, | ||
38 | |||
39 | /* EDMAC */ | ||
40 | { EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, EDMAC0_PRIORITY }, | ||
41 | { EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, EDMAC1_PRIORITY }, | ||
42 | { EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, EDMAC2_PRIORITY }, | ||
43 | |||
44 | /* SIOF0 */ | ||
45 | { SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
46 | { SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
47 | { SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
48 | { SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
49 | |||
50 | /* SIOF1 */ | ||
51 | { SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
52 | { SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
53 | { SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
54 | { SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
55 | |||
56 | /* SLIC IRQ's */ | ||
57 | { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, | ||
58 | { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, | ||
59 | }; | ||
60 | |||
16 | /* | 61 | /* |
17 | * Initialize IRQ setting | 62 | * Initialize IRQ setting |
18 | */ | 63 | */ |
@@ -37,65 +82,7 @@ static void __init sh7710voipgw_init_irq(void) | |||
37 | */ | 82 | */ |
38 | ctrl_outw(0x2aa, INTC_ICR1); | 83 | ctrl_outw(0x2aa, INTC_ICR1); |
39 | 84 | ||
40 | /* Now make IPR interrupts */ | 85 | make_ipr_irq(sh7710voipgw_ipr_map, ARRAY_SIZE(sh7710voipgw_ipr_map)); |
41 | make_ipr_irq(TIMER2_IRQ, TIMER2_IPR_ADDR, | ||
42 | TIMER2_IPR_POS, TIMER2_PRIORITY); | ||
43 | make_ipr_irq(WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY); | ||
44 | |||
45 | /* SCIF0 */ | ||
46 | make_ipr_irq(SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
47 | SCIF0_PRIORITY); | ||
48 | make_ipr_irq(SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
49 | SCIF0_PRIORITY); | ||
50 | make_ipr_irq(SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
51 | SCIF0_PRIORITY); | ||
52 | make_ipr_irq(SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
53 | SCIF0_PRIORITY); | ||
54 | |||
55 | /* DMAC-1 */ | ||
56 | make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
57 | make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
58 | make_ipr_irq(DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
59 | make_ipr_irq(DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
60 | |||
61 | /* DMAC-2 */ | ||
62 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
63 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
64 | |||
65 | /* IPSEC */ | ||
66 | make_ipr_irq(IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY); | ||
67 | |||
68 | /* EDMAC */ | ||
69 | make_ipr_irq(EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, | ||
70 | EDMAC0_PRIORITY); | ||
71 | make_ipr_irq(EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, | ||
72 | EDMAC1_PRIORITY); | ||
73 | make_ipr_irq(EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, | ||
74 | EDMAC2_PRIORITY); | ||
75 | |||
76 | /* SIOF0 */ | ||
77 | make_ipr_irq(SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
78 | SIOF0_PRIORITY); | ||
79 | make_ipr_irq(SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
80 | SIOF0_PRIORITY); | ||
81 | make_ipr_irq(SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
82 | SIOF0_PRIORITY); | ||
83 | make_ipr_irq(SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
84 | SIOF0_PRIORITY); | ||
85 | |||
86 | /* SIOF1 */ | ||
87 | make_ipr_irq(SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
88 | SIOF1_PRIORITY); | ||
89 | make_ipr_irq(SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
90 | SIOF1_PRIORITY); | ||
91 | make_ipr_irq(SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
92 | SIOF1_PRIORITY); | ||
93 | make_ipr_irq(SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
94 | SIOF1_PRIORITY); | ||
95 | |||
96 | /* SLIC IRQ's */ | ||
97 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); | ||
98 | make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); | ||
99 | } | 86 | } |
100 | 87 | ||
101 | /* | 88 | /* |