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-rw-r--r--arch/sh/boards/magicpanelr2/Kconfig13
-rw-r--r--arch/sh/boards/magicpanelr2/Makefile5
-rw-r--r--arch/sh/boards/magicpanelr2/setup.c312
3 files changed, 330 insertions, 0 deletions
diff --git a/arch/sh/boards/magicpanelr2/Kconfig b/arch/sh/boards/magicpanelr2/Kconfig
new file mode 100644
index 000000000000..b0abddc3e84f
--- /dev/null
+++ b/arch/sh/boards/magicpanelr2/Kconfig
@@ -0,0 +1,13 @@
1if SH_MAGIC_PANEL_R2
2
3menu "Magic Panel R2 options"
4
5config SH_MAGIC_PANEL_R2_VERSION
6 int SH_MAGIC_PANEL_R2_VERSION
7 default "3"
8 help
9 Set the version of the Magic Panel R2
10
11endmenu
12
13endif
diff --git a/arch/sh/boards/magicpanelr2/Makefile b/arch/sh/boards/magicpanelr2/Makefile
new file mode 100644
index 000000000000..7a6d586b9072
--- /dev/null
+++ b/arch/sh/boards/magicpanelr2/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Magic Panel specific parts
3#
4
5obj-y := setup.o \ No newline at end of file
diff --git a/arch/sh/boards/magicpanelr2/setup.c b/arch/sh/boards/magicpanelr2/setup.c
new file mode 100644
index 000000000000..c5930656654f
--- /dev/null
+++ b/arch/sh/boards/magicpanelr2/setup.c
@@ -0,0 +1,312 @@
1/*
2 * linux/arch/sh/boards/magicpanel/setup.c
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * Magic Panel Release 2 board setup
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/platform_device.h>
15#include <linux/ide.h>
16#include <linux/irq.h>
17#include <linux/delay.h>
18#include <asm/magicpanelr2.h>
19#include <asm/heartbeat.h>
20
21#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL)
22
23/* Wait until reset finished. Timeout is 100ms. */
24static int __init ethernet_reset_finished(void)
25{
26 int i;
27
28 if (LAN9115_READY)
29 return 1;
30
31 for (i = 0; i < 10; ++i) {
32 mdelay(10);
33 if (LAN9115_READY)
34 return 1;
35 }
36
37 return 0;
38}
39
40static void __init reset_ethernet(void)
41{
42 /* PMDR: LAN_RESET=on */
43 CLRBITS_OUTB(0x10, PORT_PMDR);
44
45 udelay(200);
46
47 /* PMDR: LAN_RESET=off */
48 SETBITS_OUTB(0x10, PORT_PMDR);
49}
50
51static void __init setup_chip_select(void)
52{
53 /* CS2: LAN (0x08000000 - 0x0bffffff) */
54 /* no idle cycles, normal space, 8 bit data bus */
55 ctrl_outl(0x36db0400, CS2BCR);
56 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
57 ctrl_outl(0x000003c0, CS2WCR);
58
59 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
60 /* no idle cycles, normal space, 8 bit data bus */
61 ctrl_outl(0x00000200, CS4BCR);
62 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
63 ctrl_outl(0x00100981, CS4WCR);
64
65 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
66 /* no idle cycles, normal space, 8 bit data bus */
67 ctrl_outl(0x00000200, CS5ABCR);
68 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
69 ctrl_outl(0x00100981, CS5AWCR);
70
71 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
72 /* no idle cycles, normal space, 8 bit data bus */
73 ctrl_outl(0x00000200, CS5BBCR);
74 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
75 ctrl_outl(0x00100981, CS5BWCR);
76
77 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
78 /* no idle cycles, normal space, 8 bit data bus */
79 ctrl_outl(0x00000200, CS6ABCR);
80 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
81 ctrl_outl(0x001009C1, CS6AWCR);
82}
83
84static void __init setup_port_multiplexing(void)
85{
86 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
87 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
88 */
89 ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
90
91 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
92 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
93 */
94 ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
95
96 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
97 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
98 */
99 ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
100
101 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
102 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
103 */
104 ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
105
106 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
107 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
108 */
109 ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
110
111 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
112 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
113 */
114 ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
115
116 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
117 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
118 */
119 ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
120
121 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
122 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
123 */
124 ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
125
126 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
127 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
128 */
129 ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
130
131 /* K7 (x); K6 (x); K5 (x); K4 (x);
132 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
133 */
134 ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
135
136 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
137 * L3 TCK; L2 (x); L1 (x); L0 (x);
138 */
139 ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
140
141 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
142 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
143 * M1 CS5B(CAN3_CS); M0 GPI+(nc);
144 */
145 ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
146
147 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
148 * LAN_RESET=off, BUZZER=off, LCD_BL=off
149 */
150#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
151 ctrl_outb(0x30, PORT_PMDR);
152#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
153 ctrl_outb(0xF0, PORT_PMDR);
154#else
155#error Unknown revision of PLATFORM_MP_R2
156#endif
157
158 /* P7 (x); P6 (x); P5 (x);
159 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
160 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
161 */
162 ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
163 ctrl_outb(0x10, PORT_PPDR);
164
165 /* R7 A25; R6 A24; R5 A23; R4 A22;
166 * R3 A21; R2 A20; R1 A19; R0 A0;
167 */
168 ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */
169
170 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
171 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
172 */
173 ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
174
175 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
176 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
177 */
178 ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
179
180 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
181 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
182 */
183 ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
184
185 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
186 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
187 */
188 ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
189}
190
191static void __init mpr2_setup(char **cmdline_p)
192{
193 __set_io_port_base(0xa0000000);
194
195 /* set Pin Select Register A:
196 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
197 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
198 */
199 ctrl_outw(0xAABC, PORT_PSELA);
200 /* set Pin Select Register B:
201 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
202 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
203 */
204 ctrl_outw(0x3C00, PORT_PSELB);
205 /* set Pin Select Register C:
206 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
207 */
208 ctrl_outw(0x0000, PORT_PSELC);
209 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
210 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
211 */
212 ctrl_outw(0x0000, PORT_PSELD);
213 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
214 ctrl_outw(0x0101, PORT_UTRCTL);
215 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
216 ctrl_outw(0xA5C0, PORT_UCLKCR_W);
217
218 setup_chip_select();
219
220 setup_port_multiplexing();
221
222 reset_ethernet();
223
224 printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
225 CONFIG_SH_MAGIC_PANEL_R2_VERSION);
226
227 if (ethernet_reset_finished() == 0)
228 printk(KERN_WARNING "Ethernet not ready\n");
229}
230
231static struct resource smc911x_resources[] = {
232 [0] = {
233 .start = 0xa8000000,
234 .end = 0xabffffff,
235 .flags = IORESOURCE_MEM,
236 },
237 [1] = {
238 .start = 35,
239 .end = 35,
240 .flags = IORESOURCE_IRQ,
241 },
242};
243
244static struct platform_device smc911x_device = {
245 .name = "smc911x",
246 .id = -1,
247 .num_resources = ARRAY_SIZE(smc911x_resources),
248 .resource = smc911x_resources,
249};
250
251static struct resource heartbeat_resources[] = {
252 [0] = {
253 .start = PA_LED,
254 .end = PA_LED,
255 .flags = IORESOURCE_MEM,
256 },
257};
258
259static struct heartbeat_data heartbeat_data = {
260 .flags = HEARTBEAT_INVERTED,
261};
262
263static struct platform_device heartbeat_device = {
264 .name = "heartbeat",
265 .id = -1,
266 .dev = {
267 .platform_data = &heartbeat_data,
268 },
269 .num_resources = ARRAY_SIZE(heartbeat_resources),
270 .resource = heartbeat_resources,
271};
272
273static struct platform_device *mpr2_devices[] __initdata = {
274 &heartbeat_device,
275 &smc911x_device,
276};
277
278static int __init mpr2_devices_setup(void)
279{
280 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
281}
282device_initcall(mpr2_devices_setup);
283
284/*
285 * Initialize IRQ setting
286 */
287static void __init init_mpr2_IRQ(void)
288{
289 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
290
291 set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
292 set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
293 set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
294 set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
295 set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
296 set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
297
298 intc_set_priority(32, 13); /* IRQ0 CAN1 */
299 intc_set_priority(33, 13); /* IRQ0 CAN2 */
300 intc_set_priority(34, 13); /* IRQ0 CAN3 */
301 intc_set_priority(35, 6); /* IRQ3 SMSC9115 */
302}
303
304/*
305 * The Machine Vector
306 */
307
308static struct sh_machine_vector mv_mpr2 __initmv = {
309 .mv_name = "mpr2",
310 .mv_setup = mpr2_setup,
311 .mv_init_irq = init_mpr2_IRQ,
312};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 10:20:47 -0500