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-rw-r--r--arch/sh/boards/mach-kfr2r09/Makefile4
-rw-r--r--arch/sh/boards/mach-kfr2r09/lcd_wqvga.c338
-rw-r--r--arch/sh/boards/mach-kfr2r09/sdram.S80
-rw-r--r--arch/sh/boards/mach-kfr2r09/setup.c647
4 files changed, 1069 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-kfr2r09/Makefile b/arch/sh/boards/mach-kfr2r09/Makefile
new file mode 100644
index 000000000000..60dd63f4a427
--- /dev/null
+++ b/arch/sh/boards/mach-kfr2r09/Makefile
@@ -0,0 +1,4 @@
1obj-y := setup.o sdram.o
2ifneq ($(CONFIG_FB_SH_MOBILE_LCDC),)
3obj-y += lcd_wqvga.o
4endif
diff --git a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
new file mode 100644
index 000000000000..25e145fb7087
--- /dev/null
+++ b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
@@ -0,0 +1,338 @@
1/*
2 * KFR2R09 LCD panel support
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * Register settings based on the out-of-tree t33fb.c driver
7 * Copyright (C) 2008 Lineo Solutions, Inc.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/gpio.h>
21#include <video/sh_mobile_lcdc.h>
22#include <mach/kfr2r09.h>
23#include <cpu/sh7724.h>
24
25/* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made
26 * up of a 240x400 LCD hooked up to a R61517 driver IC. The driver IC is
27 * communicating with the main port of the LCDC using an 18-bit SYS interface.
28 *
29 * The device code for this LCD module is 0x01221517.
30 */
31
32static const unsigned char data_frame_if[] = {
33 0x02, /* WEMODE: 1=cont, 0=one-shot */
34 0x00, 0x00,
35 0x00, /* EPF, DFM */
36 0x02, /* RIM[1] : 1 (18bpp) */
37};
38
39static const unsigned char data_panel[] = {
40 0x0b,
41 0x63, /* 400 lines */
42 0x04, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00,
43};
44
45static const unsigned char data_timing[] = {
46 0x00, 0x00, 0x13, 0x08, 0x08,
47};
48
49static const unsigned char data_timing_src[] = {
50 0x11, 0x01, 0x00, 0x01,
51};
52
53static const unsigned char data_gamma[] = {
54 0x01, 0x02, 0x08, 0x23, 0x03, 0x0c, 0x00, 0x06, 0x00, 0x00,
55 0x01, 0x00, 0x0c, 0x23, 0x03, 0x08, 0x02, 0x06, 0x00, 0x00,
56};
57
58static const unsigned char data_power[] = {
59 0x07, 0xc5, 0xdc, 0x02, 0x33, 0x0a,
60};
61
62static unsigned long read_reg(void *sohandle,
63 struct sh_mobile_lcdc_sys_bus_ops *so)
64{
65 return so->read_data(sohandle);
66}
67
68static void write_reg(void *sohandle,
69 struct sh_mobile_lcdc_sys_bus_ops *so,
70 int i, unsigned long v)
71{
72 if (i)
73 so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */
74 else
75 so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */
76}
77
78static void write_data(void *sohandle,
79 struct sh_mobile_lcdc_sys_bus_ops *so,
80 unsigned char const *data, int no_data)
81{
82 int i;
83
84 for (i = 0; i < no_data; i++)
85 write_reg(sohandle, so, 1, data[i]);
86}
87
88static unsigned long read_device_code(void *sohandle,
89 struct sh_mobile_lcdc_sys_bus_ops *so)
90{
91 unsigned long device_code;
92
93 /* access protect OFF */
94 write_reg(sohandle, so, 0, 0xb0);
95 write_reg(sohandle, so, 1, 0x00);
96
97 /* deep standby OFF */
98 write_reg(sohandle, so, 0, 0xb1);
99 write_reg(sohandle, so, 1, 0x00);
100
101 /* device code command */
102 write_reg(sohandle, so, 0, 0xbf);
103 mdelay(50);
104
105 /* dummy read */
106 read_reg(sohandle, so);
107
108 /* read device code */
109 device_code = ((read_reg(sohandle, so) & 0xff) << 24);
110 device_code |= ((read_reg(sohandle, so) & 0xff) << 16);
111 device_code |= ((read_reg(sohandle, so) & 0xff) << 8);
112 device_code |= (read_reg(sohandle, so) & 0xff);
113
114 return device_code;
115}
116
117static void write_memory_start(void *sohandle,
118 struct sh_mobile_lcdc_sys_bus_ops *so)
119{
120 write_reg(sohandle, so, 0, 0x2c);
121}
122
123static void clear_memory(void *sohandle,
124 struct sh_mobile_lcdc_sys_bus_ops *so)
125{
126 int i;
127
128 /* write start */
129 write_memory_start(sohandle, so);
130
131 /* paint it black */
132 for (i = 0; i < (240 * 400); i++)
133 write_reg(sohandle, so, 1, 0x00);
134}
135
136static void display_on(void *sohandle,
137 struct sh_mobile_lcdc_sys_bus_ops *so)
138{
139 /* access protect off */
140 write_reg(sohandle, so, 0, 0xb0);
141 write_reg(sohandle, so, 1, 0x00);
142
143 /* exit deep standby mode */
144 write_reg(sohandle, so, 0, 0xb1);
145 write_reg(sohandle, so, 1, 0x00);
146
147 /* frame memory I/F */
148 write_reg(sohandle, so, 0, 0xb3);
149 write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if));
150
151 /* display mode and frame memory write mode */
152 write_reg(sohandle, so, 0, 0xb4);
153 write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */
154
155 /* panel */
156 write_reg(sohandle, so, 0, 0xc0);
157 write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel));
158
159 /* timing (normal) */
160 write_reg(sohandle, so, 0, 0xc1);
161 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
162
163 /* timing (partial) */
164 write_reg(sohandle, so, 0, 0xc2);
165 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
166
167 /* timing (idle) */
168 write_reg(sohandle, so, 0, 0xc3);
169 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
170
171 /* timing (source/VCOM/gate driving) */
172 write_reg(sohandle, so, 0, 0xc4);
173 write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src));
174
175 /* gamma (red) */
176 write_reg(sohandle, so, 0, 0xc8);
177 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
178
179 /* gamma (green) */
180 write_reg(sohandle, so, 0, 0xc9);
181 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
182
183 /* gamma (blue) */
184 write_reg(sohandle, so, 0, 0xca);
185 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
186
187 /* power (common) */
188 write_reg(sohandle, so, 0, 0xd0);
189 write_data(sohandle, so, data_power, ARRAY_SIZE(data_power));
190
191 /* VCOM */
192 write_reg(sohandle, so, 0, 0xd1);
193 write_reg(sohandle, so, 1, 0x00);
194 write_reg(sohandle, so, 1, 0x0f);
195 write_reg(sohandle, so, 1, 0x02);
196
197 /* power (normal) */
198 write_reg(sohandle, so, 0, 0xd2);
199 write_reg(sohandle, so, 1, 0x63);
200 write_reg(sohandle, so, 1, 0x24);
201
202 /* power (partial) */
203 write_reg(sohandle, so, 0, 0xd3);
204 write_reg(sohandle, so, 1, 0x63);
205 write_reg(sohandle, so, 1, 0x24);
206
207 /* power (idle) */
208 write_reg(sohandle, so, 0, 0xd4);
209 write_reg(sohandle, so, 1, 0x63);
210 write_reg(sohandle, so, 1, 0x24);
211
212 write_reg(sohandle, so, 0, 0xd8);
213 write_reg(sohandle, so, 1, 0x77);
214 write_reg(sohandle, so, 1, 0x77);
215
216 /* TE signal */
217 write_reg(sohandle, so, 0, 0x35);
218 write_reg(sohandle, so, 1, 0x00);
219
220 /* TE signal line */
221 write_reg(sohandle, so, 0, 0x44);
222 write_reg(sohandle, so, 1, 0x00);
223 write_reg(sohandle, so, 1, 0x00);
224
225 /* column address */
226 write_reg(sohandle, so, 0, 0x2a);
227 write_reg(sohandle, so, 1, 0x00);
228 write_reg(sohandle, so, 1, 0x00);
229 write_reg(sohandle, so, 1, 0x00);
230 write_reg(sohandle, so, 1, 0xef);
231
232 /* page address */
233 write_reg(sohandle, so, 0, 0x2b);
234 write_reg(sohandle, so, 1, 0x00);
235 write_reg(sohandle, so, 1, 0x00);
236 write_reg(sohandle, so, 1, 0x01);
237 write_reg(sohandle, so, 1, 0x8f);
238
239 /* exit sleep mode */
240 write_reg(sohandle, so, 0, 0x11);
241
242 mdelay(120);
243
244 /* clear vram */
245 clear_memory(sohandle, so);
246
247 /* display ON */
248 write_reg(sohandle, so, 0, 0x29);
249 mdelay(1);
250
251 write_memory_start(sohandle, so);
252}
253
254int kfr2r09_lcd_setup(void *board_data, void *sohandle,
255 struct sh_mobile_lcdc_sys_bus_ops *so)
256{
257 /* power on */
258 gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */
259 gpio_set_value(GPIO_PTE4, 0); /* LCD_RST/ -> L */
260 gpio_set_value(GPIO_PTF4, 1); /* PROTECT/ -> H */
261 udelay(1100);
262 gpio_set_value(GPIO_PTE4, 1); /* LCD_RST/ -> H */
263 udelay(10);
264 gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */
265 mdelay(20);
266
267 if (read_device_code(sohandle, so) != 0x01221517)
268 return -ENODEV;
269
270 pr_info("KFR2R09 WQVGA LCD Module detected.\n");
271
272 display_on(sohandle, so);
273 return 0;
274}
275
276void kfr2r09_lcd_start(void *board_data, void *sohandle,
277 struct sh_mobile_lcdc_sys_bus_ops *so)
278{
279 write_memory_start(sohandle, so);
280}
281
282#define CTRL_CKSW 0x10
283#define CTRL_C10 0x20
284#define CTRL_CPSW 0x80
285#define MAIN_MLED4 0x40
286#define MAIN_MSW 0x80
287
288static int kfr2r09_lcd_backlight(int on)
289{
290 struct i2c_adapter *a;
291 struct i2c_msg msg;
292 unsigned char buf[2];
293 int ret;
294
295 a = i2c_get_adapter(0);
296 if (!a)
297 return -ENODEV;
298
299 buf[0] = 0x00;
300 if (on)
301 buf[1] = CTRL_CPSW | CTRL_C10 | CTRL_CKSW;
302 else
303 buf[1] = 0;
304
305 msg.addr = 0x75;
306 msg.buf = buf;
307 msg.len = 2;
308 msg.flags = 0;
309 ret = i2c_transfer(a, &msg, 1);
310 if (ret != 1)
311 return -ENODEV;
312
313 buf[0] = 0x01;
314 if (on)
315 buf[1] = MAIN_MSW | MAIN_MLED4 | 0x0c;
316 else
317 buf[1] = 0;
318
319 msg.addr = 0x75;
320 msg.buf = buf;
321 msg.len = 2;
322 msg.flags = 0;
323 ret = i2c_transfer(a, &msg, 1);
324 if (ret != 1)
325 return -ENODEV;
326
327 return 0;
328}
329
330void kfr2r09_lcd_on(void *board_data, struct fb_info *info)
331{
332 kfr2r09_lcd_backlight(1);
333}
334
335void kfr2r09_lcd_off(void *board_data)
336{
337 kfr2r09_lcd_backlight(0);
338}
diff --git a/arch/sh/boards/mach-kfr2r09/sdram.S b/arch/sh/boards/mach-kfr2r09/sdram.S
new file mode 100644
index 000000000000..0c9f55bec2fe
--- /dev/null
+++ b/arch/sh/boards/mach-kfr2r09/sdram.S
@@ -0,0 +1,80 @@
1/*
2 * KFR2R09 sdram self/auto-refresh setup code
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/sys.h>
12#include <linux/errno.h>
13#include <linux/linkage.h>
14#include <asm/asm-offsets.h>
15#include <asm/suspend.h>
16#include <asm/romimage-macros.h>
17
18/* code to enter and leave self-refresh. must be self-contained.
19 * this code will be copied to on-chip memory and executed from there.
20 */
21 .balign 4
22ENTRY(kfr2r09_sdram_enter_start)
23
24 /* DBSC: put memory in self-refresh mode */
25
26 ED 0xFD000010, 0x00000000 /* DBEN */
27 ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
28 ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
29 ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
30 ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
31
32 rts
33 nop
34
35ENTRY(kfr2r09_sdram_enter_end)
36
37 .balign 4
38ENTRY(kfr2r09_sdram_leave_start)
39
40 /* DBSC: put memory in auto-refresh mode */
41
42 mov.l @(SH_SLEEP_MODE, r5), r0
43 tst #SUSP_SH_RSTANDBY, r0
44 bf resume_rstandby
45
46 ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
47 WAIT 1
48 ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
49 ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
50 ED 0xFD000010, 0x00000001 /* DBEN */
51 ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
52
53 rts
54 nop
55
56resume_rstandby:
57
58 /* DBSC: re-initialize and put in auto-refresh */
59
60 ED 0xFD000108, 0x40000301 /* DBPDCNT0 */
61 ED 0xFD000020, 0x011B0002 /* DBCONF */
62 ED 0xFD000030, 0x03060E02 /* DBTR0 */
63 ED 0xFD000034, 0x01020102 /* DBTR1 */
64 ED 0xFD000038, 0x01090406 /* DBTR2 */
65 ED 0xFD000008, 0x00000004 /* DBKIND */
66 ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
67 ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
68 ED 0xFD000018, 0x00000001 /* DBCKECNT */
69 WAIT 1
70 ED 0xFD000010, 0x00000001 /* DBEN */
71 ED 0xFD000044, 0x000004AF /* DBRFPDN1 */
72 ED 0xFD000048, 0x20CF0037 /* DBRFPDN2 */
73 ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
74 ED 0xFD000108, 0x40000300 /* DBPDCNT0 */
75 ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
76
77 rts
78 nop
79
80ENTRY(kfr2r09_sdram_leave_end)
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
new file mode 100644
index 000000000000..9b60eaabf8f3
--- /dev/null
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -0,0 +1,647 @@
1/*
2 * KFR2R09 board support code
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/sh_mobile_sdhi.h>
14#include <linux/mfd/tmio.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/onenand.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/gpio.h>
20#include <linux/input.h>
21#include <linux/input/sh_keysc.h>
22#include <linux/i2c.h>
23#include <linux/usb/r8a66597.h>
24#include <media/rj54n1cb0c.h>
25#include <media/soc_camera.h>
26#include <media/sh_mobile_ceu.h>
27#include <video/sh_mobile_lcdc.h>
28#include <asm/suspend.h>
29#include <asm/clock.h>
30#include <asm/machvec.h>
31#include <asm/io.h>
32#include <cpu/sh7724.h>
33#include <mach/kfr2r09.h>
34
35static struct mtd_partition kfr2r09_nor_flash_partitions[] =
36{
37 {
38 .name = "boot",
39 .offset = 0,
40 .size = (4 * 1024 * 1024),
41 .mask_flags = MTD_WRITEABLE, /* Read-only */
42 },
43 {
44 .name = "other",
45 .offset = MTDPART_OFS_APPEND,
46 .size = MTDPART_SIZ_FULL,
47 },
48};
49
50static struct physmap_flash_data kfr2r09_nor_flash_data = {
51 .width = 2,
52 .parts = kfr2r09_nor_flash_partitions,
53 .nr_parts = ARRAY_SIZE(kfr2r09_nor_flash_partitions),
54};
55
56static struct resource kfr2r09_nor_flash_resources[] = {
57 [0] = {
58 .name = "NOR Flash",
59 .start = 0x00000000,
60 .end = 0x03ffffff,
61 .flags = IORESOURCE_MEM,
62 }
63};
64
65static struct platform_device kfr2r09_nor_flash_device = {
66 .name = "physmap-flash",
67 .resource = kfr2r09_nor_flash_resources,
68 .num_resources = ARRAY_SIZE(kfr2r09_nor_flash_resources),
69 .dev = {
70 .platform_data = &kfr2r09_nor_flash_data,
71 },
72};
73
74static struct resource kfr2r09_nand_flash_resources[] = {
75 [0] = {
76 .name = "NAND Flash",
77 .start = 0x10000000,
78 .end = 0x1001ffff,
79 .flags = IORESOURCE_MEM,
80 }
81};
82
83static struct platform_device kfr2r09_nand_flash_device = {
84 .name = "onenand-flash",
85 .resource = kfr2r09_nand_flash_resources,
86 .num_resources = ARRAY_SIZE(kfr2r09_nand_flash_resources),
87};
88
89static struct sh_keysc_info kfr2r09_sh_keysc_info = {
90 .mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */
91 .scan_timing = 3,
92 .delay = 10,
93 .keycodes = {
94 KEY_PHONE, KEY_CLEAR, KEY_MAIL, KEY_WWW, KEY_ENTER,
95 KEY_1, KEY_2, KEY_3, 0, KEY_UP,
96 KEY_4, KEY_5, KEY_6, 0, KEY_LEFT,
97 KEY_7, KEY_8, KEY_9, KEY_PROG1, KEY_RIGHT,
98 KEY_S, KEY_0, KEY_P, KEY_PROG2, KEY_DOWN,
99 0, 0, 0, 0, 0
100 },
101};
102
103static struct resource kfr2r09_sh_keysc_resources[] = {
104 [0] = {
105 .name = "KEYSC",
106 .start = 0x044b0000,
107 .end = 0x044b000f,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = 79,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device kfr2r09_sh_keysc_device = {
117 .name = "sh_keysc",
118 .id = 0, /* "keysc0" clock */
119 .num_resources = ARRAY_SIZE(kfr2r09_sh_keysc_resources),
120 .resource = kfr2r09_sh_keysc_resources,
121 .dev = {
122 .platform_data = &kfr2r09_sh_keysc_info,
123 },
124 .archdata = {
125 .hwblk_id = HWBLK_KEYSC,
126 },
127};
128
129const static struct fb_videomode kfr2r09_lcdc_modes[] = {
130 {
131 .name = "TX07D34VM0AAA",
132 .xres = 240,
133 .yres = 400,
134 .left_margin = 0,
135 .right_margin = 16,
136 .hsync_len = 8,
137 .upper_margin = 0,
138 .lower_margin = 1,
139 .vsync_len = 1,
140 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
141 },
142};
143
144static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
145 .clock_source = LCDC_CLK_BUS,
146 .ch[0] = {
147 .chan = LCDC_CHAN_MAINLCD,
148 .bpp = 16,
149 .interface_type = SYS18,
150 .clock_divider = 6,
151 .flags = LCDC_FLAGS_DWPOL,
152 .lcd_cfg = kfr2r09_lcdc_modes,
153 .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
154 .lcd_size_cfg = {
155 .width = 35,
156 .height = 58,
157 },
158 .board_cfg = {
159 .setup_sys = kfr2r09_lcd_setup,
160 .start_transfer = kfr2r09_lcd_start,
161 .display_on = kfr2r09_lcd_on,
162 .display_off = kfr2r09_lcd_off,
163 },
164 .sys_bus_cfg = {
165 .ldmt2r = 0x07010904,
166 .ldmt3r = 0x14012914,
167 /* set 1s delay to encourage fsync() */
168 .deferred_io_msec = 1000,
169 },
170 }
171};
172
173static struct resource kfr2r09_sh_lcdc_resources[] = {
174 [0] = {
175 .name = "LCDC",
176 .start = 0xfe940000, /* P4-only space */
177 .end = 0xfe942fff,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = 106,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186static struct platform_device kfr2r09_sh_lcdc_device = {
187 .name = "sh_mobile_lcdc_fb",
188 .num_resources = ARRAY_SIZE(kfr2r09_sh_lcdc_resources),
189 .resource = kfr2r09_sh_lcdc_resources,
190 .dev = {
191 .platform_data = &kfr2r09_sh_lcdc_info,
192 },
193 .archdata = {
194 .hwblk_id = HWBLK_LCDC,
195 },
196};
197
198static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
199 .on_chip = 1,
200};
201
202static struct resource kfr2r09_usb0_gadget_resources[] = {
203 [0] = {
204 .start = 0x04d80000,
205 .end = 0x04d80123,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = 65,
210 .end = 65,
211 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
212 },
213};
214
215static struct platform_device kfr2r09_usb0_gadget_device = {
216 .name = "r8a66597_udc",
217 .id = 0,
218 .dev = {
219 .dma_mask = NULL, /* not use dma */
220 .coherent_dma_mask = 0xffffffff,
221 .platform_data = &kfr2r09_usb0_gadget_data,
222 },
223 .num_resources = ARRAY_SIZE(kfr2r09_usb0_gadget_resources),
224 .resource = kfr2r09_usb0_gadget_resources,
225};
226
227static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
228 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
229};
230
231static struct resource kfr2r09_ceu_resources[] = {
232 [0] = {
233 .name = "CEU",
234 .start = 0xfe910000,
235 .end = 0xfe91009f,
236 .flags = IORESOURCE_MEM,
237 },
238 [1] = {
239 .start = 52,
240 .end = 52,
241 .flags = IORESOURCE_IRQ,
242 },
243 [2] = {
244 /* place holder for contiguous memory */
245 },
246};
247
248static struct platform_device kfr2r09_ceu_device = {
249 .name = "sh_mobile_ceu",
250 .id = 0, /* "ceu0" clock */
251 .num_resources = ARRAY_SIZE(kfr2r09_ceu_resources),
252 .resource = kfr2r09_ceu_resources,
253 .dev = {
254 .platform_data = &sh_mobile_ceu_info,
255 },
256 .archdata = {
257 .hwblk_id = HWBLK_CEU0,
258 },
259};
260
261static struct i2c_board_info kfr2r09_i2c_camera = {
262 I2C_BOARD_INFO("rj54n1cb0c", 0x50),
263};
264
265static struct clk *camera_clk;
266
267/* set VIO_CKO clock to 25MHz */
268#define CEU_MCLK_FREQ 25000000
269
270#define DRVCRB 0xA405018C
271static int camera_power(struct device *dev, int mode)
272{
273 int ret;
274
275 if (mode) {
276 long rate;
277
278 camera_clk = clk_get(NULL, "video_clk");
279 if (IS_ERR(camera_clk))
280 return PTR_ERR(camera_clk);
281
282 rate = clk_round_rate(camera_clk, CEU_MCLK_FREQ);
283 ret = clk_set_rate(camera_clk, rate);
284 if (ret < 0)
285 goto eclkrate;
286
287 /* set DRVCRB
288 *
289 * use 1.8 V for VccQ_VIO
290 * use 2.85V for VccQ_SR
291 */
292 __raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
293
294 /* reset clear */
295 ret = gpio_request(GPIO_PTB4, NULL);
296 if (ret < 0)
297 goto eptb4;
298 ret = gpio_request(GPIO_PTB7, NULL);
299 if (ret < 0)
300 goto eptb7;
301
302 ret = gpio_direction_output(GPIO_PTB4, 1);
303 if (!ret)
304 ret = gpio_direction_output(GPIO_PTB7, 1);
305 if (ret < 0)
306 goto egpioout;
307 msleep(1);
308
309 ret = clk_enable(camera_clk); /* start VIO_CKO */
310 if (ret < 0)
311 goto eclkon;
312
313 return 0;
314 }
315
316 ret = 0;
317
318 clk_disable(camera_clk);
319eclkon:
320 gpio_set_value(GPIO_PTB7, 0);
321egpioout:
322 gpio_set_value(GPIO_PTB4, 0);
323 gpio_free(GPIO_PTB7);
324eptb7:
325 gpio_free(GPIO_PTB4);
326eptb4:
327eclkrate:
328 clk_put(camera_clk);
329 return ret;
330}
331
332static struct rj54n1_pdata rj54n1_priv = {
333 .mclk_freq = CEU_MCLK_FREQ,
334 .ioctl_high = false,
335};
336
337static struct soc_camera_link rj54n1_link = {
338 .power = camera_power,
339 .board_info = &kfr2r09_i2c_camera,
340 .i2c_adapter_id = 1,
341 .priv = &rj54n1_priv,
342};
343
344static struct platform_device kfr2r09_camera = {
345 .name = "soc-camera-pdrv",
346 .id = 0,
347 .dev = {
348 .platform_data = &rj54n1_link,
349 },
350};
351
352static struct resource kfr2r09_sh_sdhi0_resources[] = {
353 [0] = {
354 .name = "SDHI0",
355 .start = 0x04ce0000,
356 .end = 0x04ce01ff,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 .start = 100,
361 .flags = IORESOURCE_IRQ,
362 },
363};
364
365static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
366 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
367 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
368 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
369};
370
371static struct platform_device kfr2r09_sh_sdhi0_device = {
372 .name = "sh_mobile_sdhi",
373 .num_resources = ARRAY_SIZE(kfr2r09_sh_sdhi0_resources),
374 .resource = kfr2r09_sh_sdhi0_resources,
375 .dev = {
376 .platform_data = &sh7724_sdhi0_data,
377 },
378 .archdata = {
379 .hwblk_id = HWBLK_SDHI0,
380 },
381};
382
383static struct platform_device *kfr2r09_devices[] __initdata = {
384 &kfr2r09_nor_flash_device,
385 &kfr2r09_nand_flash_device,
386 &kfr2r09_sh_keysc_device,
387 &kfr2r09_sh_lcdc_device,
388 &kfr2r09_ceu_device,
389 &kfr2r09_camera,
390 &kfr2r09_sh_sdhi0_device,
391};
392
393#define BSC_CS0BCR 0xfec10004
394#define BSC_CS0WCR 0xfec10024
395#define BSC_CS4BCR 0xfec10010
396#define BSC_CS4WCR 0xfec10030
397#define PORT_MSELCRB 0xa4050182
398
399#ifdef CONFIG_I2C
400static int kfr2r09_usb0_gadget_i2c_setup(void)
401{
402 struct i2c_adapter *a;
403 struct i2c_msg msg;
404 unsigned char buf[2];
405 int ret;
406
407 a = i2c_get_adapter(0);
408 if (!a)
409 return -ENODEV;
410
411 /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
412 buf[0] = 0x13;
413 msg.addr = 0x09;
414 msg.buf = buf;
415 msg.len = 1;
416 msg.flags = 0;
417 ret = i2c_transfer(a, &msg, 1);
418 if (ret != 1)
419 return -ENODEV;
420
421 buf[0] = 0;
422 msg.addr = 0x09;
423 msg.buf = buf;
424 msg.len = 1;
425 msg.flags = I2C_M_RD;
426 ret = i2c_transfer(a, &msg, 1);
427 if (ret != 1)
428 return -ENODEV;
429
430 buf[1] = buf[0] | (1 << 1);
431 buf[0] = 0x13;
432 msg.addr = 0x09;
433 msg.buf = buf;
434 msg.len = 2;
435 msg.flags = 0;
436 ret = i2c_transfer(a, &msg, 1);
437 if (ret != 1)
438 return -ENODEV;
439
440 return 0;
441}
442
443static int kfr2r09_serial_i2c_setup(void)
444{
445 struct i2c_adapter *a;
446 struct i2c_msg msg;
447 unsigned char buf[2];
448 int ret;
449
450 a = i2c_get_adapter(0);
451 if (!a)
452 return -ENODEV;
453
454 /* set bit 6 (the 7th bit) of chip at 0x09, register 0x13 */
455 buf[0] = 0x13;
456 msg.addr = 0x09;
457 msg.buf = buf;
458 msg.len = 1;
459 msg.flags = 0;
460 ret = i2c_transfer(a, &msg, 1);
461 if (ret != 1)
462 return -ENODEV;
463
464 buf[0] = 0;
465 msg.addr = 0x09;
466 msg.buf = buf;
467 msg.len = 1;
468 msg.flags = I2C_M_RD;
469 ret = i2c_transfer(a, &msg, 1);
470 if (ret != 1)
471 return -ENODEV;
472
473 buf[1] = buf[0] | (1 << 6);
474 buf[0] = 0x13;
475 msg.addr = 0x09;
476 msg.buf = buf;
477 msg.len = 2;
478 msg.flags = 0;
479 ret = i2c_transfer(a, &msg, 1);
480 if (ret != 1)
481 return -ENODEV;
482
483 return 0;
484}
485#else
486static int kfr2r09_usb0_gadget_i2c_setup(void)
487{
488 return -ENODEV;
489}
490
491static int kfr2r09_serial_i2c_setup(void)
492{
493 return -ENODEV;
494}
495#endif
496
497static int kfr2r09_usb0_gadget_setup(void)
498{
499 int plugged_in;
500
501 gpio_request(GPIO_PTN4, NULL); /* USB_DET */
502 gpio_direction_input(GPIO_PTN4);
503 plugged_in = gpio_get_value(GPIO_PTN4);
504 if (!plugged_in)
505 return -ENODEV; /* no cable plugged in */
506
507 if (kfr2r09_usb0_gadget_i2c_setup() != 0)
508 return -ENODEV; /* unable to configure using i2c */
509
510 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
511 gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
512 gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
513 gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
514 msleep(20); /* wait 20ms to let the clock settle */
515 clk_enable(clk_get(NULL, "usb0"));
516 __raw_writew(0x0600, 0xa40501d4);
517
518 return 0;
519}
520
521extern char kfr2r09_sdram_enter_start;
522extern char kfr2r09_sdram_enter_end;
523extern char kfr2r09_sdram_leave_start;
524extern char kfr2r09_sdram_leave_end;
525
526static int __init kfr2r09_devices_setup(void)
527{
528 /* register board specific self-refresh code */
529 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
530 SUSP_SH_RSTANDBY,
531 &kfr2r09_sdram_enter_start,
532 &kfr2r09_sdram_enter_end,
533 &kfr2r09_sdram_leave_start,
534 &kfr2r09_sdram_leave_end);
535
536 /* enable SCIF1 serial port for YC401 console support */
537 gpio_request(GPIO_FN_SCIF1_RXD, NULL);
538 gpio_request(GPIO_FN_SCIF1_TXD, NULL);
539 kfr2r09_serial_i2c_setup(); /* ECONTMSK(bit6=L10ONEN) set 1 */
540 gpio_request(GPIO_PTG3, NULL); /* HPON_ON */
541 gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
542
543 /* setup NOR flash at CS0 */
544 __raw_writel(0x36db0400, BSC_CS0BCR);
545 __raw_writel(0x00000500, BSC_CS0WCR);
546
547 /* setup NAND flash at CS4 */
548 __raw_writel(0x36db0400, BSC_CS4BCR);
549 __raw_writel(0x00000500, BSC_CS4WCR);
550
551 /* setup KEYSC pins */
552 gpio_request(GPIO_FN_KEYOUT0, NULL);
553 gpio_request(GPIO_FN_KEYOUT1, NULL);
554 gpio_request(GPIO_FN_KEYOUT2, NULL);
555 gpio_request(GPIO_FN_KEYOUT3, NULL);
556 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
557 gpio_request(GPIO_FN_KEYIN0, NULL);
558 gpio_request(GPIO_FN_KEYIN1, NULL);
559 gpio_request(GPIO_FN_KEYIN2, NULL);
560 gpio_request(GPIO_FN_KEYIN3, NULL);
561 gpio_request(GPIO_FN_KEYIN4, NULL);
562 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
563
564 /* setup LCDC pins for SYS panel */
565 gpio_request(GPIO_FN_LCDD17, NULL);
566 gpio_request(GPIO_FN_LCDD16, NULL);
567 gpio_request(GPIO_FN_LCDD15, NULL);
568 gpio_request(GPIO_FN_LCDD14, NULL);
569 gpio_request(GPIO_FN_LCDD13, NULL);
570 gpio_request(GPIO_FN_LCDD12, NULL);
571 gpio_request(GPIO_FN_LCDD11, NULL);
572 gpio_request(GPIO_FN_LCDD10, NULL);
573 gpio_request(GPIO_FN_LCDD9, NULL);
574 gpio_request(GPIO_FN_LCDD8, NULL);
575 gpio_request(GPIO_FN_LCDD7, NULL);
576 gpio_request(GPIO_FN_LCDD6, NULL);
577 gpio_request(GPIO_FN_LCDD5, NULL);
578 gpio_request(GPIO_FN_LCDD4, NULL);
579 gpio_request(GPIO_FN_LCDD3, NULL);
580 gpio_request(GPIO_FN_LCDD2, NULL);
581 gpio_request(GPIO_FN_LCDD1, NULL);
582 gpio_request(GPIO_FN_LCDD0, NULL);
583 gpio_request(GPIO_FN_LCDRS, NULL); /* LCD_RS */
584 gpio_request(GPIO_FN_LCDCS, NULL); /* LCD_CS/ */
585 gpio_request(GPIO_FN_LCDRD, NULL); /* LCD_RD/ */
586 gpio_request(GPIO_FN_LCDWR, NULL); /* LCD_WR/ */
587 gpio_request(GPIO_FN_LCDVSYN, NULL); /* LCD_VSYNC */
588 gpio_request(GPIO_PTE4, NULL); /* LCD_RST/ */
589 gpio_direction_output(GPIO_PTE4, 1);
590 gpio_request(GPIO_PTF4, NULL); /* PROTECT/ */
591 gpio_direction_output(GPIO_PTF4, 1);
592 gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */
593 gpio_direction_output(GPIO_PTU0, 1);
594
595 /* setup USB function */
596 if (kfr2r09_usb0_gadget_setup() == 0)
597 platform_device_register(&kfr2r09_usb0_gadget_device);
598
599 /* CEU */
600 gpio_request(GPIO_FN_VIO_CKO, NULL);
601 gpio_request(GPIO_FN_VIO0_CLK, NULL);
602 gpio_request(GPIO_FN_VIO0_VD, NULL);
603 gpio_request(GPIO_FN_VIO0_HD, NULL);
604 gpio_request(GPIO_FN_VIO0_FLD, NULL);
605 gpio_request(GPIO_FN_VIO0_D7, NULL);
606 gpio_request(GPIO_FN_VIO0_D6, NULL);
607 gpio_request(GPIO_FN_VIO0_D5, NULL);
608 gpio_request(GPIO_FN_VIO0_D4, NULL);
609 gpio_request(GPIO_FN_VIO0_D3, NULL);
610 gpio_request(GPIO_FN_VIO0_D2, NULL);
611 gpio_request(GPIO_FN_VIO0_D1, NULL);
612 gpio_request(GPIO_FN_VIO0_D0, NULL);
613
614 platform_resource_setup_memory(&kfr2r09_ceu_device, "ceu", 4 << 20);
615
616 /* SDHI0 connected to yc304 */
617 gpio_request(GPIO_FN_SDHI0CD, NULL);
618 gpio_request(GPIO_FN_SDHI0D3, NULL);
619 gpio_request(GPIO_FN_SDHI0D2, NULL);
620 gpio_request(GPIO_FN_SDHI0D1, NULL);
621 gpio_request(GPIO_FN_SDHI0D0, NULL);
622 gpio_request(GPIO_FN_SDHI0CMD, NULL);
623 gpio_request(GPIO_FN_SDHI0CLK, NULL);
624
625 return platform_add_devices(kfr2r09_devices,
626 ARRAY_SIZE(kfr2r09_devices));
627}
628device_initcall(kfr2r09_devices_setup);
629
630/* Return the board specific boot mode pin configuration */
631static int kfr2r09_mode_pins(void)
632{
633 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
634 * MD3=0: 16-bit Area0 Bus Width
635 * MD5=1: Little Endian
636 * MD8=1: Test Mode Disabled
637 */
638 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5 | MODE_PIN8;
639}
640
641/*
642 * The Machine Vector
643 */
644static struct sh_machine_vector mv_kfr2r09 __initmv = {
645 .mv_name = "kfr2r09",
646 .mv_mode_pins = kfr2r09_mode_pins,
647};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 23:19:44 -0500