diff options
Diffstat (limited to 'arch/sh/boards/mach-dreamcast')
-rw-r--r-- | arch/sh/boards/mach-dreamcast/Makefile | 6 | ||||
-rw-r--r-- | arch/sh/boards/mach-dreamcast/irq.c | 153 | ||||
-rw-r--r-- | arch/sh/boards/mach-dreamcast/rtc.c | 81 | ||||
-rw-r--r-- | arch/sh/boards/mach-dreamcast/setup.c | 64 |
4 files changed, 304 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-dreamcast/Makefile b/arch/sh/boards/mach-dreamcast/Makefile new file mode 100644 index 000000000000..7b97546c7e5f --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/Makefile | |||
@@ -0,0 +1,6 @@ | |||
1 | # | ||
2 | # Makefile for the Sega Dreamcast specific parts of the kernel | ||
3 | # | ||
4 | |||
5 | obj-y := setup.o irq.o rtc.o | ||
6 | |||
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c new file mode 100644 index 000000000000..67bdc33dd411 --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/irq.c | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * arch/sh/boards/dreamcast/irq.c | ||
3 | * | ||
4 | * Holly IRQ support for the Sega Dreamcast. | ||
5 | * | ||
6 | * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> | ||
7 | * | ||
8 | * This file is part of the LinuxDC project (www.linuxdc.org) | ||
9 | * Released under the terms of the GNU GPL v2.0 | ||
10 | */ | ||
11 | |||
12 | #include <linux/irq.h> | ||
13 | #include <asm/io.h> | ||
14 | #include <asm/irq.h> | ||
15 | #include <mach/sysasic.h> | ||
16 | |||
17 | /* Dreamcast System ASIC Hardware Events - | ||
18 | |||
19 | The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving | ||
20 | hardware events from system peripherals and triggering an SH7750 IRQ. | ||
21 | Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are | ||
22 | set in the Event Mask Registers (EMRs). When a hardware event is | ||
23 | triggered, it's corresponding bit in the Event Status Registers (ESRs) | ||
24 | is set, and that bit should be rewritten to the ESR to acknowledge that | ||
25 | event. | ||
26 | |||
27 | There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event | ||
28 | types can be found in include/asm-sh/dreamcast/sysasic.h. There are three | ||
29 | groups of EMRs that parallel the ESRs. Each EMR group corresponds to an | ||
30 | IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 | ||
31 | triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. | ||
32 | |||
33 | In the kernel, these events are mapped to virtual IRQs so that drivers can | ||
34 | respond to them as they would a normal interrupt. In order to keep this | ||
35 | mapping simple, the events are mapped as: | ||
36 | |||
37 | 6900/6910 - Events 0-31, IRQ 13 | ||
38 | 6904/6924 - Events 32-63, IRQ 11 | ||
39 | 6908/6938 - Events 64-95, IRQ 9 | ||
40 | |||
41 | */ | ||
42 | |||
43 | #define ESR_BASE 0x005f6900 /* Base event status register */ | ||
44 | #define EMR_BASE 0x005f6910 /* Base event mask register */ | ||
45 | |||
46 | /* Helps us determine the EMR group that this event belongs to: 0 = 0x6910, | ||
47 | 1 = 0x6920, 2 = 0x6930; also determine the event offset */ | ||
48 | #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) | ||
49 | |||
50 | /* Return the hardware event's bit positon within the EMR/ESR */ | ||
51 | #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) | ||
52 | |||
53 | /* For each of these *_irq routines, the IRQ passed in is the virtual IRQ | ||
54 | (logically mapped to the corresponding bit for the hardware event). */ | ||
55 | |||
56 | /* Disable the hardware event by masking its bit in its EMR */ | ||
57 | static inline void disable_systemasic_irq(unsigned int irq) | ||
58 | { | ||
59 | __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); | ||
60 | __u32 mask; | ||
61 | |||
62 | mask = inl(emr); | ||
63 | mask &= ~(1 << EVENT_BIT(irq)); | ||
64 | outl(mask, emr); | ||
65 | } | ||
66 | |||
67 | /* Enable the hardware event by setting its bit in its EMR */ | ||
68 | static inline void enable_systemasic_irq(unsigned int irq) | ||
69 | { | ||
70 | __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); | ||
71 | __u32 mask; | ||
72 | |||
73 | mask = inl(emr); | ||
74 | mask |= (1 << EVENT_BIT(irq)); | ||
75 | outl(mask, emr); | ||
76 | } | ||
77 | |||
78 | /* Acknowledge a hardware event by writing its bit back to its ESR */ | ||
79 | static void ack_systemasic_irq(unsigned int irq) | ||
80 | { | ||
81 | __u32 esr = ESR_BASE + (LEVEL(irq) << 2); | ||
82 | disable_systemasic_irq(irq); | ||
83 | outl((1 << EVENT_BIT(irq)), esr); | ||
84 | } | ||
85 | |||
86 | /* After a IRQ has been ack'd and responded to, it needs to be renabled */ | ||
87 | static void end_systemasic_irq(unsigned int irq) | ||
88 | { | ||
89 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
90 | enable_systemasic_irq(irq); | ||
91 | } | ||
92 | |||
93 | static unsigned int startup_systemasic_irq(unsigned int irq) | ||
94 | { | ||
95 | enable_systemasic_irq(irq); | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | static void shutdown_systemasic_irq(unsigned int irq) | ||
101 | { | ||
102 | disable_systemasic_irq(irq); | ||
103 | } | ||
104 | |||
105 | struct hw_interrupt_type systemasic_int = { | ||
106 | .typename = "System ASIC", | ||
107 | .startup = startup_systemasic_irq, | ||
108 | .shutdown = shutdown_systemasic_irq, | ||
109 | .enable = enable_systemasic_irq, | ||
110 | .disable = disable_systemasic_irq, | ||
111 | .ack = ack_systemasic_irq, | ||
112 | .end = end_systemasic_irq, | ||
113 | }; | ||
114 | |||
115 | /* | ||
116 | * Map the hardware event indicated by the processor IRQ to a virtual IRQ. | ||
117 | */ | ||
118 | int systemasic_irq_demux(int irq) | ||
119 | { | ||
120 | __u32 emr, esr, status, level; | ||
121 | __u32 j, bit; | ||
122 | |||
123 | switch (irq) { | ||
124 | case 13: | ||
125 | level = 0; | ||
126 | break; | ||
127 | case 11: | ||
128 | level = 1; | ||
129 | break; | ||
130 | case 9: | ||
131 | level = 2; | ||
132 | break; | ||
133 | default: | ||
134 | return irq; | ||
135 | } | ||
136 | emr = EMR_BASE + (level << 4) + (level << 2); | ||
137 | esr = ESR_BASE + (level << 2); | ||
138 | |||
139 | /* Mask the ESR to filter any spurious, unwanted interrupts */ | ||
140 | status = inl(esr); | ||
141 | status &= inl(emr); | ||
142 | |||
143 | /* Now scan and find the first set bit as the event to map */ | ||
144 | for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { | ||
145 | if (status & bit) { | ||
146 | irq = HW_EVENT_IRQ_BASE + j + (level << 5); | ||
147 | return irq; | ||
148 | } | ||
149 | } | ||
150 | |||
151 | /* Not reached */ | ||
152 | return irq; | ||
153 | } | ||
diff --git a/arch/sh/boards/mach-dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c new file mode 100644 index 000000000000..a7433685798d --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/rtc.c | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * arch/sh/boards/dreamcast/rtc.c | ||
3 | * | ||
4 | * Dreamcast AICA RTC routines. | ||
5 | * | ||
6 | * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> | ||
7 | * Copyright (c) 2002 Paul Mundt <lethal@chaoticdreams.org> | ||
8 | * | ||
9 | * Released under the terms of the GNU GPL v2.0. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #include <linux/time.h> | ||
14 | #include <asm/rtc.h> | ||
15 | #include <asm/io.h> | ||
16 | |||
17 | /* The AICA RTC has an Epoch of 1/1/1950, so we must subtract 20 years (in | ||
18 | seconds) to get the standard Unix Epoch when getting the time, and add | ||
19 | 20 years when setting the time. */ | ||
20 | #define TWENTY_YEARS ((20 * 365LU + 5) * 86400) | ||
21 | |||
22 | /* The AICA RTC is represented by a 32-bit seconds counter stored in 2 16-bit | ||
23 | registers.*/ | ||
24 | #define AICA_RTC_SECS_H 0xa0710000 | ||
25 | #define AICA_RTC_SECS_L 0xa0710004 | ||
26 | |||
27 | /** | ||
28 | * aica_rtc_gettimeofday - Get the time from the AICA RTC | ||
29 | * @ts: pointer to resulting timespec | ||
30 | * | ||
31 | * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch. | ||
32 | */ | ||
33 | static void aica_rtc_gettimeofday(struct timespec *ts) | ||
34 | { | ||
35 | unsigned long val1, val2; | ||
36 | |||
37 | do { | ||
38 | val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | | ||
39 | (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); | ||
40 | |||
41 | val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | | ||
42 | (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); | ||
43 | } while (val1 != val2); | ||
44 | |||
45 | ts->tv_sec = val1 - TWENTY_YEARS; | ||
46 | |||
47 | /* Can't get nanoseconds with just a seconds counter. */ | ||
48 | ts->tv_nsec = 0; | ||
49 | } | ||
50 | |||
51 | /** | ||
52 | * aica_rtc_settimeofday - Set the AICA RTC to the current time | ||
53 | * @secs: contains the time_t to set | ||
54 | * | ||
55 | * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter. | ||
56 | */ | ||
57 | static int aica_rtc_settimeofday(const time_t secs) | ||
58 | { | ||
59 | unsigned long val1, val2; | ||
60 | unsigned long adj = secs + TWENTY_YEARS; | ||
61 | |||
62 | do { | ||
63 | ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); | ||
64 | ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L); | ||
65 | |||
66 | val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | | ||
67 | (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); | ||
68 | |||
69 | val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | | ||
70 | (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); | ||
71 | } while (val1 != val2); | ||
72 | |||
73 | return 0; | ||
74 | } | ||
75 | |||
76 | void aica_time_init(void) | ||
77 | { | ||
78 | rtc_sh_get_time = aica_rtc_gettimeofday; | ||
79 | rtc_sh_set_time = aica_rtc_settimeofday; | ||
80 | } | ||
81 | |||
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c new file mode 100644 index 000000000000..7d944fc75e93 --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/setup.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * arch/sh/boards/dreamcast/setup.c | ||
3 | * | ||
4 | * Hardware support for the Sega Dreamcast. | ||
5 | * | ||
6 | * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@linuxdc.org> | ||
7 | * Copyright (c) 2002, 2003, 2004 Paul Mundt <lethal@linux-sh.org> | ||
8 | * | ||
9 | * This file is part of the LinuxDC project (www.linuxdc.org) | ||
10 | * | ||
11 | * Released under the terms of the GNU GPL v2.0. | ||
12 | * | ||
13 | * This file originally bore the message (with enclosed-$): | ||
14 | * Id: setup_dc.c,v 1.5 2001/05/24 05:09:16 mrbrown Exp | ||
15 | * SEGA Dreamcast support | ||
16 | */ | ||
17 | |||
18 | #include <linux/sched.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/param.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/init.h> | ||
23 | #include <linux/irq.h> | ||
24 | #include <linux/device.h> | ||
25 | #include <asm/io.h> | ||
26 | #include <asm/irq.h> | ||
27 | #include <asm/rtc.h> | ||
28 | #include <asm/machvec.h> | ||
29 | #include <mach/sysasic.h> | ||
30 | |||
31 | extern struct hw_interrupt_type systemasic_int; | ||
32 | extern void aica_time_init(void); | ||
33 | extern int gapspci_init(void); | ||
34 | extern int systemasic_irq_demux(int); | ||
35 | |||
36 | static void __init dreamcast_setup(char **cmdline_p) | ||
37 | { | ||
38 | int i; | ||
39 | |||
40 | /* Mask all hardware events */ | ||
41 | /* XXX */ | ||
42 | |||
43 | /* Acknowledge any previous events */ | ||
44 | /* XXX */ | ||
45 | |||
46 | __set_io_port_base(0xa0000000); | ||
47 | |||
48 | /* Assign all virtual IRQs to the System ASIC int. handler */ | ||
49 | for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) | ||
50 | irq_desc[i].chip = &systemasic_int; | ||
51 | |||
52 | board_time_init = aica_time_init; | ||
53 | |||
54 | #ifdef CONFIG_PCI | ||
55 | if (gapspci_init() < 0) | ||
56 | printk(KERN_WARNING "GAPSPCI was not detected.\n"); | ||
57 | #endif | ||
58 | } | ||
59 | |||
60 | static struct sh_machine_vector mv_dreamcast __initmv = { | ||
61 | .mv_name = "Sega Dreamcast", | ||
62 | .mv_setup = dreamcast_setup, | ||
63 | .mv_irq_demux = systemasic_irq_demux, | ||
64 | }; | ||