aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/boards/board-ap325rxa.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/boards/board-ap325rxa.c')
-rw-r--r--arch/sh/boards/board-ap325rxa.c138
1 files changed, 101 insertions, 37 deletions
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index fd1612590bf4..7c7874e6ac36 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -18,11 +18,13 @@
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/smc911x.h> 20#include <linux/smc911x.h>
21#include <linux/gpio.h>
21#include <media/soc_camera_platform.h> 22#include <media/soc_camera_platform.h>
22#include <media/sh_mobile_ceu.h> 23#include <media/sh_mobile_ceu.h>
23#include <asm/sh_mobile_lcdc.h> 24#include <video/sh_mobile_lcdc.h>
24#include <asm/io.h> 25#include <asm/io.h>
25#include <asm/clock.h> 26#include <asm/clock.h>
27#include <cpu/sh7723.h>
26 28
27static struct smc911x_platdata smc911x_info = { 29static struct smc911x_platdata smc911x_info = {
28 .flags = SMC911X_USE_32BIT, 30 .flags = SMC911X_USE_32BIT,
@@ -52,20 +54,33 @@ static struct platform_device smc9118_device = {
52 }, 54 },
53}; 55};
54 56
57/*
58 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
59 * If this area erased, this board can not boot.
60 */
55static struct mtd_partition ap325rxa_nor_flash_partitions[] = { 61static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
56 { 62 {
57 .name = "uboot", 63 .name = "uboot",
58 .offset = 0, 64 .offset = 0,
59 .size = (1 * 1024 * 1024), 65 .size = (1 * 1024 * 1024),
60 .mask_flags = MTD_WRITEABLE, /* Read-only */ 66 .mask_flags = MTD_WRITEABLE, /* Read-only */
67 }, {
68 .name = "kernel",
69 .offset = MTDPART_OFS_APPEND,
70 .size = (2 * 1024 * 1024),
71 }, {
72 .name = "free-area0",
73 .offset = MTDPART_OFS_APPEND,
74 .size = ((7 * 1024 * 1024) + (512 * 1024)),
61 }, { 75 }, {
62 .name = "kernel", 76 .name = "CPLD-Data",
63 .offset = MTDPART_OFS_APPEND, 77 .offset = MTDPART_OFS_APPEND,
64 .size = (2 * 1024 * 1024), 78 .mask_flags = MTD_WRITEABLE, /* Read-only */
79 .size = (1024 * 128 * 2),
65 }, { 80 }, {
66 .name = "other", 81 .name = "free-area1",
67 .offset = MTDPART_OFS_APPEND, 82 .offset = MTDPART_OFS_APPEND,
68 .size = MTDPART_SIZ_FULL, 83 .size = MTDPART_SIZ_FULL,
69 }, 84 },
70}; 85};
71 86
@@ -96,17 +111,7 @@ static struct platform_device ap325rxa_nor_flash_device = {
96#define FPGA_LCDREG 0xB4100180 111#define FPGA_LCDREG 0xB4100180
97#define FPGA_BKLREG 0xB4100212 112#define FPGA_BKLREG 0xB4100212
98#define FPGA_LCDREG_VAL 0x0018 113#define FPGA_LCDREG_VAL 0x0018
99#define PORT_PHCR 0xA405010E
100#define PORT_PLCR 0xA4050114
101#define PORT_PMCR 0xA4050116
102#define PORT_PRCR 0xA405011C
103#define PORT_PSCR 0xA405011E
104#define PORT_PZCR 0xA405014C
105#define PORT_HIZCRA 0xA4050158
106#define PORT_MSELCRB 0xA4050182 114#define PORT_MSELCRB 0xA4050182
107#define PORT_PSDR 0xA405013E
108#define PORT_PZDR 0xA405016C
109#define PORT_PSELD 0xA4050154
110 115
111static void ap320_wvga_power_on(void *board_data) 116static void ap320_wvga_power_on(void *board_data)
112{ 117{
@@ -116,8 +121,7 @@ static void ap320_wvga_power_on(void *board_data)
116 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); 121 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
117 122
118 /* backlight */ 123 /* backlight */
119 ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); 124 gpio_set_value(GPIO_PTS3, 0);
120 ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR);
121 ctrl_outw(0x100, FPGA_BKLREG); 125 ctrl_outw(0x100, FPGA_BKLREG);
122} 126}
123 127
@@ -281,12 +285,84 @@ static struct platform_device *ap325rxa_devices[] __initdata = {
281}; 285};
282 286
283static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 287static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
288 {
289 I2C_BOARD_INFO("pcf8563", 0x51),
290 },
284}; 291};
285 292
286static int __init ap325rxa_devices_setup(void) 293static int __init ap325rxa_devices_setup(void)
287{ 294{
288 clk_always_enable("mstp200"); /* LCDC */ 295 /* LD3 and LD4 LEDs */
289 clk_always_enable("mstp203"); /* CEU */ 296 gpio_request(GPIO_PTX5, NULL); /* RUN */
297 gpio_direction_output(GPIO_PTX5, 1);
298 gpio_export(GPIO_PTX5, 0);
299
300 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
301 gpio_direction_output(GPIO_PTX4, 0);
302 gpio_export(GPIO_PTX4, 0);
303
304 /* SW1 input */
305 gpio_request(GPIO_PTF7, NULL); /* MODE */
306 gpio_direction_input(GPIO_PTF7);
307 gpio_export(GPIO_PTF7, 0);
308
309 /* LCDC */
310 clk_always_enable("mstp200");
311 gpio_request(GPIO_FN_LCDD15, NULL);
312 gpio_request(GPIO_FN_LCDD14, NULL);
313 gpio_request(GPIO_FN_LCDD13, NULL);
314 gpio_request(GPIO_FN_LCDD12, NULL);
315 gpio_request(GPIO_FN_LCDD11, NULL);
316 gpio_request(GPIO_FN_LCDD10, NULL);
317 gpio_request(GPIO_FN_LCDD9, NULL);
318 gpio_request(GPIO_FN_LCDD8, NULL);
319 gpio_request(GPIO_FN_LCDD7, NULL);
320 gpio_request(GPIO_FN_LCDD6, NULL);
321 gpio_request(GPIO_FN_LCDD5, NULL);
322 gpio_request(GPIO_FN_LCDD4, NULL);
323 gpio_request(GPIO_FN_LCDD3, NULL);
324 gpio_request(GPIO_FN_LCDD2, NULL);
325 gpio_request(GPIO_FN_LCDD1, NULL);
326 gpio_request(GPIO_FN_LCDD0, NULL);
327 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
328 gpio_request(GPIO_FN_LCDDCK, NULL);
329 gpio_request(GPIO_FN_LCDVEPWC, NULL);
330 gpio_request(GPIO_FN_LCDVCPWC, NULL);
331 gpio_request(GPIO_FN_LCDVSYN, NULL);
332 gpio_request(GPIO_FN_LCDHSYN, NULL);
333 gpio_request(GPIO_FN_LCDDISP, NULL);
334 gpio_request(GPIO_FN_LCDDON, NULL);
335
336 /* LCD backlight */
337 gpio_request(GPIO_PTS3, NULL);
338 gpio_direction_output(GPIO_PTS3, 1);
339
340 /* CEU */
341 clk_always_enable("mstp203");
342 gpio_request(GPIO_FN_VIO_CLK2, NULL);
343 gpio_request(GPIO_FN_VIO_VD2, NULL);
344 gpio_request(GPIO_FN_VIO_HD2, NULL);
345 gpio_request(GPIO_FN_VIO_FLD, NULL);
346 gpio_request(GPIO_FN_VIO_CKO, NULL);
347 gpio_request(GPIO_FN_VIO_D15, NULL);
348 gpio_request(GPIO_FN_VIO_D14, NULL);
349 gpio_request(GPIO_FN_VIO_D13, NULL);
350 gpio_request(GPIO_FN_VIO_D12, NULL);
351 gpio_request(GPIO_FN_VIO_D11, NULL);
352 gpio_request(GPIO_FN_VIO_D10, NULL);
353 gpio_request(GPIO_FN_VIO_D9, NULL);
354 gpio_request(GPIO_FN_VIO_D8, NULL);
355
356 gpio_request(GPIO_PTZ7, NULL);
357 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
358 gpio_request(GPIO_PTZ6, NULL);
359 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
360 gpio_request(GPIO_PTZ5, NULL);
361 gpio_direction_output(GPIO_PTZ5, 1); /* RST_CAM */
362 gpio_request(GPIO_PTZ4, NULL);
363 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
364
365 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
290 366
291 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 367 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
292 368
@@ -300,18 +376,6 @@ device_initcall(ap325rxa_devices_setup);
300 376
301static void __init ap325rxa_setup(char **cmdline_p) 377static void __init ap325rxa_setup(char **cmdline_p)
302{ 378{
303 /* LCDC configuration */
304 ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR);
305 ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR);
306 ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR);
307 ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR);
308 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA);
309
310 /* CEU */
311 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
312 ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD);
313 ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR);
314 ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR);
315} 379}
316 380
317static struct sh_machine_vector mv_ap325rxa __initmv = { 381static struct sh_machine_vector mv_ap325rxa __initmv = {