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-rw-r--r--arch/sh/boards/bigsur/irq.c334
1 files changed, 0 insertions, 334 deletions
diff --git a/arch/sh/boards/bigsur/irq.c b/arch/sh/boards/bigsur/irq.c
deleted file mode 100644
index 1ab04da36382..000000000000
--- a/arch/sh/boards/bigsur/irq.c
+++ /dev/null
@@ -1,334 +0,0 @@
1/*
2 *
3 * By Dustin McIntire (dustin@sensoria.com) (c)2001
4 *
5 * Setup and IRQ handling code for the HD64465 companion chip.
6 * by Greg Banks <gbanks@pocketpenguins.com>
7 * Copyright (c) 2000 PocketPenguins Inc
8 *
9 * Derived from setup_hd64465.c which bore the message:
10 * Greg Banks <gbanks@pocketpenguins.com>
11 * Copyright (c) 2000 PocketPenguins Inc and
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 * and setup_cqreek.c which bore message:
14 * Copyright (C) 2000 Niibe Yutaka
15 *
16 * May be copied or modified under the terms of the GNU General Public
17 * License. See linux/COPYING for more information.
18 *
19 * IRQ functions for a Hitachi Big Sur Evaluation Board.
20 *
21 */
22#undef DEBUG
23
24#include <linux/sched.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/param.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/irq.h>
32#include <linux/bitops.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36
37#include <asm/bigsur/io.h>
38#include <asm/hd64465/hd64465.h>
39#include <asm/bigsur/bigsur.h>
40
41//#define BIGSUR_DEBUG 3
42#undef BIGSUR_DEBUG
43
44#ifdef BIGSUR_DEBUG
45#define DIPRINTK(n, args...) if (BIGSUR_DEBUG>(n)) printk(args)
46#else
47#define DIPRINTK(n, args...)
48#endif /* BIGSUR_DEBUG */
49
50#ifdef CONFIG_HD64465
51extern int hd64465_irq_demux(int irq);
52#endif /* CONFIG_HD64465 */
53
54
55/*===========================================================*/
56// Big Sur CPLD IRQ Routines
57/*===========================================================*/
58
59/* Level 1 IRQ routines */
60static void disable_bigsur_l1irq(unsigned int irq)
61{
62 unsigned char mask;
63 unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
64 unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
65
66 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
67 pr_debug("Disable L1 IRQ %d\n", irq);
68 DIPRINTK(2,"disable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
69 mask_port, bit);
70
71 /* Disable IRQ - set mask bit */
72 mask = inb(mask_port) | bit;
73 outb(mask, mask_port);
74 return;
75 }
76 pr_debug("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);
77}
78
79static void enable_bigsur_l1irq(unsigned int irq)
80{
81 unsigned char mask;
82 unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
83 unsigned char bit = (1 << ((irq - MGATE_IRQ_LOW)%8) );
84
85 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
86 pr_debug("Enable L1 IRQ %d\n", irq);
87 DIPRINTK(2,"enable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
88 mask_port, bit);
89 /* Enable L1 IRQ - clear mask bit */
90 mask = inb(mask_port) & ~bit;
91 outb(mask, mask_port);
92 return;
93 }
94 pr_debug("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);
95}
96
97
98/* Level 2 irq masks and registers for L2 decoding */
99/* Level2 bitmasks for each level 1 IRQ */
100const u32 bigsur_l2irq_mask[] =
101 {0x40,0x80,0x08,0x01,0x01,0x3C,0x3E,0xFF,0x40,0x80,0x06,0x03};
102/* Level2 to ISR[n] map for each level 1 IRQ */
103const u32 bigsur_l2irq_reg[] =
104 { 2, 2, 3, 3, 1, 2, 1, 0, 1, 1, 3, 2};
105/* Level2 to Level 1 IRQ map */
106const u32 bigsur_l2_l1_map[] =
107 {7,7,7,7,7,7,7,7, 4,6,6,6,6,6,8,9, 11,11,5,5,5,5,0,1, 3,10,10,2,-1,-1,-1,-1};
108/* IRQ inactive level (high or low) */
109const u32 bigsur_l2_inactv_state[] = {0x00, 0xBE, 0xFC, 0xF7};
110
111/* CPLD external status and mask registers base and offsets */
112static const u32 isr_base = BIGSUR_IRQ0;
113static const u32 isr_offset = BIGSUR_IRQ0 - BIGSUR_IRQ1;
114static const u32 imr_base = BIGSUR_IMR0;
115static const u32 imr_offset = BIGSUR_IMR0 - BIGSUR_IMR1;
116
117#define REG_NUM(irq) ((irq-BIGSUR_2NDLVL_IRQ_LOW)/8 )
118
119/* Level 2 IRQ routines */
120static void disable_bigsur_l2irq(unsigned int irq)
121{
122 unsigned char mask;
123 unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
124 unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
125
126 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
127 pr_debug("Disable L2 IRQ %d\n", irq);
128 DIPRINTK(2,"disable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
129 mask_port, bit);
130
131 /* Disable L2 IRQ - set mask bit */
132 mask = inb(mask_port) | bit;
133 outb(mask, mask_port);
134 return;
135 }
136 pr_debug("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);
137}
138
139static void enable_bigsur_l2irq(unsigned int irq)
140{
141 unsigned char mask;
142 unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
143 unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
144
145 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
146 pr_debug("Enable L2 IRQ %d\n", irq);
147 DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
148 mask_port, bit);
149
150 /* Enable L2 IRQ - clear mask bit */
151 mask = inb(mask_port) & ~bit;
152 outb(mask, mask_port);
153 return;
154 }
155 pr_debug("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);
156}
157
158static void mask_and_ack_bigsur(unsigned int irq)
159{
160 pr_debug("mask_and_ack_bigsur IRQ %d\n", irq);
161 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
162 disable_bigsur_l1irq(irq);
163 else
164 disable_bigsur_l2irq(irq);
165}
166
167static void end_bigsur_irq(unsigned int irq)
168{
169 pr_debug("end_bigsur_irq IRQ %d\n", irq);
170 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
171 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
172 enable_bigsur_l1irq(irq);
173 else
174 enable_bigsur_l2irq(irq);
175 }
176}
177
178static unsigned int startup_bigsur_irq(unsigned int irq)
179{
180 u8 mask;
181 u32 reg;
182
183 pr_debug("startup_bigsur_irq IRQ %d\n", irq);
184
185 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
186 /* Enable the L1 IRQ */
187 enable_bigsur_l1irq(irq);
188 /* Enable all L2 IRQs in this L1 IRQ */
189 mask = ~(bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW]);
190 reg = imr_base - bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW] * imr_offset;
191 mask &= inb(reg);
192 outb(mask,reg);
193 DIPRINTK(2,"startup_bigsur_irq: IMR=0x%08x mask=0x%x\n",reg,inb(reg));
194 }
195 else {
196 /* Enable the L2 IRQ - clear mask bit */
197 enable_bigsur_l2irq(irq);
198 /* Enable the L1 bit masking this L2 IRQ */
199 enable_bigsur_l1irq(bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW]);
200 DIPRINTK(2,"startup_bigsur_irq: L1=%d L2=%d\n",
201 bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW],irq);
202 }
203 return 0;
204}
205
206static void shutdown_bigsur_irq(unsigned int irq)
207{
208 pr_debug("shutdown_bigsur_irq IRQ %d\n", irq);
209 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
210 disable_bigsur_l1irq(irq);
211 else
212 disable_bigsur_l2irq(irq);
213}
214
215/* Define the IRQ structures for the L1 and L2 IRQ types */
216static struct hw_interrupt_type bigsur_l1irq_type = {
217 .typename = "BigSur-CPLD-Level1-IRQ",
218 .startup = startup_bigsur_irq,
219 .shutdown = shutdown_bigsur_irq,
220 .enable = enable_bigsur_l1irq,
221 .disable = disable_bigsur_l1irq,
222 .ack = mask_and_ack_bigsur,
223 .end = end_bigsur_irq
224};
225
226static struct hw_interrupt_type bigsur_l2irq_type = {
227 .typename = "BigSur-CPLD-Level2-IRQ",
228 .startup = startup_bigsur_irq,
229 .shutdown =shutdown_bigsur_irq,
230 .enable = enable_bigsur_l2irq,
231 .disable = disable_bigsur_l2irq,
232 .ack = mask_and_ack_bigsur,
233 .end = end_bigsur_irq
234};
235
236
237static void make_bigsur_l1isr(unsigned int irq) {
238
239 /* sanity check first */
240 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
241 /* save the handler in the main description table */
242 irq_desc[irq].chip = &bigsur_l1irq_type;
243 irq_desc[irq].status = IRQ_DISABLED;
244 irq_desc[irq].action = 0;
245 irq_desc[irq].depth = 1;
246
247 disable_bigsur_l1irq(irq);
248 return;
249 }
250 pr_debug("make_bigsur_l1isr: bad irq, %d\n", irq);
251 return;
252}
253
254static void make_bigsur_l2isr(unsigned int irq) {
255
256 /* sanity check first */
257 if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
258 /* save the handler in the main description table */
259 irq_desc[irq].chip = &bigsur_l2irq_type;
260 irq_desc[irq].status = IRQ_DISABLED;
261 irq_desc[irq].action = 0;
262 irq_desc[irq].depth = 1;
263
264 disable_bigsur_l2irq(irq);
265 return;
266 }
267 pr_debug("make_bigsur_l2isr: bad irq, %d\n", irq);
268 return;
269}
270
271/* The IRQ's will be decoded as follows:
272 * If a level 2 handler exists and there is an unmasked active
273 * IRQ, the 2nd level handler will be called.
274 * If a level 2 handler does not exist for the active IRQ
275 * the 1st level handler will be called.
276 */
277
278int bigsur_irq_demux(int irq)
279{
280 int dmux_irq = irq;
281 u8 mask, actv_irqs;
282 u32 reg_num;
283
284 DIPRINTK(3,"bigsur_irq_demux, irq=%d\n", irq);
285 /* decode the 1st level IRQ */
286 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
287 /* Get corresponding L2 ISR bitmask and ISR number */
288 mask = bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW];
289 reg_num = bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW];
290 /* find the active IRQ's (XOR with inactive level)*/
291 actv_irqs = inb(isr_base-reg_num*isr_offset) ^
292 bigsur_l2_inactv_state[reg_num];
293 /* decode active IRQ's */
294 actv_irqs = actv_irqs & mask & ~(inb(imr_base-reg_num*imr_offset));
295 /* if NEZ then we have an active L2 IRQ */
296 if(actv_irqs) dmux_irq = ffz(~actv_irqs) + reg_num*8+BIGSUR_2NDLVL_IRQ_LOW;
297 /* if no 2nd level IRQ action, but has 1st level, use 1st level handler */
298 if(!irq_desc[dmux_irq].action && irq_desc[irq].action)
299 dmux_irq = irq;
300 DIPRINTK(1,"bigsur_irq_demux: irq=%d dmux_irq=%d mask=0x%04x reg=%d\n",
301 irq, dmux_irq, mask, reg_num);
302 }
303#ifdef CONFIG_HD64465
304 dmux_irq = hd64465_irq_demux(dmux_irq);
305#endif /* CONFIG_HD64465 */
306 DIPRINTK(3,"bigsur_irq_demux, demux_irq=%d\n", dmux_irq);
307
308 return dmux_irq;
309}
310
311/*===========================================================*/
312// Big Sur Init Routines
313/*===========================================================*/
314void __init init_bigsur_IRQ(void)
315{
316 int i;
317
318 if (!MACH_BIGSUR) return;
319
320 /* Create ISR's for Big Sur CPLD IRQ's */
321 /*==============================================================*/
322 for(i=BIGSUR_IRQ_LOW;i<BIGSUR_IRQ_HIGH;i++)
323 make_bigsur_l1isr(i);
324
325 printk(KERN_INFO "Big Sur CPLD L1 interrupts %d to %d.\n",
326 BIGSUR_IRQ_LOW,BIGSUR_IRQ_HIGH);
327
328 for(i=BIGSUR_2NDLVL_IRQ_LOW;i<BIGSUR_2NDLVL_IRQ_HIGH;i++)
329 make_bigsur_l2isr(i);
330
331 printk(KERN_INFO "Big Sur CPLD L2 interrupts %d to %d.\n",
332 BIGSUR_2NDLVL_IRQ_LOW,BIGSUR_2NDLVL_IRQ_HIGH);
333
334}
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