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-rw-r--r--arch/sh/Kconfig126
1 files changed, 84 insertions, 42 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index e7390dd0283d..586cd045e2db 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -15,6 +15,7 @@ config SUPERH
15 select HAVE_IOREMAP_PROT if MMU 15 select HAVE_IOREMAP_PROT if MMU
16 select HAVE_ARCH_TRACEHOOK 16 select HAVE_ARCH_TRACEHOOK
17 select HAVE_DMA_API_DEBUG 17 select HAVE_DMA_API_DEBUG
18 select RTC_LIB
18 help 19 help
19 The SuperH is a RISC processor targeted for use in embedded systems 20 The SuperH is a RISC processor targeted for use in embedded systems
20 and consumer electronics; it was also used in the Sega Dreamcast 21 and consumer electronics; it was also used in the Sega Dreamcast
@@ -74,14 +75,18 @@ config GENERIC_IOMAP
74 bool 75 bool
75 76
76config GENERIC_TIME 77config GENERIC_TIME
77 def_bool n 78 def_bool y
78 79
79config GENERIC_CLOCKEVENTS 80config GENERIC_CLOCKEVENTS
80 def_bool n 81 def_bool y
81 82
82config GENERIC_CLOCKEVENTS_BROADCAST 83config GENERIC_CLOCKEVENTS_BROADCAST
83 bool 84 bool
84 85
86config GENERIC_CMOS_UPDATE
87 def_bool y
88 depends on SH_SH03 || SH_DREAMCAST
89
85config GENERIC_LOCKBREAK 90config GENERIC_LOCKBREAK
86 def_bool y 91 def_bool y
87 depends on SMP && PREEMPT 92 depends on SMP && PREEMPT
@@ -112,6 +117,12 @@ config SYS_SUPPORTS_PCI
112config SYS_SUPPORTS_CMT 117config SYS_SUPPORTS_CMT
113 bool 118 bool
114 119
120config SYS_SUPPORTS_MTU2
121 bool
122
123config SYS_SUPPORTS_TMU
124 bool
125
115config STACKTRACE_SUPPORT 126config STACKTRACE_SUPPORT
116 def_bool y 127 def_bool y
117 128
@@ -157,13 +168,14 @@ config CPU_SH3
157 bool 168 bool
158 select CPU_HAS_INTEVT 169 select CPU_HAS_INTEVT
159 select CPU_HAS_SR_RB 170 select CPU_HAS_SR_RB
171 select SYS_SUPPORTS_TMU
160 172
161config CPU_SH4 173config CPU_SH4
162 bool 174 bool
163 select CPU_HAS_INTEVT 175 select CPU_HAS_INTEVT
164 select CPU_HAS_SR_RB 176 select CPU_HAS_SR_RB
165 select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
166 select CPU_HAS_FPU if !CPU_SH4AL_DSP 177 select CPU_HAS_FPU if !CPU_SH4AL_DSP
178 select SYS_SUPPORTS_TMU
167 179
168config CPU_SH4A 180config CPU_SH4A
169 bool 181 bool
@@ -177,6 +189,7 @@ config CPU_SH4AL_DSP
177config CPU_SH5 189config CPU_SH5
178 bool 190 bool
179 select CPU_HAS_FPU 191 select CPU_HAS_FPU
192 select SYS_SUPPORTS_TMU
180 193
181config CPU_SHX2 194config CPU_SHX2
182 bool 195 bool
@@ -210,27 +223,32 @@ config CPU_SUBTYPE_SH7201
210 bool "Support SH7201 processor" 223 bool "Support SH7201 processor"
211 select CPU_SH2A 224 select CPU_SH2A
212 select CPU_HAS_FPU 225 select CPU_HAS_FPU
226 select SYS_SUPPORTS_MTU2
213 227
214config CPU_SUBTYPE_SH7203 228config CPU_SUBTYPE_SH7203
215 bool "Support SH7203 processor" 229 bool "Support SH7203 processor"
216 select CPU_SH2A 230 select CPU_SH2A
217 select CPU_HAS_FPU 231 select CPU_HAS_FPU
218 select SYS_SUPPORTS_CMT 232 select SYS_SUPPORTS_CMT
233 select SYS_SUPPORTS_MTU2
219 234
220config CPU_SUBTYPE_SH7206 235config CPU_SUBTYPE_SH7206
221 bool "Support SH7206 processor" 236 bool "Support SH7206 processor"
222 select CPU_SH2A 237 select CPU_SH2A
223 select SYS_SUPPORTS_CMT 238 select SYS_SUPPORTS_CMT
239 select SYS_SUPPORTS_MTU2
224 240
225config CPU_SUBTYPE_SH7263 241config CPU_SUBTYPE_SH7263
226 bool "Support SH7263 processor" 242 bool "Support SH7263 processor"
227 select CPU_SH2A 243 select CPU_SH2A
228 select CPU_HAS_FPU 244 select CPU_HAS_FPU
229 select SYS_SUPPORTS_CMT 245 select SYS_SUPPORTS_CMT
246 select SYS_SUPPORTS_MTU2
230 247
231config CPU_SUBTYPE_MXG 248config CPU_SUBTYPE_MXG
232 bool "Support MX-G processor" 249 bool "Support MX-G processor"
233 select CPU_SH2A 250 select CPU_SH2A
251 select SYS_SUPPORTS_MTU2
234 help 252 help
235 Select MX-G if running on an R8A03022BG part. 253 Select MX-G if running on an R8A03022BG part.
236 254
@@ -283,6 +301,7 @@ config CPU_SUBTYPE_SH7720
283 bool "Support SH7720 processor" 301 bool "Support SH7720 processor"
284 select CPU_SH3 302 select CPU_SH3
285 select CPU_HAS_DSP 303 select CPU_HAS_DSP
304 select SYS_SUPPORTS_CMT
286 help 305 help
287 Select SH7720 if you have a SH3-DSP SH7720 CPU. 306 Select SH7720 if you have a SH3-DSP SH7720 CPU.
288 307
@@ -290,6 +309,7 @@ config CPU_SUBTYPE_SH7721
290 bool "Support SH7721 processor" 309 bool "Support SH7721 processor"
291 select CPU_SH3 310 select CPU_SH3
292 select CPU_HAS_DSP 311 select CPU_HAS_DSP
312 select SYS_SUPPORTS_CMT
293 help 313 help
294 Select SH7721 if you have a SH3-DSP SH7721 CPU. 314 Select SH7721 if you have a SH3-DSP SH7721 CPU.
295 315
@@ -347,6 +367,16 @@ config CPU_SUBTYPE_SH7723
347 help 367 help
348 Select SH7723 if you have an SH-MobileR2 CPU. 368 Select SH7723 if you have an SH-MobileR2 CPU.
349 369
370config CPU_SUBTYPE_SH7724
371 bool "Support SH7724 processor"
372 select CPU_SH4A
373 select CPU_SHX2
374 select ARCH_SHMOBILE
375 select ARCH_SPARSEMEM_ENABLE
376 select SYS_SUPPORTS_CMT
377 help
378 Select SH7724 if you have an SH-MobileR2R CPU.
379
350config CPU_SUBTYPE_SH7763 380config CPU_SUBTYPE_SH7763
351 bool "Support SH7763 processor" 381 bool "Support SH7763 processor"
352 select CPU_SH4A 382 select CPU_SH4A
@@ -442,48 +472,26 @@ source "arch/sh/boards/Kconfig"
442 472
443menu "Timer and clock configuration" 473menu "Timer and clock configuration"
444 474
445config SH_TMU 475config SH_TIMER_TMU
446 bool "TMU timer support" 476 bool "TMU timer driver"
447 depends on CPU_SH3 || CPU_SH4 477 depends on SYS_SUPPORTS_TMU
448 default y 478 default y
449 select GENERIC_TIME
450 select GENERIC_CLOCKEVENTS
451 help 479 help
452 This enables the use of the TMU as the system timer. 480 This enables the build of the TMU timer driver.
453 481
454config SH_CMT 482config SH_TIMER_CMT
455 bool "CMT timer support" 483 bool "CMT timer driver"
456 depends on SYS_SUPPORTS_CMT && CPU_SH2 484 depends on SYS_SUPPORTS_CMT
457 default y 485 default y
458 help 486 help
459 This enables the use of the CMT as the system timer. 487 This enables build of the CMT timer driver.
460 488
461# 489config SH_TIMER_MTU2
462# Support for the new-style CMT driver. This will replace SH_CMT 490 bool "MTU2 timer driver"
463# once its other dependencies are merged. 491 depends on SYS_SUPPORTS_MTU2
464#
465config SH_TIMER_CMT
466 bool "CMT clockevents driver"
467 depends on SYS_SUPPORTS_CMT && !SH_CMT
468 select GENERIC_CLOCKEVENTS
469
470config SH_MTU2
471 bool "MTU2 timer support"
472 depends on CPU_SH2A
473 default y 492 default y
474 help 493 help
475 This enables the use of the MTU2 as the system timer. 494 This enables build of the MTU2 timer driver.
476
477config SH_TIMER_IRQ
478 int
479 default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
480 CPU_SUBTYPE_SH7763
481 default "86" if CPU_SUBTYPE_SH7619
482 default "140" if CPU_SUBTYPE_SH7206
483 default "142" if CPU_SUBTYPE_SH7203 && SH_CMT
484 default "153" if CPU_SUBTYPE_SH7203 && SH_MTU2
485 default "238" if CPU_SUBTYPE_MXG
486 default "16"
487 495
488config SH_PCLK_FREQ 496config SH_PCLK_FREQ
489 int "Peripheral clock frequency (in Hz)" 497 int "Peripheral clock frequency (in Hz)"
@@ -494,7 +502,7 @@ config SH_PCLK_FREQ
494 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \ 502 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
495 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \ 503 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
496 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \ 504 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
497 CPU_SUBTYPE_SH7786 505 CPU_SUBTYPE_SH7786 || CPU_SUBTYPE_SH7724
498 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R 506 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
499 default "66000000" if CPU_SUBTYPE_SH4_202 507 default "66000000" if CPU_SUBTYPE_SH4_202
500 default "50000000" 508 default "50000000"
@@ -503,6 +511,13 @@ config SH_PCLK_FREQ
503 This is necessary for determining the reference clock value on 511 This is necessary for determining the reference clock value on
504 platforms lacking an RTC. 512 platforms lacking an RTC.
505 513
514config SH_CLK_CPG
515 def_bool y
516
517config SH_CLK_CPG_LEGACY
518 depends on SH_CLK_CPG
519 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
520
506config SH_CLK_MD 521config SH_CLK_MD
507 int "CPU Mode Pin Setting" 522 int "CPU Mode Pin Setting"
508 depends on CPU_SH2 523 depends on CPU_SH2
@@ -663,27 +678,54 @@ config GUSA_RB
663 LLSC, this should be more efficient than the other alternative of 678 LLSC, this should be more efficient than the other alternative of
664 disabling interrupts around the atomic sequence. 679 disabling interrupts around the atomic sequence.
665 680
681config SPARSE_IRQ
682 bool "Support sparse irq numbering"
683 depends on EXPERIMENTAL
684 help
685 This enables support for sparse irqs. This is useful in general
686 as most CPUs have a fairly sparse array of IRQ vectors, which
687 the irq_desc then maps directly on to. Systems with a high
688 number of off-chip IRQs will want to treat this as
689 experimental until they have been independently verified.
690
691 If you don't know what to do here, say N.
692
666endmenu 693endmenu
667 694
668menu "Boot options" 695menu "Boot options"
669 696
670config ZERO_PAGE_OFFSET 697config ZERO_PAGE_OFFSET
671 hex "Zero page offset" 698 hex
672 default "0x00004000" if SH_SH03 699 default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
673 default "0x00010000" if PAGE_SIZE_64KB 700 SH_7751_SOLUTION_ENGINE
701 default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
674 default "0x00002000" if PAGE_SIZE_8KB 702 default "0x00002000" if PAGE_SIZE_8KB
675 default "0x00001000" 703 default "0x00001000"
676 help 704 help
677 This sets the default offset of zero page. 705 This sets the default offset of zero page.
678 706
679config BOOT_LINK_OFFSET 707config BOOT_LINK_OFFSET
680 hex "Link address offset for booting" 708 hex
709 default "0x00210000" if SH_SHMIN
710 default "0x00400000" if SH_CAYMAN
711 default "0x00810000" if SH_7780_SOLUTION_ENGINE
712 default "0x009e0000" if SH_TITAN
713 default "0x01800000" if SH_SDK7780
714 default "0x02000000" if SH_EDOSK7760
681 default "0x00800000" 715 default "0x00800000"
682 help 716 help
683 This option allows you to set the link address offset of the zImage. 717 This option allows you to set the link address offset of the zImage.
684 This can be useful if you are on a board which has a small amount of 718 This can be useful if you are on a board which has a small amount of
685 memory. 719 memory.
686 720
721config ENTRY_OFFSET
722 hex
723 default "0x00001000" if PAGE_SIZE_4KB
724 default "0x00002000" if PAGE_SIZE_8KB
725 default "0x00004000" if PAGE_SIZE_16KB
726 default "0x00010000" if PAGE_SIZE_64KB
727 default "0x00000000"
728
687config UBC_WAKEUP 729config UBC_WAKEUP
688 bool "Wakeup UBC on startup" 730 bool "Wakeup UBC on startup"
689 depends on CPU_SH4 && !CPU_SH4A 731 depends on CPU_SH4 && !CPU_SH4A