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-rw-r--r--arch/s390/kernel/time.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 9e7b039458da..87be655557aa 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -724,7 +724,7 @@ static void clock_sync_cpu(struct clock_sync_data *sync)
724} 724}
725 725
726/* 726/*
727 * Sync the TOD clock using the port refered to by aibp. This port 727 * Sync the TOD clock using the port referred to by aibp. This port
728 * has to be enabled and the other port has to be disabled. The 728 * has to be enabled and the other port has to be disabled. The
729 * last eacr update has to be more than 1.6 seconds in the past. 729 * last eacr update has to be more than 1.6 seconds in the past.
730 */ 730 */
@@ -1012,7 +1012,7 @@ static void etr_work_fn(struct work_struct *work)
1012 eacr = etr_handle_update(&aib, eacr); 1012 eacr = etr_handle_update(&aib, eacr);
1013 1013
1014 /* 1014 /*
1015 * Select ports to enable. The prefered synchronization mode is PPS. 1015 * Select ports to enable. The preferred synchronization mode is PPS.
1016 * If a port can be enabled depends on a number of things: 1016 * If a port can be enabled depends on a number of things:
1017 * 1) The port needs to be online and uptodate. A port is not 1017 * 1) The port needs to be online and uptodate. A port is not
1018 * disabled just because it is not uptodate, but it is only 1018 * disabled just because it is not uptodate, but it is only
@@ -1091,7 +1091,7 @@ static void etr_work_fn(struct work_struct *work)
1091 /* 1091 /*
1092 * Update eacr and try to synchronize the clock. If the update 1092 * Update eacr and try to synchronize the clock. If the update
1093 * of eacr caused a stepping port switch (or if we have to 1093 * of eacr caused a stepping port switch (or if we have to
1094 * assume that a stepping port switch has occured) or the 1094 * assume that a stepping port switch has occurred) or the
1095 * clock syncing failed, reset the sync check control bit 1095 * clock syncing failed, reset the sync check control bit
1096 * and set up a timer to try again after 0.5 seconds 1096 * and set up a timer to try again after 0.5 seconds
1097 */ 1097 */