1 files changed, 69 insertions, 73 deletions

diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
index f72d611f7e13..e3bffd4e2d66 100644
--- a/arch/s390/include/asm/sigp.h
+++ b/arch/s390/include/asm/sigp.h
@@ -1,24 +1,19 @@
 /*
- *  include/asm-s390/sigp.h
+ *  Routines and structures for signalling other processors.
  *
- *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com)
- *               Heiko Carstens (heiko.carstens@de.ibm.com)
- *
- *  sigp.h by D.J. Barrow (c) IBM 1999
- *  contains routines / structures for signalling other S/390 processors in an
- *  SMP configuration.
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Denis Joseph Barrow,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  */
 
-#ifndef __SIGP__
-#define __SIGP__
+#ifndef __ASM_SIGP_H
+#define __ASM_SIGP_H
 
 #include <asm/system.h>
 
-/* get real cpu address from logical cpu number */
-extern int __cpu_logical_map[];
+/* Get real cpu address from logical cpu number. */
+extern unsigned short __cpu_logical_map[];
 
 static inline int cpu_logical_map(int cpu)
 {
@@ -29,107 +24,108 @@ static inline int cpu_logical_map(int cpu)
 #endif
 }
 
-typedef enum
-{
-        sigp_unassigned=0x0,
-        sigp_sense,
-        sigp_external_call,
-        sigp_emergency_signal,
-        sigp_start,
-        sigp_stop,
-        sigp_restart,
-        sigp_unassigned1,
-        sigp_unassigned2,
-        sigp_stop_and_store_status,
-        sigp_unassigned3,
-        sigp_initial_cpu_reset,
-        sigp_cpu_reset,
-        sigp_set_prefix,
-        sigp_store_status_at_address,
-        sigp_store_extended_status_at_address
-} sigp_order_code;
-
-typedef __u32 sigp_status_word;
-
-typedef enum
-{
-        sigp_order_code_accepted=0,
-        sigp_status_stored,
-        sigp_busy,
-        sigp_not_operational
-} sigp_ccode;
-
+enum {
+        sigp_sense = 1,
+        sigp_external_call = 2,
+        sigp_emergency_signal = 3,
+        sigp_start = 4,
+        sigp_stop = 5,
+        sigp_restart = 6,
+        sigp_stop_and_store_status = 9,
+        sigp_initial_cpu_reset = 11,
+        sigp_cpu_reset = 12,
+        sigp_set_prefix = 13,
+        sigp_store_status_at_address = 14,
+        sigp_store_extended_status_at_address = 15,
+        sigp_set_architecture = 18,
+        sigp_conditional_emergency_signal = 19,
+        sigp_sense_running = 21,
+};
+
+enum {
+        sigp_order_code_accepted = 0,
+        sigp_status_stored = 1,
+        sigp_busy = 2,
+        sigp_not_operational = 3,
+};
 
 /*
- * Definitions for the external call
+ * Definitions for external call.
  */
-
-/* 'Bit' signals, asynchronous */
-typedef enum
-{
-        ec_schedule=0,
+enum {
+        ec_schedule = 0,
         ec_call_function,
         ec_call_function_single,
-        ec_bit_last
-} ec_bit_sig;
+};
 
 /*
- * Signal processor
+ * Signal processor.
  */
-static inline sigp_ccode
-signal_processor(__u16 cpu_addr, sigp_order_code order_code)
+static inline int raw_sigp(u16 cpu, int order)
 {
         register unsigned long reg1 asm ("1") = 0;
-        sigp_ccode ccode;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 :       "=d"    (ccode)
-                : "d" (reg1), "d" (cpu_logical_map(cpu_addr)),
-                  "a" (order_code) : "cc" , "memory");
+                : "d" (reg1), "d" (cpu),
+                  "a" (order) : "cc" , "memory");
         return ccode;
 }
 
 /*
- * Signal processor with parameter
+ * Signal processor with parameter.
  */
-static inline sigp_ccode
-signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
+static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
 {
         register unsigned int reg1 asm ("1") = parameter;
-        sigp_ccode ccode;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 : "=d" (ccode)
-                : "d" (reg1), "d" (cpu_logical_map(cpu_addr)),
-                  "a" (order_code) : "cc" , "memory");
+                : "d" (reg1), "d" (cpu),
+                  "a" (order) : "cc" , "memory");
         return ccode;
 }
 
 /*
- * Signal processor with parameter and return status
+ * Signal processor with parameter and return status.
  */
-static inline sigp_ccode
-signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
-                    sigp_order_code order_code)
+static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
 {
-        register unsigned int reg1 asm ("1") = parameter;
-        sigp_ccode ccode;
+        register unsigned int reg1 asm ("1") = parm;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 : "=d" (ccode), "+d" (reg1)
-                : "d" (cpu_logical_map(cpu_addr)), "a" (order_code)
+                : "d" (cpu), "a" (order)
                 : "cc" , "memory");
-        *statusptr = reg1;
+        *status = reg1;
         return ccode;
 }
 
-#endif /* __SIGP__ */
+static inline int sigp(int cpu, int order)
+{
+        return raw_sigp(cpu_logical_map(cpu), order);
+}
+
+static inline int sigp_p(u32 parameter, int cpu, int order)
+{
+        return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
+}
+
+static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
+{
+        return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
+}
+
+#endif /* __ASM_SIGP_H */