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-rw-r--r--arch/ppc/Kconfig47
-rw-r--r--arch/ppc/platforms/Makefile3
-rw-r--r--arch/ppc/platforms/fads.h2
-rw-r--r--arch/ppc/platforms/mpc8272ads_setup.c236
-rw-r--r--arch/ppc/platforms/mpc866ads_setup.c273
-rw-r--r--arch/ppc/platforms/mpc885ads_setup.c389
-rw-r--r--arch/ppc/platforms/pq2ads.h4
-rw-r--r--arch/ppc/platforms/pq2ads_pd.h114
8 files changed, 1067 insertions, 1 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 11899f06bf06..54a0a9bb12dd 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -481,6 +481,53 @@ config WINCEPT
481 481
482endchoice 482endchoice
483 483
484menu "Freescale Ethernet driver platform-specific options"
485 depends on FS_ENET
486
487 config MPC8xx_SECOND_ETH
488 bool "Second Ethernet channel"
489 depends on (MPC885ADS || MPC86XADS)
490 default y
491 help
492 This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
493 The latter will use SCC1, for 885ADS you can select it below.
494
495 choice
496 prompt "Second Ethernet channel"
497 depends on MPC8xx_SECOND_ETH
498 default MPC8xx_SECOND_ETH_FEC2
499
500 config MPC8xx_SECOND_ETH_FEC2
501 bool "FEC2"
502 depends on MPC885ADS
503 help
504 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
505 (often 2-nd UART) will not work if this is enabled.
506
507 config MPC8xx_SECOND_ETH_SCC1
508 bool "SCC1"
509 depends on MPC86XADS
510 select MPC8xx_SCC_ENET_FIXED
511 help
512 Enable SCC1 to serve as 2-nd Ethernet channel. Note that SMC1
513 (often 1-nd UART) will not work if this is enabled.
514
515 config MPC8xx_SECOND_ETH_SCC3
516 bool "SCC3"
517 depends on MPC885ADS
518 help
519 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
520 (often 1-nd UART) will not work if this is enabled.
521
522 endchoice
523
524 config MPC8xx_SCC_ENET_FIXED
525 depends on MPC8xx_SECOND_ETH_SCC
526 default n
527 bool "Use fixed MII-less mode for SCC Ethernet"
528
529endmenu
530
484choice 531choice
485 prompt "Machine Type" 532 prompt "Machine Type"
486 depends on 6xx || POWER3 533 depends on 6xx || POWER3
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 51430e294b32..e8b91a33ce91 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
37obj-$(CONFIG_SPRUCE) += spruce.o 37obj-$(CONFIG_SPRUCE) += spruce.o
38obj-$(CONFIG_LITE5200) += lite5200.o 38obj-$(CONFIG_LITE5200) += lite5200.o
39obj-$(CONFIG_EV64360) += ev64360.o 39obj-$(CONFIG_EV64360) += ev64360.o
40obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
41obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
42obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
40 43
41ifeq ($(CONFIG_SMP),y) 44ifeq ($(CONFIG_SMP),y)
42obj-$(CONFIG_PPC_CHRP) += chrp_smp.o 45obj-$(CONFIG_PPC_CHRP) += chrp_smp.o
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
index a48fb8d723e4..e1c0b1b6dcb3 100644
--- a/arch/ppc/platforms/fads.h
+++ b/arch/ppc/platforms/fads.h
@@ -112,7 +112,7 @@
112 112
113/* CPM Ethernet through SCC1 or SCC2 */ 113/* CPM Ethernet through SCC1 or SCC2 */
114 114
115#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */ 115#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */
116/* Bits in parallel I/O port registers that have to be set/cleared 116/* Bits in parallel I/O port registers that have to be set/cleared
117 * to configure the pins for SCC1 use. 117 * to configure the pins for SCC1 use.
118 * TCLK - CLK1, RCLK - CLK2. 118 * TCLK - CLK1, RCLK - CLK2.
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
new file mode 100644
index 000000000000..bc9b94f77e39
--- /dev/null
+++ b/arch/ppc/platforms/mpc8272ads_setup.c
@@ -0,0 +1,236 @@
1/*
2 * arch/ppc/platforms/82xx/pq2ads_pd.c
3 *
4 * MPC82xx Board-specific PlatformDevice descriptions
5 *
6 * 2005 (c) MontaVista Software, Inc.
7 * Vitaly Bordug <vbordug@ru.mvista.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/device.h>
18#include <linux/ioport.h>
19#include <linux/fs_enet_pd.h>
20#include <linux/platform_device.h>
21
22#include <asm/io.h>
23#include <asm/mpc8260.h>
24#include <asm/cpm2.h>
25#include <asm/immap_cpm2.h>
26#include <asm/irq.h>
27#include <asm/ppc_sys.h>
28#include <asm/ppcboot.h>
29
30#include "pq2ads_pd.h"
31
32static void init_fcc1_ioports(void);
33static void init_fcc2_ioports(void);
34
35static struct fs_mii_bus_info mii_bus_info = {
36 .method = fsmii_bitbang,
37 .id = 0,
38 .i.bitbang = {
39 .mdio_port = fsiop_portc,
40 .mdio_bit = 18,
41 .mdc_port = fsiop_portc,
42 .mdc_bit = 19,
43 .delay = 1,
44 },
45};
46
47static struct fs_platform_info mpc82xx_fcc1_pdata = {
48 .fs_no = fsid_fcc1,
49 .cp_page = CPM_CR_FCC1_PAGE,
50 .cp_block = CPM_CR_FCC1_SBLOCK,
51 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
52 .clk_route = CMX1_CLK_ROUTE,
53 .clk_mask = CMX1_CLK_MASK,
54 .init_ioports = init_fcc1_ioports,
55
56 .phy_addr = 0,
57#ifdef PHY_INTERRUPT
58 .phy_irq = PHY_INTERRUPT,
59#else
60 .phy_irq = -1;
61#endif
62 .mem_offset = FCC1_MEM_OFFSET,
63 .bus_info = &mii_bus_info,
64 .rx_ring = 32,
65 .tx_ring = 32,
66 .rx_copybreak = 240,
67 .use_napi = 0,
68 .napi_weight = 17,
69};
70
71static struct fs_platform_info mpc82xx_fcc2_pdata = {
72 .fs_no = fsid_fcc2,
73 .cp_page = CPM_CR_FCC2_PAGE,
74 .cp_block = CPM_CR_FCC2_SBLOCK,
75 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
76 .clk_route = CMX2_CLK_ROUTE,
77 .clk_mask = CMX2_CLK_MASK,
78 .init_ioports = init_fcc2_ioports,
79
80 .phy_addr = 3,
81#ifdef PHY_INTERRUPT
82 .phy_irq = PHY_INTERRUPT,
83#else
84 .phy_irq = -1;
85#endif
86 .mem_offset = FCC2_MEM_OFFSET,
87 .bus_info = &mii_bus_info,
88 .rx_ring = 32,
89 .tx_ring = 32,
90 .rx_copybreak = 240,
91 .use_napi = 0,
92 .napi_weight = 17,
93};
94
95static void init_fcc1_ioports(void)
96{
97 struct io_port *io;
98 u32 tempval;
99 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
100 u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
101
102 io = &immap->im_ioport;
103
104 /* Enable the PHY */
105 clrbits32(bcsr, BCSR1_FETHIEN);
106 setbits32(bcsr, BCSR1_FETH_RST);
107
108 /* FCC1 pins are on port A/C. */
109 /* Configure port A and C pins for FCC1 Ethernet. */
110
111 tempval = in_be32(&io->iop_pdira);
112 tempval &= ~PA1_DIRA0;
113 tempval |= PA1_DIRA1;
114 out_be32(&io->iop_pdira, tempval);
115
116 tempval = in_be32(&io->iop_psora);
117 tempval &= ~PA1_PSORA0;
118 tempval |= PA1_PSORA1;
119 out_be32(&io->iop_psora, tempval);
120
121 setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
122
123 /* Alter clocks */
124 tempval = PC_F1TXCLK|PC_F1RXCLK;
125
126 clrbits32(&io->iop_psorc, tempval);
127 clrbits32(&io->iop_pdirc, tempval);
128 setbits32(&io->iop_pparc, tempval);
129
130 clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
131 setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
132 iounmap(bcsr);
133 iounmap(immap);
134}
135
136static void init_fcc2_ioports(void)
137{
138 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
139 u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
140
141 struct io_port *io;
142 u32 tempval;
143
144 immap = cpm2_immr;
145
146 io = &immap->im_ioport;
147
148 /* Enable the PHY */
149 clrbits32(bcsr, BCSR3_FETHIEN2);
150 setbits32(bcsr, BCSR3_FETH2_RST);
151
152 /* FCC2 are port B/C. */
153 /* Configure port A and C pins for FCC2 Ethernet. */
154
155 tempval = in_be32(&io->iop_pdirb);
156 tempval &= ~PB2_DIRB0;
157 tempval |= PB2_DIRB1;
158 out_be32(&io->iop_pdirb, tempval);
159
160 tempval = in_be32(&io->iop_psorb);
161 tempval &= ~PB2_PSORB0;
162 tempval |= PB2_PSORB1;
163 out_be32(&io->iop_psorb, tempval);
164
165 setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
166
167 tempval = PC_F2RXCLK|PC_F2TXCLK;
168
169 /* Alter clocks */
170 clrbits32(&io->iop_psorc,tempval);
171 clrbits32(&io->iop_pdirc,tempval);
172 setbits32(&io->iop_pparc,tempval);
173
174 clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
175 setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
176
177 iounmap(bcsr);
178 iounmap(immap);
179}
180
181
182static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
183 int idx)
184{
185 bd_t* bi = (void*)__res;
186 int fs_no = fsid_fcc1+pdev->id-1;
187
188 mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
189 mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
190
191 switch(fs_no) {
192 case fsid_fcc1:
193 memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
194 pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
195 break;
196 case fsid_fcc2:
197 memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
198 mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
199 pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
200 break;
201 }
202}
203
204static int mpc8272ads_platform_notify(struct device *dev)
205{
206 static const struct platform_notify_dev_map dev_map[] = {
207 {
208 .bus_id = "fsl-cpm-fcc",
209 .rtn = mpc8272ads_fixup_enet_pdata
210 },
211 {
212 .bus_id = NULL
213 }
214 };
215 platform_notify_map(dev_map,dev);
216
217 return 0;
218
219}
220
221int __init mpc8272ads_init(void)
222{
223 printk(KERN_NOTICE "mpc8272ads: Init\n");
224
225 platform_notify = mpc8272ads_platform_notify;
226
227 ppc_sys_device_initfunc();
228
229 ppc_sys_device_disable_all();
230 ppc_sys_device_enable(MPC82xx_CPM_FCC1);
231 ppc_sys_device_enable(MPC82xx_CPM_FCC2);
232
233 return 0;
234}
235
236arch_initcall(mpc8272ads_init);
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
new file mode 100644
index 000000000000..ac8fcc68afeb
--- /dev/null
+++ b/arch/ppc/platforms/mpc866ads_setup.c
@@ -0,0 +1,273 @@
1/*arch/ppc/platforms/mpc885ads-setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/ioport.h>
20#include <linux/device.h>
21
22#include <linux/fs_enet_pd.h>
23#include <linux/mii.h>
24
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/time.h>
32#include <asm/ppcboot.h>
33#include <asm/8xx_immap.h>
34#include <asm/commproc.h>
35#include <asm/ppc_sys.h>
36#include <asm/mpc8xx.h>
37
38extern unsigned char __res[];
39
40static struct fs_mii_bus_info fec_mii_bus_info = {
41 .method = fsmii_fec,
42 .id = 0,
43};
44
45static struct fs_mii_bus_info scc_mii_bus_info = {
46 .method = fsmii_fixed,
47 .id = 0,
48 .i.fixed.speed = 10,
49 .i.fixed.duplex = 0,
50};
51
52static struct fs_platform_info mpc8xx_fec_pdata[] = {
53 {
54 .rx_ring = 128,
55 .tx_ring = 16,
56 .rx_copybreak = 240,
57
58 .use_napi = 1,
59 .napi_weight = 17,
60
61 .phy_addr = 15,
62 .phy_irq = -1,
63
64 .use_rmii = 0,
65
66 .bus_info = &fec_mii_bus_info,
67 }
68};
69
70static struct fs_platform_info mpc8xx_scc_pdata = {
71 .rx_ring = 64,
72 .tx_ring = 8,
73 .rx_copybreak = 240,
74
75 .use_napi = 1,
76 .napi_weight = 17,
77
78 .phy_addr = -1,
79 .phy_irq = -1,
80
81 .bus_info = &scc_mii_bus_info,
82};
83
84void __init board_init(void)
85{
86 volatile cpm8xx_t *cp = cpmp;
87 unsigned *bcsr_io;
88
89 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
90
91 if (bcsr_io == NULL) {
92 printk(KERN_CRIT "Could not remap BCSR1\n");
93 return;
94 }
95#ifdef CONFIG_SERIAL_CPM_SMC1
96 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
97 clrbits32(bcsr_io,(0x80000000 >> 7));
98#else
99 setbits32(bcsr_io,(0x80000000 >> 7));
100
101 cp->cp_pbpar &= ~(0x000000c0);
102 cp->cp_pbdir |= 0x000000c0;
103 cp->cp_smc[0].smc_smcmr = 0;
104 cp->cp_smc[0].smc_smce = 0;
105#endif
106
107#ifdef CONFIG_SERIAL_CPM_SMC2
108 cp->cp_simode &= ~(0xe0000000 >> 1);
109 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
110 clrbits32(bcsr_io,(0x80000000 >> 13));
111#else
112 clrbits32(bcsr_io,(0x80000000 >> 13));
113 cp->cp_pbpar &= ~(0x00000c00);
114 cp->cp_pbdir |= 0x00000c00;
115 cp->cp_smc[1].smc_smcmr = 0;
116 cp->cp_smc[1].smc_smce = 0;
117#endif
118 iounmap(bcsr_io);
119}
120
121static void setup_fec1_ioports(void)
122{
123 immap_t *immap = (immap_t *) IMAP_ADDR;
124
125 setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
126 setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
127}
128
129static void setup_scc1_ioports(void)
130{
131 immap_t *immap = (immap_t *) IMAP_ADDR;
132 unsigned *bcsr_io;
133
134 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
135
136 if (bcsr_io == NULL) {
137 printk(KERN_CRIT "Could not remap BCSR1\n");
138 return;
139 }
140
141 /* Enable the PHY.
142 */
143 clrbits32(bcsr_io,BCSR1_ETHEN);
144
145 /* Configure port A pins for Txd and Rxd.
146 */
147 /* Disable receive and transmit in case EPPC-Bug started it.
148 */
149 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
150 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
151 clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
152
153 /* Configure port C pins to enable CLSN and RENA.
154 */
155 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
156 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
157 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
158 /* Configure port A for TCLK and RCLK.
159 */
160 setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
161 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
162 clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
163 clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
164
165 /* Configure Serial Interface clock routing.
166 * First, clear all SCC bits to zero, then set the ones we want.
167 */
168 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
169 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
170
171 /* In the original SCC enet driver the following code is placed at
172 the end of the initialization */
173 setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
174 setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
175
176}
177
178static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
179{
180 struct fs_platform_info *fpi = pdev->dev.platform_data;
181
182 volatile cpm8xx_t *cp;
183 bd_t *bd = (bd_t *) __res;
184 char *e;
185 int i;
186
187 /* Get pointer to Communication Processor */
188 cp = cpmp;
189 switch (fs_no) {
190 case fsid_fec1:
191 fpi = &mpc8xx_fec_pdata[0];
192 fpi->init_ioports = &setup_fec1_ioports;
193
194 break;
195 case fsid_scc1:
196 fpi = &mpc8xx_scc_pdata;
197 fpi->init_ioports = &setup_scc1_ioports;
198
199 break;
200 default:
201 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
202 return;
203 }
204
205 pdev->dev.platform_data = fpi;
206 fpi->fs_no = fs_no;
207
208 e = (unsigned char *)&bd->bi_enetaddr;
209 for (i = 0; i < 6; i++)
210 fpi->macaddr[i] = *e++;
211
212 fpi->macaddr[5 - pdev->id]++;
213
214}
215
216static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
217 int idx)
218{
219 /* This is for FEC devices only */
220 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
221 return;
222 mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
223}
224
225static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
226 int idx)
227{
228 /* This is for SCC devices only */
229 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
230 return;
231
232 mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
233}
234
235static int mpc866ads_platform_notify(struct device *dev)
236{
237 static const struct platform_notify_dev_map dev_map[] = {
238 {
239 .bus_id = "fsl-cpm-fec",
240 .rtn = mpc866ads_fixup_fec_enet_pdata,
241 },
242 {
243 .bus_id = "fsl-cpm-scc",
244 .rtn = mpc866ads_fixup_scc_enet_pdata,
245 },
246 {
247 .bus_id = NULL
248 }
249 };
250
251 platform_notify_map(dev_map,dev);
252
253 return 0;
254}
255
256int __init mpc866ads_init(void)
257{
258 printk(KERN_NOTICE "mpc866ads: Init\n");
259
260 platform_notify = mpc866ads_platform_notify;
261
262 ppc_sys_device_initfunc();
263 ppc_sys_device_disable_all();
264
265#ifdef MPC8xx_SECOND_ETH_SCC1
266 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
267#endif
268 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
269
270 return 0;
271}
272
273arch_initcall(mpc866ads_init);
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
new file mode 100644
index 000000000000..50a99e5f7c68
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -0,0 +1,389 @@
1/*arch/ppc/platforms/mpc885ads-setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/ioport.h>
20#include <linux/device.h>
21
22#include <linux/fs_enet_pd.h>
23#include <linux/mii.h>
24
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/time.h>
32#include <asm/ppcboot.h>
33#include <asm/8xx_immap.h>
34#include <asm/commproc.h>
35#include <asm/ppc_sys.h>
36
37extern unsigned char __res[];
38
39static void __init mpc885ads_scc_phy_init(char);
40
41static struct fs_mii_bus_info fec_mii_bus_info = {
42 .method = fsmii_fec,
43 .id = 0,
44};
45
46static struct fs_mii_bus_info scc_mii_bus_info = {
47#ifdef CONFIG_SCC_ENET_8xx_FIXED
48 .method = fsmii_fixed,
49#else
50 .method = fsmii_fec,
51#endif
52
53 .id = 0,
54};
55
56static struct fs_platform_info mpc8xx_fec_pdata[] = {
57 {
58 .rx_ring = 128,
59 .tx_ring = 16,
60 .rx_copybreak = 240,
61
62 .use_napi = 1,
63 .napi_weight = 17,
64
65 .phy_addr = 0,
66 .phy_irq = SIU_IRQ7,
67
68 .bus_info = &fec_mii_bus_info,
69 }, {
70 .rx_ring = 128,
71 .tx_ring = 16,
72 .rx_copybreak = 240,
73
74 .use_napi = 1,
75 .napi_weight = 17,
76
77 .phy_addr = 1,
78 .phy_irq = SIU_IRQ7,
79
80 .bus_info = &fec_mii_bus_info,
81 }
82};
83
84static struct fs_platform_info mpc8xx_scc_pdata = {
85 .rx_ring = 64,
86 .tx_ring = 8,
87 .rx_copybreak = 240,
88
89 .use_napi = 1,
90 .napi_weight = 17,
91
92 .phy_addr = 2,
93#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
94 .phy_irq = -1,
95#else
96 .phy_irq = SIU_IRQ7,
97#endif
98
99 .bus_info = &scc_mii_bus_info,
100};
101
102void __init board_init(void)
103{
104 volatile cpm8xx_t *cp = cpmp;
105 unsigned int *bcsr_io;
106
107#ifdef CONFIG_FS_ENET
108 immap_t *immap = (immap_t *) IMAP_ADDR;
109#endif
110 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
111
112 if (bcsr_io == NULL) {
113 printk(KERN_CRIT "Could not remap BCSR\n");
114 return;
115 }
116#ifdef CONFIG_SERIAL_CPM_SMC1
117 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
118 clrbits32(bcsr_io, BCSR1_RS232EN_1);
119#else
120 setbits32(bcsr_io,BCSR1_RS232EN_1);
121 cp->cp_smc[0].smc_smcmr = 0;
122 cp->cp_smc[0].smc_smce = 0;
123#endif
124
125#ifdef CONFIG_SERIAL_CPM_SMC2
126 cp->cp_simode &= ~(0xe0000000 >> 1);
127 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
128 clrbits32(bcsr_io,BCSR1_RS232EN_2);
129#else
130 setbits32(bcsr_io,BCSR1_RS232EN_2);
131 cp->cp_smc[1].smc_smcmr = 0;
132 cp->cp_smc[1].smc_smce = 0;
133#endif
134 iounmap(bcsr_io);
135
136#ifdef CONFIG_FS_ENET
137 /* use MDC for MII (common) */
138 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
139 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
140#endif
141}
142
143static void setup_fec1_ioports(void)
144{
145 immap_t *immap = (immap_t *) IMAP_ADDR;
146
147 /* configure FEC1 pins */
148 setbits16(&immap->im_ioport.iop_papar, 0xf830);
149 setbits16(&immap->im_ioport.iop_padir, 0x0830);
150 clrbits16(&immap->im_ioport.iop_padir, 0xf000);
151 setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
152
153 clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
154 setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
155 clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
156 setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
157
158 setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
159 clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
160 clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
161}
162
163static void setup_fec2_ioports(void)
164{
165 immap_t *immap = (immap_t *) IMAP_ADDR;
166
167 /* configure FEC2 pins */
168 setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
169 setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
170 setbits32(&immap->im_cpm.cp_peso, 0x00037800);
171 clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
172 clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
173}
174
175static void setup_scc3_ioports(void)
176{
177 immap_t *immap = (immap_t *) IMAP_ADDR;
178 unsigned *bcsr_io;
179
180 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
181
182 if (bcsr_io == NULL) {
183 printk(KERN_CRIT "Could not remap BCSR\n");
184 return;
185 }
186
187 /* Enable the PHY.
188 */
189 setbits32(bcsr_io+4, BCSR4_ETH10_RST);
190 /* Configure port A pins for Txd and Rxd.
191 */
192 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
193 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
194
195 /* Configure port C pins to enable CLSN and RENA.
196 */
197 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
198 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
199 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
200
201 /* Configure port E for TCLK and RCLK.
202 */
203 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
204 clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
205 clrbits32(&immap->im_cpm.cp_pedir,
206 PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
207 clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
208 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
209
210 /* Configure Serial Interface clock routing.
211 * First, clear all SCC bits to zero, then set the ones we want.
212 */
213 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
214 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
215
216 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
217 */
218 immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
219 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
220 * by H/W setting after reset. SCC ethernet controller support only half duplex.
221 * This discrepancy of modes causes a lot of carrier lost errors.
222 */
223
224 /* In the original SCC enet driver the following code is placed at
225 the end of the initialization */
226 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
227 clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
228 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
229
230 setbits32(bcsr_io+1, BCSR1_ETHEN);
231 iounmap(bcsr_io);
232}
233
234static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
235{
236 struct fs_platform_info *fpi = pdev->dev.platform_data;
237
238 volatile cpm8xx_t *cp;
239 bd_t *bd = (bd_t *) __res;
240 char *e;
241 int i;
242
243 /* Get pointer to Communication Processor */
244 cp = cpmp;
245 switch (fs_no) {
246 case fsid_fec1:
247 fpi = &mpc8xx_fec_pdata[0];
248 fpi->init_ioports = &setup_fec1_ioports;
249 break;
250 case fsid_fec2:
251 fpi = &mpc8xx_fec_pdata[1];
252 fpi->init_ioports = &setup_fec2_ioports;
253 break;
254 case fsid_scc3:
255 fpi = &mpc8xx_scc_pdata;
256 fpi->init_ioports = &setup_scc3_ioports;
257 mpc885ads_scc_phy_init(fpi->phy_addr);
258 break;
259 default:
260 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
261 return;
262 }
263
264 pdev->dev.platform_data = fpi;
265 fpi->fs_no = fs_no;
266
267 e = (unsigned char *)&bd->bi_enetaddr;
268 for (i = 0; i < 6; i++)
269 fpi->macaddr[i] = *e++;
270
271 fpi->macaddr[5 - pdev->id]++;
272
273}
274
275static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
276 int idx)
277{
278 /* This is for FEC devices only */
279 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
280 return;
281 mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
282}
283
284static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
285 int idx)
286{
287 /* This is for SCC devices only */
288 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
289 return;
290
291 mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
292}
293
294/* SCC ethernet controller does not have MII management channel. FEC1 MII
295 * channel is used to communicate with the 10Mbit PHY.
296 */
297
298#define MII_ECNTRL_PINMUX 0x4
299#define FEC_ECNTRL_PINMUX 0x00000004
300#define FEC_RCNTRL_MII_MODE 0x00000004
301
302/* Make MII read/write commands.
303 */
304#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \
305 ((VAL) & 0xffff) | ((PHY_ADDR) << 23))
306
307static void mpc885ads_scc_phy_init(char phy_addr)
308{
309 volatile immap_t *immap;
310 volatile fec_t *fecp;
311 bd_t *bd;
312
313 bd = (bd_t *) __res;
314 immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
315 fecp = &(immap->im_cpm.cp_fec);
316
317 /* Enable MII pins of the FEC1
318 */
319 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
320 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
321 /* Set MII speed to 2.5 MHz
322 */
323 out_be32(&fecp->fec_mii_speed,
324 ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
325
326 /* Enable FEC pin MUX
327 */
328 setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
329 setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
330
331 out_be32(&fecp->fec_mii_data,
332 mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
333 udelay(100);
334 out_be32(&fecp->fec_mii_data,
335 mk_mii_write(MII_ADVERTISE,
336 ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
337 udelay(100);
338
339 /* Disable FEC MII settings
340 */
341 clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
342 clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
343 out_be32(&fecp->fec_mii_speed, 0);
344}
345
346static int mpc885ads_platform_notify(struct device *dev)
347{
348
349 static const struct platform_notify_dev_map dev_map[] = {
350 {
351 .bus_id = "fsl-cpm-fec",
352 .rtn = mpc885ads_fixup_fec_enet_pdata,
353 },
354 {
355 .bus_id = "fsl-cpm-scc",
356 .rtn = mpc885ads_fixup_scc_enet_pdata,
357 },
358 {
359 .bus_id = NULL
360 }
361 };
362
363 platform_notify_map(dev_map,dev);
364
365}
366
367int __init mpc885ads_init(void)
368{
369 printk(KERN_NOTICE "mpc885ads: Init\n");
370
371 platform_notify = mpc885ads_platform_notify;
372
373 ppc_sys_device_initfunc();
374 ppc_sys_device_disable_all();
375
376 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
377
378#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
379 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
380
381#endif
382#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
383 ppc_sys_device_enable(MPC8xx_CPM_FEC2);
384#endif
385
386 return 0;
387}
388
389arch_initcall(mpc885ads_init);
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index 067d9a5aebc1..6b26dd36c640 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -13,6 +13,10 @@
13 13
14#include <asm/ppcboot.h> 14#include <asm/ppcboot.h>
15 15
16#if defined(CONFIG_ADS8272)
17#define BOARD_CHIP_NAME "8272"
18#endif
19
16/* Memory map is configured by the PROM startup. 20/* Memory map is configured by the PROM startup.
17 * We just map a few things we need. The CSR is actually 4 byte-wide 21 * We just map a few things we need. The CSR is actually 4 byte-wide
18 * registers that can be accessed as 8-, 16-, or 32-bit values. 22 * registers that can be accessed as 8-, 16-, or 32-bit values.
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
new file mode 100644
index 000000000000..8f14a43eafec
--- /dev/null
+++ b/arch/ppc/platforms/pq2ads_pd.h
@@ -0,0 +1,114 @@
1#ifndef __PQ2ADS_PD_H
2#define __PQ2ADS_PD_H
3/*
4 * arch/ppc/platforms/82xx/pq2ads_pd.h
5 *
6 * Some defines for MPC82xx board-specific PlatformDevice descriptions
7 *
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
17 Can only choose from CLK9-12 */
18
19#define F1_RXCLK 11
20#define F1_TXCLK 10
21
22/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
23 Can only choose from CLK13-16 */
24#define F2_RXCLK 15
25#define F2_TXCLK 16
26
27/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
28 Can only choose from CLK13-16 */
29#define F3_RXCLK 13
30#define F3_TXCLK 14
31
32/* Automatically generates register configurations */
33#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
34
35#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
41
42#define PC_F1RXCLK PC_CLK(F1_RXCLK)
43#define PC_F1TXCLK PC_CLK(F1_TXCLK)
44#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
45#define CMX1_CLK_MASK ((uint)0xff000000)
46
47#define PC_F2RXCLK PC_CLK(F2_RXCLK)
48#define PC_F2TXCLK PC_CLK(F2_TXCLK)
49#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
50#define CMX2_CLK_MASK ((uint)0x00ff0000)
51
52#define PC_F3RXCLK PC_CLK(F3_RXCLK)
53#define PC_F3TXCLK PC_CLK(F3_TXCLK)
54#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
55#define CMX3_CLK_MASK ((uint)0x0000ff00)
56
57/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58 * but there is little variation among the choices.
59 */
60#define PA1_COL 0x00000001U
61#define PA1_CRS 0x00000002U
62#define PA1_TXER 0x00000004U
63#define PA1_TXEN 0x00000008U
64#define PA1_RXDV 0x00000010U
65#define PA1_RXER 0x00000020U
66#define PA1_TXDAT 0x00003c00U
67#define PA1_RXDAT 0x0003c000U
68#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
69#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
70 PA1_RXDV | PA1_RXER)
71#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
72#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
73
74
75/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76 * but there is little variation among the choices.
77 */
78#define PB2_TXER 0x00000001U
79#define PB2_RXDV 0x00000002U
80#define PB2_TXEN 0x00000004U
81#define PB2_RXER 0x00000008U
82#define PB2_COL 0x00000010U
83#define PB2_CRS 0x00000020U
84#define PB2_TXDAT 0x000003c0U
85#define PB2_RXDAT 0x00003c00U
86#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
87 PB2_RXER | PB2_RXDV | PB2_TXER)
88#define PB2_PSORB1 (PB2_TXEN)
89#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
90#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
91
92
93/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94 * but there is little variation among the choices.
95 */
96#define PB3_RXDV 0x00004000U
97#define PB3_RXER 0x00008000U
98#define PB3_TXER 0x00010000U
99#define PB3_TXEN 0x00020000U
100#define PB3_COL 0x00040000U
101#define PB3_CRS 0x00080000U
102#define PB3_TXDAT 0x0f000000U
103#define PB3_RXDAT 0x00f00000U
104#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
105 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
106#define PB3_PSORB1 0
107#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
108#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
109
110#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
113
114#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 23:02:09 -0500