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-rw-r--r--arch/ppc/kernel/misc.S22
-rw-r--r--arch/ppc/mm/fault.c2
-rw-r--r--arch/ppc/mm/mmu_decl.h4
-rw-r--r--arch/ppc/platforms/4xx/ebony.c2
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c2
-rw-r--r--arch/ppc/platforms/4xx/taishan.c2
6 files changed, 21 insertions, 13 deletions
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index a22e1f4d94c8..2b81e71d6b2d 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -224,7 +224,16 @@ _GLOBAL(_tlbia)
224 */ 224 */
225_GLOBAL(_tlbie) 225_GLOBAL(_tlbie)
226#if defined(CONFIG_40x) 226#if defined(CONFIG_40x)
227 /* We run the search with interrupts disabled because we have to change
228 * the PID and I don't want to preempt when that happens.
229 */
230 mfmsr r5
231 mfspr r6,SPRN_PID
232 wrteei 0
233 mtspr SPRN_PID,r4
227 tlbsx. r3, 0, r3 234 tlbsx. r3, 0, r3
235 mtspr SPRN_PID,r6
236 wrtee r5
228 bne 10f 237 bne 10f
229 sync 238 sync
230 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. 239 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
@@ -234,22 +243,21 @@ _GLOBAL(_tlbie)
234 isync 243 isync
23510: 24410:
236#elif defined(CONFIG_44x) 245#elif defined(CONFIG_44x)
237 mfspr r4,SPRN_MMUCR 246 mfspr r5,SPRN_MMUCR
238 mfspr r5,SPRN_PID /* Get PID */ 247 rlwimi r5,r4,0,24,31 /* Set TID */
239 rlwimi r4,r5,0,24,31 /* Set TID */
240 248
241 /* We have to run the search with interrupts disabled, even critical 249 /* We have to run the search with interrupts disabled, even critical
242 * and debug interrupts (in fact the only critical exceptions we have 250 * and debug interrupts (in fact the only critical exceptions we have
243 * are debug and machine check). Otherwise an interrupt which causes 251 * are debug and machine check). Otherwise an interrupt which causes
244 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ 252 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
245 mfmsr r5 253 mfmsr r4
246 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha 254 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
247 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l 255 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
248 andc r6,r5,r6 256 andc r6,r4,r6
249 mtmsr r6 257 mtmsr r6
250 mtspr SPRN_MMUCR,r4 258 mtspr SPRN_MMUCR,r5
251 tlbsx. r3, 0, r3 259 tlbsx. r3, 0, r3
252 mtmsr r5 260 mtmsr r4
253 bne 10f 261 bne 10f
254 sync 262 sync
255 /* There are only 64 TLB entries, so r3 < 64, 263 /* There are only 64 TLB entries, so r3 < 64,
diff --git a/arch/ppc/mm/fault.c b/arch/ppc/mm/fault.c
index 254c23b755e6..36c0e7529edb 100644
--- a/arch/ppc/mm/fault.c
+++ b/arch/ppc/mm/fault.c
@@ -227,7 +227,7 @@ good_area:
227 set_bit(PG_arch_1, &page->flags); 227 set_bit(PG_arch_1, &page->flags);
228 } 228 }
229 pte_update(ptep, 0, _PAGE_HWEXEC); 229 pte_update(ptep, 0, _PAGE_HWEXEC);
230 _tlbie(address); 230 _tlbie(address, mm->context.id);
231 pte_unmap_unlock(ptep, ptl); 231 pte_unmap_unlock(ptep, ptl);
232 up_read(&mm->mmap_sem); 232 up_read(&mm->mmap_sem);
233 return 0; 233 return 0;
diff --git a/arch/ppc/mm/mmu_decl.h b/arch/ppc/mm/mmu_decl.h
index 540f3292b229..f1d4f2109a99 100644
--- a/arch/ppc/mm/mmu_decl.h
+++ b/arch/ppc/mm/mmu_decl.h
@@ -54,12 +54,12 @@ extern unsigned int num_tlbcam_entries;
54#define mmu_mapin_ram() (0UL) 54#define mmu_mapin_ram() (0UL)
55 55
56#elif defined(CONFIG_4xx) 56#elif defined(CONFIG_4xx)
57#define flush_HPTE(X, va, pg) _tlbie(va) 57#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
58extern void MMU_init_hw(void); 58extern void MMU_init_hw(void);
59extern unsigned long mmu_mapin_ram(void); 59extern unsigned long mmu_mapin_ram(void);
60 60
61#elif defined(CONFIG_FSL_BOOKE) 61#elif defined(CONFIG_FSL_BOOKE)
62#define flush_HPTE(X, va, pg) _tlbie(va) 62#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
63extern void MMU_init_hw(void); 63extern void MMU_init_hw(void);
64extern unsigned long mmu_mapin_ram(void); 64extern unsigned long mmu_mapin_ram(void);
65extern void adjust_total_lowmem(void); 65extern void adjust_total_lowmem(void);
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index 05d7184d7e14..453643a0eeea 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -236,7 +236,7 @@ ebony_early_serial_map(void)
236 gen550_init(0, &port); 236 gen550_init(0, &port);
237 237
238 /* Purge TLB entry added in head_44x.S for early serial access */ 238 /* Purge TLB entry added in head_44x.S for early serial access */
239 _tlbie(UART0_IO_BASE); 239 _tlbie(UART0_IO_BASE, 0);
240#endif 240#endif
241 241
242 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); 242 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index fd0f971881d6..28a712cd4800 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -259,7 +259,7 @@ ocotea_early_serial_map(void)
259 gen550_init(0, &port); 259 gen550_init(0, &port);
260 260
261 /* Purge TLB entry added in head_44x.S for early serial access */ 261 /* Purge TLB entry added in head_44x.S for early serial access */
262 _tlbie(UART0_IO_BASE); 262 _tlbie(UART0_IO_BASE, 0);
263#endif 263#endif
264 264
265 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); 265 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
index 888c492b4a45..f6a0c6650f33 100644
--- a/arch/ppc/platforms/4xx/taishan.c
+++ b/arch/ppc/platforms/4xx/taishan.c
@@ -316,7 +316,7 @@ taishan_early_serial_map(void)
316 gen550_init(0, &port); 316 gen550_init(0, &port);
317 317
318 /* Purge TLB entry added in head_44x.S for early serial access */ 318 /* Purge TLB entry added in head_44x.S for early serial access */
319 _tlbie(UART0_IO_BASE); 319 _tlbie(UART0_IO_BASE, 0);
320#endif 320#endif
321 321
322 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); 322 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);