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-rw-r--r--arch/ppc/kernel/entry.S23
-rw-r--r--arch/ppc/kernel/misc.S9
-rw-r--r--arch/ppc/mm/44x_mmu.c1
3 files changed, 33 insertions, 0 deletions
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index fba7ca17a67e..b19bfef2034d 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -244,6 +244,13 @@ syscall_exit_cont:
244 andis. r10,r0,DBCR0_IC@h 244 andis. r10,r0,DBCR0_IC@h
245 bnel- load_dbcr0 245 bnel- load_dbcr0
246#endif 246#endif
247#ifdef CONFIG_44x
248 lis r4,icache_44x_need_flush@ha
249 lwz r5,icache_44x_need_flush@l(r4)
250 cmplwi cr0,r5,0
251 bne- 2f
2521:
253#endif /* CONFIG_44x */
247 stwcx. r0,0,r1 /* to clear the reservation */ 254 stwcx. r0,0,r1 /* to clear the reservation */
248 lwz r4,_LINK(r1) 255 lwz r4,_LINK(r1)
249 lwz r5,_CCR(r1) 256 lwz r5,_CCR(r1)
@@ -258,6 +265,12 @@ syscall_exit_cont:
258 mtspr SPRN_SRR1,r8 265 mtspr SPRN_SRR1,r8
259 SYNC 266 SYNC
260 RFI 267 RFI
268#ifdef CONFIG_44x
2692: li r7,0
270 iccci r0,r0
271 stw r7,icache_44x_need_flush@l(r4)
272 b 1b
273#endif /* CONFIG_44x */
261 274
26266: li r3,-ENOSYS 27566: li r3,-ENOSYS
263 b ret_from_syscall 276 b ret_from_syscall
@@ -679,6 +692,16 @@ resume_kernel:
679 692
680 /* interrupts are hard-disabled at this point */ 693 /* interrupts are hard-disabled at this point */
681restore: 694restore:
695#ifdef CONFIG_44x
696 lis r4,icache_44x_need_flush@ha
697 lwz r5,icache_44x_need_flush@l(r4)
698 cmplwi cr0,r5,0
699 beq+ 1f
700 li r6,0
701 iccci r0,r0
702 stw r6,icache_44x_need_flush@l(r4)
7031:
704#endif /* CONFIG_44x */
682 lwz r0,GPR0(r1) 705 lwz r0,GPR0(r1)
683 lwz r2,GPR2(r1) 706 lwz r2,GPR2(r1)
684 REST_4GPRS(3, r1) 707 REST_4GPRS(3, r1)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 2b81e71d6b2d..e0c850d85c53 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -499,12 +499,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
499 addi r3,r3,L1_CACHE_BYTES 499 addi r3,r3,L1_CACHE_BYTES
500 bdnz 0b 500 bdnz 0b
501 sync 501 sync
502#ifndef CONFIG_44x
503 /* We don't flush the icache on 44x. Those have a virtual icache
504 * and we don't have access to the virtual address here (it's
505 * not the page vaddr but where it's mapped in user space). The
506 * flushing of the icache on these is handled elsewhere, when
507 * a change in the address space occurs, before returning to
508 * user space
509 */
502 mtctr r4 510 mtctr r4
5031: icbi 0,r6 5111: icbi 0,r6
504 addi r6,r6,L1_CACHE_BYTES 512 addi r6,r6,L1_CACHE_BYTES
505 bdnz 1b 513 bdnz 1b
506 sync 514 sync
507 isync 515 isync
516#endif /* CONFIG_44x */
508 blr 517 blr
509 518
510/* 519/*
diff --git a/arch/ppc/mm/44x_mmu.c b/arch/ppc/mm/44x_mmu.c
index 0a0a0487b334..6536a25cfcb8 100644
--- a/arch/ppc/mm/44x_mmu.c
+++ b/arch/ppc/mm/44x_mmu.c
@@ -61,6 +61,7 @@ extern char etext[], _stext[];
61 */ 61 */
62unsigned int tlb_44x_index = 0; 62unsigned int tlb_44x_index = 0;
63unsigned int tlb_44x_hwater = 62; 63unsigned int tlb_44x_hwater = 62;
64int icache_44x_need_flush;
64 65
65/* 66/*
66 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem 67 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem