6 files changed, 40 insertions, 15 deletions

diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index b6a63a49a232..191a8def3bdb 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1449,3 +1449,5 @@ _GLOBAL(sys_call_table)
         .long sys_request_key           /* 270 */
         .long sys_keyctl
         .long sys_waitid
+        .long sys_ioprio_set
+        .long sys_ioprio_get
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index 334ef4150d92..6164a2b34733 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -606,9 +606,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
                 struct page *page = pfn_to_page(pfn);
                 if (!PageReserved(page)
                     && !test_bit(PG_arch_1, &page->flags)) {
-                        if (vma->vm_mm == current->active_mm)
+                        if (vma->vm_mm == current->active_mm) {
+#ifdef CONFIG_8xx
+                        /* On 8xx, cache control instructions (particularly 
+                         * "dcbst" from flush_dcache_icache) fault as write 
+                         * operation if there is an unpopulated TLB entry 
+                         * for the address in question. To workaround that, 
+                         * we invalidate the TLB here, thus avoiding dcbst 
+                         * misbehaviour.
+                         */
+                                _tlbie(address);
+#endif
                                 __flush_dcache_icache((void *) address);
-                        else
+                        } else
                                 flush_dcache_icache_page(page);
                         set_bit(PG_arch_1, &page->flags);
                 }
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
index f459ade1bd63..016a74649155 100644
--- a/arch/ppc/platforms/pmac_sleep.S
+++ b/arch/ppc/platforms/pmac_sleep.S
@@ -46,7 +46,7 @@
         .section .text
         .align  5
 
-#if defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ_PMAC)
+#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC)
 
 /* This gets called by via-pmu.c late during the sleep process.
  * The PMU was already send the sleep command and will shut us down
@@ -382,7 +382,7 @@ turn_on_mmu:
         isync
         rfi
 
-#endif /* defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ) */
+#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
 
         .section .data
         .balign L1_CACHE_LINE_SIZE
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
index de60ccc7db9f..778ce4fec368 100644
--- a/arch/ppc/platforms/pmac_time.c
+++ b/arch/ppc/platforms/pmac_time.c
@@ -206,7 +206,7 @@ via_calibrate_decr(void)
         return 1;
 }
 
-#ifdef CONFIG_PMAC_PBOOK
+#ifdef CONFIG_PM
 /*
  * Reset the time after a sleep.
  */
@@ -238,7 +238,7 @@ time_sleep_notify(struct pmu_sleep_notifier *self, int when)
 static struct pmu_sleep_notifier time_sleep_notifier __pmacdata = {
         time_sleep_notify, SLEEP_LEVEL_MISC,
 };
-#endif /* CONFIG_PMAC_PBOOK */
+#endif /* CONFIG_PM */
 
 /*
  * Query the OF and get the decr frequency.
@@ -251,9 +251,9 @@ pmac_calibrate_decr(void)
         struct device_node *cpu;
         unsigned int freq, *fp;
 
-#ifdef CONFIG_PMAC_PBOOK
+#ifdef CONFIG_PM
         pmu_register_sleep_notifier(&time_sleep_notifier);
-#endif /* CONFIG_PMAC_PBOOK */
+#endif /* CONFIG_PM */
 
         /* We assume MacRISC2 machines have correct device-tree
          * calibration. That's better since the VIA itself seems
diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c
index 70e58f43f2b8..8b149c2fc54f 100644
--- a/arch/ppc/platforms/sandpoint.c
+++ b/arch/ppc/platforms/sandpoint.c
@@ -324,6 +324,7 @@ sandpoint_setup_arch(void)
                         pdata[1].irq = 0;
                         pdata[1].mapbase = 0;
                 }
+        }
 
         printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index b45d8268bf93..ad39b86ca92c 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -370,8 +370,9 @@ void __init openpic_init(int offset)
         /* Initialize IPI interrupts */
         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
-                /* Disabled, Priority 10..13 */
-                openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
+                /* Disabled, increased priorities 10..13 */
+                openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
+                                OPENPIC_VEC_IPI+i+offset);
                 /* IPIs are per-CPU */
                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
@@ -399,8 +400,9 @@ void __init openpic_init(int offset)
                 if (sense & IRQ_SENSE_MASK)
                         irq_desc[i+offset].status = IRQ_LEVEL;
 
-                /* Enabled, Priority 8 */
-                openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
+                /* Enabled, Default priority */
+                openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
+                                (sense & IRQ_POLARITY_MASK),
                                 (sense & IRQ_SENSE_MASK));
                 /* Processor 0 */
                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
@@ -656,6 +658,18 @@ static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 }
 
 /*
+ * Change the priority of an interrupt
+ */
+void __init
+openpic_set_irq_priority(u_int irq, u_int pri)
+{
+        check_arg_irq(irq);
+        openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
+                                OPENPIC_PRIORITY_MASK,
+                                pri << OPENPIC_PRIORITY_SHIFT);
+}
+
+/*
  * Initalize the interrupt source which will generate an NMI.
  * This raises the interrupt's priority from 8 to 9.
  *
@@ -665,9 +679,7 @@ void __init
 openpic_init_nmi_irq(u_int irq)
 {
         check_arg_irq(irq);
-        openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
-                                OPENPIC_PRIORITY_MASK,
-                                9 << OPENPIC_PRIORITY_SHIFT);
+        openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
 }
 
 /*