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-rw-r--r--arch/ppc/Kconfig21
-rw-r--r--arch/ppc/boot/images/Makefile3
-rw-r--r--arch/ppc/configs/mpc8555_cds_defconfig117
-rw-r--r--arch/ppc/kernel/cputable.c11
-rw-r--r--arch/ppc/kernel/entry.S16
-rw-r--r--arch/ppc/kernel/head_fsl_booke.S15
-rw-r--r--arch/ppc/kernel/misc.S6
-rw-r--r--arch/ppc/kernel/pci.c2
-rw-r--r--arch/ppc/kernel/ppc_ksyms.c2
-rw-r--r--arch/ppc/kernel/ptrace.c40
-rw-r--r--arch/ppc/kernel/traps.c7
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.c1
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.h7
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c3
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c143
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.h3
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c3
-rw-r--r--arch/ppc/platforms/pmac_cpufreq.c43
-rw-r--r--arch/ppc/platforms/pq2ads.h41
-rw-r--r--arch/ppc/syslib/Makefile4
-rw-r--r--arch/ppc/syslib/m8260_pci.c193
-rw-r--r--arch/ppc/syslib/m8260_pci.h76
-rw-r--r--arch/ppc/syslib/m8260_pci_erratum9.c10
-rw-r--r--arch/ppc/syslib/m8260_setup.c11
-rw-r--r--arch/ppc/syslib/m82xx_pci.c383
-rw-r--r--arch/ppc/syslib/m82xx_pci.h92
-rw-r--r--arch/ppc/syslib/ocp.c2
-rw-r--r--arch/ppc/syslib/of_device.c2
-rw-r--r--arch/ppc/syslib/open_pic.c4
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c28
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c16
-rw-r--r--arch/ppc/syslib/prom_init.c10
32 files changed, 937 insertions, 378 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 600f23d7fd33..54ce6da22644 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -1083,6 +1083,23 @@ source "drivers/zorro/Kconfig"
1083 1083
1084source kernel/power/Kconfig 1084source kernel/power/Kconfig
1085 1085
1086config SECCOMP
1087 bool "Enable seccomp to safely compute untrusted bytecode"
1088 depends on PROC_FS
1089 default y
1090 help
1091 This kernel feature is useful for number crunching applications
1092 that may need to compute untrusted bytecode during their
1093 execution. By using pipes or other transports made available to
1094 the process as file descriptors supporting the read/write
1095 syscalls, it's possible to isolate those applications in
1096 their own address space using seccomp. Once seccomp is
1097 enabled via /proc/<pid>/seccomp, it cannot be disabled
1098 and the task is only allowed to execute a few safe syscalls
1099 defined by each seccomp mode.
1100
1101 If unsure, say Y. Only embedded should say N here.
1102
1086endmenu 1103endmenu
1087 1104
1088config ISA_DMA_API 1105config ISA_DMA_API
@@ -1143,12 +1160,12 @@ config PCI_QSPAN
1143 1160
1144config PCI_8260 1161config PCI_8260
1145 bool 1162 bool
1146 depends on PCI && 8260 && !8272 1163 depends on PCI && 8260
1147 default y 1164 default y
1148 1165
1149config 8260_PCI9 1166config 8260_PCI9
1150 bool " Enable workaround for MPC826x erratum PCI 9" 1167 bool " Enable workaround for MPC826x erratum PCI 9"
1151 depends on PCI_8260 1168 depends on PCI_8260 && !ADS8272
1152 default y 1169 default y
1153 1170
1154choice 1171choice
diff --git a/arch/ppc/boot/images/Makefile b/arch/ppc/boot/images/Makefile
index f850fb0fb511..c9ac5f5fa9e4 100644
--- a/arch/ppc/boot/images/Makefile
+++ b/arch/ppc/boot/images/Makefile
@@ -22,7 +22,8 @@ targets += uImage
22$(obj)/uImage: $(obj)/vmlinux.gz 22$(obj)/uImage: $(obj)/vmlinux.gz
23 $(Q)rm -f $@ 23 $(Q)rm -f $@
24 $(call if_changed,uimage) 24 $(call if_changed,uimage)
25 @echo ' Image: $@' $(if $(wildcard $@),'is ready','not made') 25 @echo -n ' Image: $@ '
26 @if [ -f $@ ]; then echo 'is ready' ; else echo 'not made'; fi
26 27
27# Files generated that shall be removed upon make clean 28# Files generated that shall be removed upon make clean
28clean-files := sImage vmapus vmlinux* miboot* zImage* uImage 29clean-files := sImage vmapus vmlinux* miboot* zImage* uImage
diff --git a/arch/ppc/configs/mpc8555_cds_defconfig b/arch/ppc/configs/mpc8555_cds_defconfig
index 728bd9e1a8fa..15abebf46b96 100644
--- a/arch/ppc/configs/mpc8555_cds_defconfig
+++ b/arch/ppc/configs/mpc8555_cds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc1 3# Linux kernel version: 2.6.12-rc4
4# Thu Jan 20 01:25:35 2005 4# Tue May 17 11:56:01 2005
5# 5#
6CONFIG_MMU=y 6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y 7CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y
11CONFIG_PPC=y 11CONFIG_PPC=y
12CONFIG_PPC32=y 12CONFIG_PPC32=y
13CONFIG_GENERIC_NVRAM=y 13CONFIG_GENERIC_NVRAM=y
14CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14 15
15# 16#
16# Code maturity level options 17# Code maturity level options
@@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
18CONFIG_EXPERIMENTAL=y 19CONFIG_EXPERIMENTAL=y
19CONFIG_CLEAN_COMPILE=y 20CONFIG_CLEAN_COMPILE=y
20CONFIG_BROKEN_ON_SMP=y 21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
21 23
22# 24#
23# General setup 25# General setup
@@ -29,12 +31,14 @@ CONFIG_SYSVIPC=y
29# CONFIG_BSD_PROCESS_ACCT is not set 31# CONFIG_BSD_PROCESS_ACCT is not set
30CONFIG_SYSCTL=y 32CONFIG_SYSCTL=y
31# CONFIG_AUDIT is not set 33# CONFIG_AUDIT is not set
32CONFIG_LOG_BUF_SHIFT=14
33# CONFIG_HOTPLUG is not set 34# CONFIG_HOTPLUG is not set
34CONFIG_KOBJECT_UEVENT=y 35CONFIG_KOBJECT_UEVENT=y
35# CONFIG_IKCONFIG is not set 36# CONFIG_IKCONFIG is not set
36CONFIG_EMBEDDED=y 37CONFIG_EMBEDDED=y
37# CONFIG_KALLSYMS is not set 38# CONFIG_KALLSYMS is not set
39CONFIG_PRINTK=y
40CONFIG_BUG=y
41CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y 42CONFIG_FUTEX=y
39# CONFIG_EPOLL is not set 43# CONFIG_EPOLL is not set
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 44# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -44,6 +48,7 @@ CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0 48CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0 49CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set 50# CONFIG_TINY_SHMEM is not set
51CONFIG_BASE_SMALL=0
47 52
48# 53#
49# Loadable module support 54# Loadable module support
@@ -62,10 +67,12 @@ CONFIG_CC_ALIGN_JUMPS=0
62CONFIG_E500=y 67CONFIG_E500=y
63CONFIG_BOOKE=y 68CONFIG_BOOKE=y
64CONFIG_FSL_BOOKE=y 69CONFIG_FSL_BOOKE=y
70# CONFIG_PHYS_64BIT is not set
65CONFIG_SPE=y 71CONFIG_SPE=y
66CONFIG_MATH_EMULATION=y 72CONFIG_MATH_EMULATION=y
67# CONFIG_CPU_FREQ is not set 73# CONFIG_CPU_FREQ is not set
68CONFIG_PPC_GEN550=y 74CONFIG_PPC_GEN550=y
75# CONFIG_PM is not set
69CONFIG_85xx=y 76CONFIG_85xx=y
70CONFIG_PPC_INDIRECT_PCI_BE=y 77CONFIG_PPC_INDIRECT_PCI_BE=y
71 78
@@ -76,6 +83,7 @@ CONFIG_PPC_INDIRECT_PCI_BE=y
76CONFIG_MPC8555_CDS=y 83CONFIG_MPC8555_CDS=y
77# CONFIG_MPC8560_ADS is not set 84# CONFIG_MPC8560_ADS is not set
78# CONFIG_SBC8560 is not set 85# CONFIG_SBC8560 is not set
86# CONFIG_STX_GP3 is not set
79CONFIG_MPC8555=y 87CONFIG_MPC8555=y
80CONFIG_85xx_PCI2=y 88CONFIG_85xx_PCI2=y
81 89
@@ -90,6 +98,7 @@ CONFIG_CPM2=y
90CONFIG_BINFMT_ELF=y 98CONFIG_BINFMT_ELF=y
91# CONFIG_BINFMT_MISC is not set 99# CONFIG_BINFMT_MISC is not set
92# CONFIG_CMDLINE_BOOL is not set 100# CONFIG_CMDLINE_BOOL is not set
101CONFIG_ISA_DMA_API=y
93 102
94# 103#
95# Bus options 104# Bus options
@@ -105,10 +114,6 @@ CONFIG_PCI_NAMES=y
105# CONFIG_PCCARD is not set 114# CONFIG_PCCARD is not set
106 115
107# 116#
108# PC-card bridges
109#
110
111#
112# Advanced setup 117# Advanced setup
113# 118#
114# CONFIG_ADVANCED_OPTIONS is not set 119# CONFIG_ADVANCED_OPTIONS is not set
@@ -180,7 +185,59 @@ CONFIG_IOSCHED_CFQ=y
180# 185#
181# ATA/ATAPI/MFM/RLL support 186# ATA/ATAPI/MFM/RLL support
182# 187#
183# CONFIG_IDE is not set 188CONFIG_IDE=y
189CONFIG_BLK_DEV_IDE=y
190
191#
192# Please see Documentation/ide.txt for help/info on IDE drives
193#
194# CONFIG_BLK_DEV_IDE_SATA is not set
195CONFIG_BLK_DEV_IDEDISK=y
196# CONFIG_IDEDISK_MULTI_MODE is not set
197# CONFIG_BLK_DEV_IDECD is not set
198# CONFIG_BLK_DEV_IDETAPE is not set
199# CONFIG_BLK_DEV_IDEFLOPPY is not set
200# CONFIG_IDE_TASK_IOCTL is not set
201
202#
203# IDE chipset support/bugfixes
204#
205CONFIG_IDE_GENERIC=y
206CONFIG_BLK_DEV_IDEPCI=y
207CONFIG_IDEPCI_SHARE_IRQ=y
208# CONFIG_BLK_DEV_OFFBOARD is not set
209CONFIG_BLK_DEV_GENERIC=y
210# CONFIG_BLK_DEV_OPTI621 is not set
211# CONFIG_BLK_DEV_SL82C105 is not set
212CONFIG_BLK_DEV_IDEDMA_PCI=y
213# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
214CONFIG_IDEDMA_PCI_AUTO=y
215# CONFIG_IDEDMA_ONLYDISK is not set
216# CONFIG_BLK_DEV_AEC62XX is not set
217# CONFIG_BLK_DEV_ALI15X3 is not set
218# CONFIG_BLK_DEV_AMD74XX is not set
219# CONFIG_BLK_DEV_CMD64X is not set
220# CONFIG_BLK_DEV_TRIFLEX is not set
221# CONFIG_BLK_DEV_CY82C693 is not set
222# CONFIG_BLK_DEV_CS5520 is not set
223# CONFIG_BLK_DEV_CS5530 is not set
224# CONFIG_BLK_DEV_HPT34X is not set
225# CONFIG_BLK_DEV_HPT366 is not set
226# CONFIG_BLK_DEV_SC1200 is not set
227# CONFIG_BLK_DEV_PIIX is not set
228# CONFIG_BLK_DEV_NS87415 is not set
229# CONFIG_BLK_DEV_PDC202XX_OLD is not set
230# CONFIG_BLK_DEV_PDC202XX_NEW is not set
231# CONFIG_BLK_DEV_SVWKS is not set
232# CONFIG_BLK_DEV_SIIMAGE is not set
233# CONFIG_BLK_DEV_SLC90E66 is not set
234# CONFIG_BLK_DEV_TRM290 is not set
235CONFIG_BLK_DEV_VIA82CXXX=y
236# CONFIG_IDE_ARM is not set
237CONFIG_BLK_DEV_IDEDMA=y
238# CONFIG_IDEDMA_IVB is not set
239CONFIG_IDEDMA_AUTO=y
240# CONFIG_BLK_DEV_HD is not set
184 241
185# 242#
186# SCSI device support 243# SCSI device support
@@ -220,7 +277,6 @@ CONFIG_NET=y
220# 277#
221CONFIG_PACKET=y 278CONFIG_PACKET=y
222# CONFIG_PACKET_MMAP is not set 279# CONFIG_PACKET_MMAP is not set
223# CONFIG_NETLINK_DEV is not set
224CONFIG_UNIX=y 280CONFIG_UNIX=y
225# CONFIG_NET_KEY is not set 281# CONFIG_NET_KEY is not set
226CONFIG_INET=y 282CONFIG_INET=y
@@ -370,14 +426,6 @@ CONFIG_INPUT=y
370# CONFIG_INPUT_EVBUG is not set 426# CONFIG_INPUT_EVBUG is not set
371 427
372# 428#
373# Input I/O drivers
374#
375# CONFIG_GAMEPORT is not set
376CONFIG_SOUND_GAMEPORT=y
377# CONFIG_SERIO is not set
378# CONFIG_SERIO_I8042 is not set
379
380#
381# Input Device Drivers 429# Input Device Drivers
382# 430#
383# CONFIG_INPUT_KEYBOARD is not set 431# CONFIG_INPUT_KEYBOARD is not set
@@ -387,6 +435,13 @@ CONFIG_SOUND_GAMEPORT=y
387# CONFIG_INPUT_MISC is not set 435# CONFIG_INPUT_MISC is not set
388 436
389# 437#
438# Hardware I/O ports
439#
440# CONFIG_SERIO is not set
441# CONFIG_GAMEPORT is not set
442CONFIG_SOUND_GAMEPORT=y
443
444#
390# Character devices 445# Character devices
391# 446#
392# CONFIG_VT is not set 447# CONFIG_VT is not set
@@ -406,6 +461,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
406CONFIG_SERIAL_CORE=y 461CONFIG_SERIAL_CORE=y
407CONFIG_SERIAL_CORE_CONSOLE=y 462CONFIG_SERIAL_CORE_CONSOLE=y
408# CONFIG_SERIAL_CPM is not set 463# CONFIG_SERIAL_CPM is not set
464# CONFIG_SERIAL_JSM is not set
409CONFIG_UNIX98_PTYS=y 465CONFIG_UNIX98_PTYS=y
410CONFIG_LEGACY_PTYS=y 466CONFIG_LEGACY_PTYS=y
411CONFIG_LEGACY_PTY_COUNT=256 467CONFIG_LEGACY_PTY_COUNT=256
@@ -434,6 +490,11 @@ CONFIG_GEN_RTC=y
434# CONFIG_RAW_DRIVER is not set 490# CONFIG_RAW_DRIVER is not set
435 491
436# 492#
493# TPM devices
494#
495# CONFIG_TCG_TPM is not set
496
497#
437# I2C support 498# I2C support
438# 499#
439CONFIG_I2C=y 500CONFIG_I2C=y
@@ -456,11 +517,11 @@ CONFIG_I2C_CHARDEV=y
456# CONFIG_I2C_AMD8111 is not set 517# CONFIG_I2C_AMD8111 is not set
457# CONFIG_I2C_I801 is not set 518# CONFIG_I2C_I801 is not set
458# CONFIG_I2C_I810 is not set 519# CONFIG_I2C_I810 is not set
520# CONFIG_I2C_PIIX4 is not set
459# CONFIG_I2C_ISA is not set 521# CONFIG_I2C_ISA is not set
460CONFIG_I2C_MPC=y 522CONFIG_I2C_MPC=y
461# CONFIG_I2C_NFORCE2 is not set 523# CONFIG_I2C_NFORCE2 is not set
462# CONFIG_I2C_PARPORT_LIGHT is not set 524# CONFIG_I2C_PARPORT_LIGHT is not set
463# CONFIG_I2C_PIIX4 is not set
464# CONFIG_I2C_PROSAVAGE is not set 525# CONFIG_I2C_PROSAVAGE is not set
465# CONFIG_I2C_SAVAGE4 is not set 526# CONFIG_I2C_SAVAGE4 is not set
466# CONFIG_SCx200_ACB is not set 527# CONFIG_SCx200_ACB is not set
@@ -483,7 +544,9 @@ CONFIG_I2C_MPC=y
483# CONFIG_SENSORS_ASB100 is not set 544# CONFIG_SENSORS_ASB100 is not set
484# CONFIG_SENSORS_DS1621 is not set 545# CONFIG_SENSORS_DS1621 is not set
485# CONFIG_SENSORS_FSCHER is not set 546# CONFIG_SENSORS_FSCHER is not set
547# CONFIG_SENSORS_FSCPOS is not set
486# CONFIG_SENSORS_GL518SM is not set 548# CONFIG_SENSORS_GL518SM is not set
549# CONFIG_SENSORS_GL520SM is not set
487# CONFIG_SENSORS_IT87 is not set 550# CONFIG_SENSORS_IT87 is not set
488# CONFIG_SENSORS_LM63 is not set 551# CONFIG_SENSORS_LM63 is not set
489# CONFIG_SENSORS_LM75 is not set 552# CONFIG_SENSORS_LM75 is not set
@@ -494,9 +557,11 @@ CONFIG_I2C_MPC=y
494# CONFIG_SENSORS_LM85 is not set 557# CONFIG_SENSORS_LM85 is not set
495# CONFIG_SENSORS_LM87 is not set 558# CONFIG_SENSORS_LM87 is not set
496# CONFIG_SENSORS_LM90 is not set 559# CONFIG_SENSORS_LM90 is not set
560# CONFIG_SENSORS_LM92 is not set
497# CONFIG_SENSORS_MAX1619 is not set 561# CONFIG_SENSORS_MAX1619 is not set
498# CONFIG_SENSORS_PC87360 is not set 562# CONFIG_SENSORS_PC87360 is not set
499# CONFIG_SENSORS_SMSC47B397 is not set 563# CONFIG_SENSORS_SMSC47B397 is not set
564# CONFIG_SENSORS_SIS5595 is not set
500# CONFIG_SENSORS_SMSC47M1 is not set 565# CONFIG_SENSORS_SMSC47M1 is not set
501# CONFIG_SENSORS_VIA686A is not set 566# CONFIG_SENSORS_VIA686A is not set
502# CONFIG_SENSORS_W83781D is not set 567# CONFIG_SENSORS_W83781D is not set
@@ -506,10 +571,12 @@ CONFIG_I2C_MPC=y
506# 571#
507# Other I2C Chip support 572# Other I2C Chip support
508# 573#
574# CONFIG_SENSORS_DS1337 is not set
509# CONFIG_SENSORS_EEPROM is not set 575# CONFIG_SENSORS_EEPROM is not set
510# CONFIG_SENSORS_PCF8574 is not set 576# CONFIG_SENSORS_PCF8574 is not set
511# CONFIG_SENSORS_PCF8591 is not set 577# CONFIG_SENSORS_PCF8591 is not set
512# CONFIG_SENSORS_RTC8564 is not set 578# CONFIG_SENSORS_RTC8564 is not set
579# CONFIG_SENSORS_M41T00 is not set
513# CONFIG_I2C_DEBUG_CORE is not set 580# CONFIG_I2C_DEBUG_CORE is not set
514# CONFIG_I2C_DEBUG_ALGO is not set 581# CONFIG_I2C_DEBUG_ALGO is not set
515# CONFIG_I2C_DEBUG_BUS is not set 582# CONFIG_I2C_DEBUG_BUS is not set
@@ -538,7 +605,6 @@ CONFIG_I2C_MPC=y
538# Graphics support 605# Graphics support
539# 606#
540# CONFIG_FB is not set 607# CONFIG_FB is not set
541# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
542 608
543# 609#
544# Sound 610# Sound
@@ -548,13 +614,9 @@ CONFIG_I2C_MPC=y
548# 614#
549# USB support 615# USB support
550# 616#
551# CONFIG_USB is not set
552CONFIG_USB_ARCH_HAS_HCD=y 617CONFIG_USB_ARCH_HAS_HCD=y
553CONFIG_USB_ARCH_HAS_OHCI=y 618CONFIG_USB_ARCH_HAS_OHCI=y
554 619# CONFIG_USB is not set
555#
556# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
557#
558 620
559# 621#
560# USB Gadget Support 622# USB Gadget Support
@@ -585,6 +647,10 @@ CONFIG_JBD=y
585CONFIG_FS_MBCACHE=y 647CONFIG_FS_MBCACHE=y
586# CONFIG_REISERFS_FS is not set 648# CONFIG_REISERFS_FS is not set
587# CONFIG_JFS_FS is not set 649# CONFIG_JFS_FS is not set
650
651#
652# XFS support
653#
588# CONFIG_XFS_FS is not set 654# CONFIG_XFS_FS is not set
589# CONFIG_MINIX_FS is not set 655# CONFIG_MINIX_FS is not set
590# CONFIG_ROMFS_FS is not set 656# CONFIG_ROMFS_FS is not set
@@ -646,7 +712,6 @@ CONFIG_NFS_FS=y
646# CONFIG_NFSD is not set 712# CONFIG_NFSD is not set
647CONFIG_ROOT_NFS=y 713CONFIG_ROOT_NFS=y
648CONFIG_LOCKD=y 714CONFIG_LOCKD=y
649# CONFIG_EXPORTFS is not set
650CONFIG_SUNRPC=y 715CONFIG_SUNRPC=y
651# CONFIG_RPCSEC_GSS_KRB5 is not set 716# CONFIG_RPCSEC_GSS_KRB5 is not set
652# CONFIG_RPCSEC_GSS_SPKM3 is not set 717# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -698,7 +763,9 @@ CONFIG_CRC32=y
698# 763#
699# Kernel hacking 764# Kernel hacking
700# 765#
766# CONFIG_PRINTK_TIME is not set
701# CONFIG_DEBUG_KERNEL is not set 767# CONFIG_DEBUG_KERNEL is not set
768CONFIG_LOG_BUF_SHIFT=14
702# CONFIG_KGDB_CONSOLE is not set 769# CONFIG_KGDB_CONSOLE is not set
703# CONFIG_SERIAL_TEXT_DEBUG is not set 770# CONFIG_SERIAL_TEXT_DEBUG is not set
704 771
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 8aa5e8c69009..d44b7dc5390a 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -838,6 +838,17 @@ struct cpu_spec cpu_specs[] = {
838 .icache_bsize = 32, 838 .icache_bsize = 32,
839 .dcache_bsize = 32, 839 .dcache_bsize = 32,
840 }, 840 },
841 { /* 405EP */
842 .pvr_mask = 0xffff0000,
843 .pvr_value = 0x51210000,
844 .cpu_name = "405EP",
845 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
846 CPU_FTR_USE_TB,
847 .cpu_user_features = PPC_FEATURE_32 |
848 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
849 .icache_bsize = 32,
850 .dcache_bsize = 32,
851 },
841 852
842#endif /* CONFIG_40x */ 853#endif /* CONFIG_40x */
843#ifdef CONFIG_44x 854#ifdef CONFIG_44x
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index 5f075dbc4ee7..661523707e8c 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -202,7 +202,7 @@ _GLOBAL(DoSyscall)
202 rlwinm r11,r11,0,~_TIFL_FORCE_NOERROR 202 rlwinm r11,r11,0,~_TIFL_FORCE_NOERROR
203 stw r11,TI_LOCAL_FLAGS(r10) 203 stw r11,TI_LOCAL_FLAGS(r10)
204 lwz r11,TI_FLAGS(r10) 204 lwz r11,TI_FLAGS(r10)
205 andi. r11,r11,_TIF_SYSCALL_TRACE 205 andi. r11,r11,_TIF_SYSCALL_T_OR_A
206 bne- syscall_dotrace 206 bne- syscall_dotrace
207syscall_dotrace_cont: 207syscall_dotrace_cont:
208 cmplwi 0,r0,NR_syscalls 208 cmplwi 0,r0,NR_syscalls
@@ -237,7 +237,7 @@ ret_from_syscall:
237 SYNC 237 SYNC
238 MTMSRD(r10) 238 MTMSRD(r10)
239 lwz r9,TI_FLAGS(r12) 239 lwz r9,TI_FLAGS(r12)
240 andi. r0,r9,(_TIF_SYSCALL_TRACE|_TIF_SIGPENDING|_TIF_NEED_RESCHED) 240 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SIGPENDING|_TIF_NEED_RESCHED)
241 bne- syscall_exit_work 241 bne- syscall_exit_work
242syscall_exit_cont: 242syscall_exit_cont:
243#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 243#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
@@ -277,7 +277,8 @@ syscall_dotrace:
277 SAVE_NVGPRS(r1) 277 SAVE_NVGPRS(r1)
278 li r0,0xc00 278 li r0,0xc00
279 stw r0,TRAP(r1) 279 stw r0,TRAP(r1)
280 bl do_syscall_trace 280 addi r3,r1,STACK_FRAME_OVERHEAD
281 bl do_syscall_trace_enter
281 lwz r0,GPR0(r1) /* Restore original registers */ 282 lwz r0,GPR0(r1) /* Restore original registers */
282 lwz r3,GPR3(r1) 283 lwz r3,GPR3(r1)
283 lwz r4,GPR4(r1) 284 lwz r4,GPR4(r1)
@@ -291,7 +292,7 @@ syscall_dotrace:
291syscall_exit_work: 292syscall_exit_work:
292 stw r6,RESULT(r1) /* Save result */ 293 stw r6,RESULT(r1) /* Save result */
293 stw r3,GPR3(r1) /* Update return value */ 294 stw r3,GPR3(r1) /* Update return value */
294 andi. r0,r9,_TIF_SYSCALL_TRACE 295 andi. r0,r9,_TIF_SYSCALL_T_OR_A
295 beq 5f 296 beq 5f
296 ori r10,r10,MSR_EE 297 ori r10,r10,MSR_EE
297 SYNC 298 SYNC
@@ -303,7 +304,8 @@ syscall_exit_work:
303 li r4,0xc00 304 li r4,0xc00
304 stw r4,TRAP(r1) 305 stw r4,TRAP(r1)
3054: 3064:
306 bl do_syscall_trace 307 addi r3,r1,STACK_FRAME_OVERHEAD
308 bl do_syscall_trace_leave
307 REST_NVGPRS(r1) 309 REST_NVGPRS(r1)
3082: 3102:
309 lwz r3,GPR3(r1) 311 lwz r3,GPR3(r1)
@@ -627,8 +629,8 @@ sigreturn_exit:
627 subi r1,r3,STACK_FRAME_OVERHEAD 629 subi r1,r3,STACK_FRAME_OVERHEAD
628 rlwinm r12,r1,0,0,18 /* current_thread_info() */ 630 rlwinm r12,r1,0,0,18 /* current_thread_info() */
629 lwz r9,TI_FLAGS(r12) 631 lwz r9,TI_FLAGS(r12)
630 andi. r0,r9,_TIF_SYSCALL_TRACE 632 andi. r0,r9,_TIF_SYSCALL_T_OR_A
631 bnel- do_syscall_trace 633 bnel- do_syscall_trace_leave
632 /* fall through */ 634 /* fall through */
633 635
634 .globl ret_from_except_full 636 .globl ret_from_except_full
diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
index f22ddce36135..ce36e88ba627 100644
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -232,7 +232,8 @@ skpinv: addi r6,r6,1 /* Increment */
232 tlbwe 232 tlbwe
233 233
234/* 7. Jump to KERNELBASE mapping */ 234/* 7. Jump to KERNELBASE mapping */
235 li r7,0 235 lis r7,MSR_KERNEL@h
236 ori r7,r7,MSR_KERNEL@l
236 bl 1f /* Find our address */ 237 bl 1f /* Find our address */
2371: mflr r9 2381: mflr r9
238 rlwimi r6,r9,0,20,31 239 rlwimi r6,r9,0,20,31
@@ -293,6 +294,18 @@ skpinv: addi r6,r6,1 /* Increment */
293 mtspr SPRN_HID0, r2 294 mtspr SPRN_HID0, r2
294#endif 295#endif
295 296
297#if !defined(CONFIG_BDI_SWITCH)
298 /*
299 * The Abatron BDI JTAG debugger does not tolerate others
300 * mucking with the debug registers.
301 */
302 lis r2,DBCR0_IDM@h
303 mtspr SPRN_DBCR0,r2
304 /* clear any residual debug events */
305 li r2,-1
306 mtspr SPRN_DBSR,r2
307#endif
308
296 /* 309 /*
297 * This is where the main kernel code starts. 310 * This is where the main kernel code starts.
298 */ 311 */
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index e4f1615ec13f..7329ef177a18 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -619,7 +619,7 @@ _GLOBAL(flush_instruction_cache)
619_GLOBAL(flush_icache_range) 619_GLOBAL(flush_icache_range)
620BEGIN_FTR_SECTION 620BEGIN_FTR_SECTION
621 blr /* for 601, do nothing */ 621 blr /* for 601, do nothing */
622END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 622END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
623 li r5,L1_CACHE_LINE_SIZE-1 623 li r5,L1_CACHE_LINE_SIZE-1
624 andc r3,r3,r5 624 andc r3,r3,r5
625 subf r4,r3,r4 625 subf r4,r3,r4
@@ -736,7 +736,7 @@ _GLOBAL(flush_dcache_all)
736_GLOBAL(__flush_dcache_icache) 736_GLOBAL(__flush_dcache_icache)
737BEGIN_FTR_SECTION 737BEGIN_FTR_SECTION
738 blr /* for 601, do nothing */ 738 blr /* for 601, do nothing */
739END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 739END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
740 rlwinm r3,r3,0,0,19 /* Get page base address */ 740 rlwinm r3,r3,0,0,19 /* Get page base address */
741 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ 741 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
742 mtctr r4 742 mtctr r4
@@ -764,7 +764,7 @@ END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
764_GLOBAL(__flush_dcache_icache_phys) 764_GLOBAL(__flush_dcache_icache_phys)
765BEGIN_FTR_SECTION 765BEGIN_FTR_SECTION
766 blr /* for 601, do nothing */ 766 blr /* for 601, do nothing */
767END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 767END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
768 mfmsr r10 768 mfmsr r10
769 rlwinm r0,r10,0,28,26 /* clear DR */ 769 rlwinm r0,r10,0,28,26 /* clear DR */
770 mtmsr r0 770 mtmsr r0
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
index 47a15306823a..6d7b92d72458 100644
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -1003,7 +1003,7 @@ pci_create_OF_bus_map(void)
1003 } 1003 }
1004} 1004}
1005 1005
1006static ssize_t pci_show_devspec(struct device *dev, char *buf) 1006static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1007{ 1007{
1008 struct pci_dev *pdev; 1008 struct pci_dev *pdev;
1009 struct device_node *np; 1009 struct device_node *np;
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index 2ccb58fe4fc3..d59ad07de8e7 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -55,7 +55,6 @@
55#define EXPORT_SYMTAB_STROPS 55#define EXPORT_SYMTAB_STROPS
56 56
57extern void transfer_to_handler(void); 57extern void transfer_to_handler(void);
58extern void do_syscall_trace(void);
59extern void do_IRQ(struct pt_regs *regs); 58extern void do_IRQ(struct pt_regs *regs);
60extern void MachineCheckException(struct pt_regs *regs); 59extern void MachineCheckException(struct pt_regs *regs);
61extern void AlignmentException(struct pt_regs *regs); 60extern void AlignmentException(struct pt_regs *regs);
@@ -74,7 +73,6 @@ extern unsigned long mm_ptov (unsigned long paddr);
74EXPORT_SYMBOL(clear_pages); 73EXPORT_SYMBOL(clear_pages);
75EXPORT_SYMBOL(clear_user_page); 74EXPORT_SYMBOL(clear_user_page);
76EXPORT_SYMBOL(do_signal); 75EXPORT_SYMBOL(do_signal);
77EXPORT_SYMBOL(do_syscall_trace);
78EXPORT_SYMBOL(transfer_to_handler); 76EXPORT_SYMBOL(transfer_to_handler);
79EXPORT_SYMBOL(do_IRQ); 77EXPORT_SYMBOL(do_IRQ);
80EXPORT_SYMBOL(MachineCheckException); 78EXPORT_SYMBOL(MachineCheckException);
diff --git a/arch/ppc/kernel/ptrace.c b/arch/ppc/kernel/ptrace.c
index 59d59a8dc249..e7aee4108dea 100644
--- a/arch/ppc/kernel/ptrace.c
+++ b/arch/ppc/kernel/ptrace.c
@@ -27,6 +27,9 @@
27#include <linux/user.h> 27#include <linux/user.h>
28#include <linux/security.h> 28#include <linux/security.h>
29#include <linux/signal.h> 29#include <linux/signal.h>
30#include <linux/seccomp.h>
31#include <linux/audit.h>
32#include <linux/module.h>
30 33
31#include <asm/uaccess.h> 34#include <asm/uaccess.h>
32#include <asm/page.h> 35#include <asm/page.h>
@@ -455,11 +458,10 @@ out:
455 return ret; 458 return ret;
456} 459}
457 460
458void do_syscall_trace(void) 461static void do_syscall_trace(void)
459{ 462{
460 if (!test_thread_flag(TIF_SYSCALL_TRACE) 463 /* the 0x80 provides a way for the tracing parent to distinguish
461 || !(current->ptrace & PT_PTRACED)) 464 between a syscall stop and SIGTRAP delivery */
462 return;
463 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) 465 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
464 ? 0x80 : 0)); 466 ? 0x80 : 0));
465 467
@@ -473,3 +475,33 @@ void do_syscall_trace(void)
473 current->exit_code = 0; 475 current->exit_code = 0;
474 } 476 }
475} 477}
478
479void do_syscall_trace_enter(struct pt_regs *regs)
480{
481 if (test_thread_flag(TIF_SYSCALL_TRACE)
482 && (current->ptrace & PT_PTRACED))
483 do_syscall_trace();
484
485 if (unlikely(current->audit_context))
486 audit_syscall_entry(current, AUDIT_ARCH_PPC,
487 regs->gpr[0],
488 regs->gpr[3], regs->gpr[4],
489 regs->gpr[5], regs->gpr[6]);
490}
491
492void do_syscall_trace_leave(struct pt_regs *regs)
493{
494 secure_computing(regs->gpr[0]);
495
496 if (unlikely(current->audit_context))
497 audit_syscall_exit(current,
498 (regs->ccr&0x1000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
499 regs->result);
500
501 if ((test_thread_flag(TIF_SYSCALL_TRACE))
502 && (current->ptrace & PT_PTRACED))
503 do_syscall_trace();
504}
505
506EXPORT_SYMBOL(do_syscall_trace_enter);
507EXPORT_SYMBOL(do_syscall_trace_leave);
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
index f8e7e324a173..c65731e8bc65 100644
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -408,12 +408,7 @@ static int emulate_string_inst(struct pt_regs *regs, u32 instword)
408 408
409 /* Early out if we are an invalid form of lswx */ 409 /* Early out if we are an invalid form of lswx */
410 if ((instword & INST_STRING_MASK) == INST_LSWX) 410 if ((instword & INST_STRING_MASK) == INST_LSWX)
411 if ((rA >= rT) || (NB_RB >= rT) || (rT == rA) || (rT == NB_RB)) 411 if ((rT == rA) || (rT == NB_RB))
412 return -EINVAL;
413
414 /* Early out if we are an invalid form of lswi */
415 if ((instword & INST_STRING_MASK) == INST_LSWI)
416 if ((rA >= rT) || (rT == rA))
417 return -EINVAL; 412 return -EINVAL;
418 413
419 EA = (rA == 0) ? 0 : regs->gpr[rA]; 414 EA = (rA == 0) ? 0 : regs->gpr[rA];
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index b3b0f51979d2..e6348b5a1ddc 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -127,7 +127,6 @@ mpc834x_sys_map_io(void)
127{ 127{
128 /* we steal the lowest ioremap addr for virt space */ 128 /* we steal the lowest ioremap addr for virt space */
129 io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO); 129 io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
130 io_block_mapping(BCSR_VIRT_ADDR, BCSR_PHYS_ADDR, BCSR_SIZE, _PAGE_IO);
131} 130}
132 131
133int 132int
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index f4d055ae19c1..a2f6e49d7151 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -26,9 +26,14 @@
26#define VIRT_IMMRBAR ((uint)0xfe000000) 26#define VIRT_IMMRBAR ((uint)0xfe000000)
27 27
28#define BCSR_PHYS_ADDR ((uint)0xf8000000) 28#define BCSR_PHYS_ADDR ((uint)0xf8000000)
29#define BCSR_VIRT_ADDR ((uint)0xfe100000)
30#define BCSR_SIZE ((uint)(32 * 1024)) 29#define BCSR_SIZE ((uint)(32 * 1024))
31 30
31#define BCSR_MISC_REG2_OFF 0x07
32#define BCSR_MISC_REG2_PORESET 0x01
33
34#define BCSR_MISC_REG3_OFF 0x08
35#define BCSR_MISC_REG3_CNFLOCK 0x80
36
32#ifdef CONFIG_PCI 37#ifdef CONFIG_PCI
33/* PCI interrupt controller */ 38/* PCI interrupt controller */
34#define PIRQA MPC83xx_IRQ_IRQ4 39#define PIRQA MPC83xx_IRQ_IRQ4
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index 4d857d6d633d..583838ab02d8 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -210,6 +210,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
210#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) 210#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
211 ppc_md.progress = gen550_progress; 211 ppc_md.progress = gen550_progress;
212#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ 212#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
213#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
214 ppc_md.early_serial_map = mpc85xx_early_serial_map;
215#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
213 216
214 if (ppc_md.progress) 217 if (ppc_md.progress)
215 ppc_md.progress("mpc8540ads_init(): exit", 0); 218 ppc_md.progress("mpc8540ads_init(): exit", 0);
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index 6c020d67ad70..e7cfa498568c 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -44,6 +44,7 @@
44#include <asm/machdep.h> 44#include <asm/machdep.h>
45#include <asm/prom.h> 45#include <asm/prom.h>
46#include <asm/open_pic.h> 46#include <asm/open_pic.h>
47#include <asm/i8259.h>
47#include <asm/bootinfo.h> 48#include <asm/bootinfo.h>
48#include <asm/pci-bridge.h> 49#include <asm/pci-bridge.h>
49#include <asm/mpc85xx.h> 50#include <asm/mpc85xx.h>
@@ -181,6 +182,7 @@ void __init
181mpc85xx_cds_init_IRQ(void) 182mpc85xx_cds_init_IRQ(void)
182{ 183{
183 bd_t *binfo = (bd_t *) __res; 184 bd_t *binfo = (bd_t *) __res;
185 int i;
184 186
185 /* Determine the Physical Address of the OpenPIC regs */ 187 /* Determine the Physical Address of the OpenPIC regs */
186 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; 188 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -198,6 +200,15 @@ mpc85xx_cds_init_IRQ(void)
198 */ 200 */
199 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); 201 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
200 202
203#ifdef CONFIG_PCI
204 openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
205
206 for (i = 0; i < NUM_8259_INTERRUPTS; i++)
207 irq_desc[i].handler = &i8259_pic;
208
209 i8259_init(0);
210#endif
211
201#ifdef CONFIG_CPM2 212#ifdef CONFIG_CPM2
202 /* Setup CPM2 PIC */ 213 /* Setup CPM2 PIC */
203 cpm2_init_IRQ(); 214 cpm2_init_IRQ();
@@ -231,7 +242,7 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
231 * interrupt on slot */ 242 * interrupt on slot */
232 { 243 {
233 { 0, 1, 2, 3 }, /* 16 - PMC */ 244 { 0, 1, 2, 3 }, /* 16 - PMC */
234 { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */ 245 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
235 { 0, 1, 2, 3 }, /* 18 - Slot 1 */ 246 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
236 { 1, 2, 3, 0 }, /* 19 - Slot 2 */ 247 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
237 { 2, 3, 0, 1 }, /* 20 - Slot 3 */ 248 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
@@ -280,13 +291,135 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
280 return PCIBIOS_DEVICE_NOT_FOUND; 291 return PCIBIOS_DEVICE_NOT_FOUND;
281#endif 292#endif
282 /* We explicitly do not go past the Tundra 320 Bridge */ 293 /* We explicitly do not go past the Tundra 320 Bridge */
283 if (bus == 1) 294 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
284 return PCIBIOS_DEVICE_NOT_FOUND; 295 return PCIBIOS_DEVICE_NOT_FOUND;
285 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) 296 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
286 return PCIBIOS_DEVICE_NOT_FOUND; 297 return PCIBIOS_DEVICE_NOT_FOUND;
287 else 298 else
288 return PCIBIOS_SUCCESSFUL; 299 return PCIBIOS_SUCCESSFUL;
289} 300}
301
302void __init
303mpc85xx_cds_enable_via(struct pci_controller *hose)
304{
305 u32 pci_class;
306 u16 vid, did;
307
308 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
309 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
310 return;
311
312 /* Configure P2P so that we can reach bus 1 */
313 early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
314 early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
315 early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
316
317 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
318 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
319
320 if ((vid != PCI_VENDOR_ID_VIA) ||
321 (did != PCI_DEVICE_ID_VIA_82C686))
322 return;
323
324 /* Enable USB and IDE functions */
325 early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
326}
327
328void __init
329mpc85xx_cds_fixup_via(struct pci_controller *hose)
330{
331 u32 pci_class;
332 u16 vid, did;
333
334 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
335 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
336 return;
337
338 /*
339 * Force the backplane P2P bridge to have a window
340 * open from 0x00000000-0x00001fff in PCI I/O space.
341 * This allows legacy I/O (i8259, etc) on the VIA
342 * southbridge to be accessed.
343 */
344 early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
345 early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
346 early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
347 early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
348
349 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
350 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
351 if ((vid != PCI_VENDOR_ID_VIA) ||
352 (did != PCI_DEVICE_ID_VIA_82C686))
353 return;
354
355 /*
356 * Since the P2P window was forced to cover the fixed
357 * legacy I/O addresses, it is necessary to manually
358 * place the base addresses for the IDE and USB functions
359 * within this window.
360 */
361 /* Function 1, IDE */
362 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
363 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
364 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
365 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
366 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
367
368 /* Function 2, USB ports 0-1 */
369 early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
370
371 /* Function 3, USB ports 2-3 */
372 early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
373
374 /* Function 5, Power Management */
375 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
376 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
377 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
378
379 /* Function 6, AC97 Interface */
380 early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
381}
382
383void __init
384mpc85xx_cds_pcibios_fixup(void)
385{
386 struct pci_dev *dev = NULL;
387 u_char c;
388
389 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
390 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
391 /*
392 * U-Boot does not set the enable bits
393 * for the IDE device. Force them on here.
394 */
395 pci_read_config_byte(dev, 0x40, &c);
396 c |= 0x03; /* IDE: Chip Enable Bits */
397 pci_write_config_byte(dev, 0x40, c);
398
399 /*
400 * Since only primary interface works, force the
401 * IDE function to standard primary IDE interrupt
402 * w/ 8259 offset
403 */
404 dev->irq = 14;
405 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
406 }
407
408 /*
409 * Force legacy USB interrupt routing
410 */
411 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
412 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
413 dev->irq = 10;
414 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
415 }
416
417 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
418 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
419 dev->irq = 11;
420 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
421 }
422}
290#endif /* CONFIG_PCI */ 423#endif /* CONFIG_PCI */
291 424
292TODC_ALLOC(); 425TODC_ALLOC();
@@ -328,6 +461,9 @@ mpc85xx_cds_setup_arch(void)
328 loops_per_jiffy = freq / HZ; 461 loops_per_jiffy = freq / HZ;
329 462
330#ifdef CONFIG_PCI 463#ifdef CONFIG_PCI
464 /* VIA IDE configuration */
465 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
466
331 /* setup PCI host bridges */ 467 /* setup PCI host bridges */
332 mpc85xx_setup_hose(); 468 mpc85xx_setup_hose();
333#endif 469#endif
@@ -459,6 +595,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
459#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) 595#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
460 ppc_md.progress = gen550_progress; 596 ppc_md.progress = gen550_progress;
461#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ 597#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
598#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
599 ppc_md.early_serial_map = mpc85xx_early_serial_map;
600#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
462 601
463 if (ppc_md.progress) 602 if (ppc_md.progress)
464 ppc_md.progress("mpc85xx_cds_init(): exit", 0); 603 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
index 7627d77504bd..12b292c6ae32 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -77,4 +77,7 @@
77 77
78#define MPC85XX_PCI2_IO_SIZE 0x01000000 78#define MPC85XX_PCI2_IO_SIZE 0x01000000
79 79
80#define NR_8259_INTS 16
81#define CPM_IRQ_OFFSET NR_8259_INTS
82
80#endif /* __MACH_MPC85XX_CDS_H__ */ 83#endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index 9ab05e590c3e..7b9e1543e175 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -221,6 +221,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
221#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) 221#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
222 ppc_md.progress = gen550_progress; 222 ppc_md.progress = gen550_progress;
223#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ 223#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
224#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
225 ppc_md.early_serial_map = sbc8560_early_serial_map;
226#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
224 227
225 if (ppc_md.progress) 228 if (ppc_md.progress)
226 ppc_md.progress("sbc8560_init(): exit", 0); 229 ppc_md.progress("sbc8560_init(): exit", 0);
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
index f7fb2786cd50..5fdd4f607a40 100644
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ b/arch/ppc/platforms/pmac_cpufreq.c
@@ -83,16 +83,13 @@ static u32 frequency_gpio;
83static u32 slew_done_gpio; 83static u32 slew_done_gpio;
84static int no_schedule; 84static int no_schedule;
85static int has_cpu_l2lve; 85static int has_cpu_l2lve;
86 86static int is_pmu_based;
87
88#define PMAC_CPU_LOW_SPEED 1
89#define PMAC_CPU_HIGH_SPEED 0
90 87
91/* There are only two frequency states for each processor. Values 88/* There are only two frequency states for each processor. Values
92 * are in kHz for the time being. 89 * are in kHz for the time being.
93 */ 90 */
94#define CPUFREQ_HIGH PMAC_CPU_HIGH_SPEED 91#define CPUFREQ_HIGH 0
95#define CPUFREQ_LOW PMAC_CPU_LOW_SPEED 92#define CPUFREQ_LOW 1
96 93
97static struct cpufreq_frequency_table pmac_cpu_freqs[] = { 94static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
98 {CPUFREQ_HIGH, 0}, 95 {CPUFREQ_HIGH, 0},
@@ -100,6 +97,11 @@ static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
100 {0, CPUFREQ_TABLE_END}, 97 {0, CPUFREQ_TABLE_END},
101}; 98};
102 99
100static struct freq_attr* pmac_cpu_freqs_attr[] = {
101 &cpufreq_freq_attr_scaling_available_freqs,
102 NULL,
103};
104
103static inline void local_delay(unsigned long ms) 105static inline void local_delay(unsigned long ms)
104{ 106{
105 if (no_schedule) 107 if (no_schedule)
@@ -269,6 +271,8 @@ static int __pmac pmu_set_cpu_speed(int low_speed)
269#ifdef DEBUG_FREQ 271#ifdef DEBUG_FREQ
270 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1)); 272 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
271#endif 273#endif
274 pmu_suspend();
275
272 /* Disable all interrupt sources on openpic */ 276 /* Disable all interrupt sources on openpic */
273 pic_prio = openpic_get_priority(); 277 pic_prio = openpic_get_priority();
274 openpic_set_priority(0xf); 278 openpic_set_priority(0xf);
@@ -343,6 +347,8 @@ static int __pmac pmu_set_cpu_speed(int low_speed)
343 debug_calc_bogomips(); 347 debug_calc_bogomips();
344#endif 348#endif
345 349
350 pmu_resume();
351
346 preempt_enable(); 352 preempt_enable();
347 353
348 return 0; 354 return 0;
@@ -355,7 +361,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
355 static unsigned long prev_l3cr; 361 static unsigned long prev_l3cr;
356 362
357 freqs.old = cur_freq; 363 freqs.old = cur_freq;
358 freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq; 364 freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
359 freqs.cpu = smp_processor_id(); 365 freqs.cpu = smp_processor_id();
360 366
361 if (freqs.old == freqs.new) 367 if (freqs.old == freqs.new)
@@ -363,7 +369,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
363 369
364 if (notify) 370 if (notify)
365 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 371 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
366 if (speed_mode == PMAC_CPU_LOW_SPEED && 372 if (speed_mode == CPUFREQ_LOW &&
367 cpu_has_feature(CPU_FTR_L3CR)) { 373 cpu_has_feature(CPU_FTR_L3CR)) {
368 l3cr = _get_L3CR(); 374 l3cr = _get_L3CR();
369 if (l3cr & L3CR_L3E) { 375 if (l3cr & L3CR_L3E) {
@@ -371,8 +377,8 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
371 _set_L3CR(0); 377 _set_L3CR(0);
372 } 378 }
373 } 379 }
374 set_speed_proc(speed_mode == PMAC_CPU_LOW_SPEED); 380 set_speed_proc(speed_mode == CPUFREQ_LOW);
375 if (speed_mode == PMAC_CPU_HIGH_SPEED && 381 if (speed_mode == CPUFREQ_HIGH &&
376 cpu_has_feature(CPU_FTR_L3CR)) { 382 cpu_has_feature(CPU_FTR_L3CR)) {
377 l3cr = _get_L3CR(); 383 l3cr = _get_L3CR();
378 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr) 384 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
@@ -380,7 +386,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
380 } 386 }
381 if (notify) 387 if (notify)
382 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
383 cur_freq = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq; 389 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
384 390
385 return 0; 391 return 0;
386} 392}
@@ -423,7 +429,8 @@ static int __pmac pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
423 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 429 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
424 policy->cur = cur_freq; 430 policy->cur = cur_freq;
425 431
426 return cpufreq_frequency_table_cpuinfo(policy, &pmac_cpu_freqs[0]); 432 cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
433 return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
427} 434}
428 435
429static u32 __pmac read_gpio(struct device_node *np) 436static u32 __pmac read_gpio(struct device_node *np)
@@ -456,8 +463,8 @@ static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, u32 state)
456 */ 463 */
457 no_schedule = 1; 464 no_schedule = 1;
458 sleep_freq = cur_freq; 465 sleep_freq = cur_freq;
459 if (cur_freq == low_freq) 466 if (cur_freq == low_freq && !is_pmu_based)
460 do_set_cpu_speed(PMAC_CPU_HIGH_SPEED, 0); 467 do_set_cpu_speed(CPUFREQ_HIGH, 0);
461 return 0; 468 return 0;
462} 469}
463 470
@@ -473,8 +480,8 @@ static int __pmac pmac_cpufreq_resume(struct cpufreq_policy *policy)
473 * is that we force a switch to whatever it was, which is 480 * is that we force a switch to whatever it was, which is
474 * probably high speed due to our suspend() routine 481 * probably high speed due to our suspend() routine
475 */ 482 */
476 do_set_cpu_speed(sleep_freq == low_freq ? PMAC_CPU_LOW_SPEED 483 do_set_cpu_speed(sleep_freq == low_freq ?
477 : PMAC_CPU_HIGH_SPEED, 0); 484 CPUFREQ_LOW : CPUFREQ_HIGH, 0);
478 485
479 no_schedule = 0; 486 no_schedule = 0;
480 return 0; 487 return 0;
@@ -488,6 +495,7 @@ static struct cpufreq_driver pmac_cpufreq_driver = {
488 .suspend = pmac_cpufreq_suspend, 495 .suspend = pmac_cpufreq_suspend,
489 .resume = pmac_cpufreq_resume, 496 .resume = pmac_cpufreq_resume,
490 .flags = CPUFREQ_PM_NO_WARN, 497 .flags = CPUFREQ_PM_NO_WARN,
498 .attr = pmac_cpu_freqs_attr,
491 .name = "powermac", 499 .name = "powermac",
492 .owner = THIS_MODULE, 500 .owner = THIS_MODULE,
493}; 501};
@@ -580,6 +588,7 @@ static int __pmac pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
580 return 1; 588 return 1;
581 hi_freq = (*value) / 1000; 589 hi_freq = (*value) / 1000;
582 set_speed_proc = pmu_set_cpu_speed; 590 set_speed_proc = pmu_set_cpu_speed;
591 is_pmu_based = 1;
583 592
584 return 0; 593 return 0;
585} 594}
@@ -684,6 +693,7 @@ static int __init pmac_cpufreq_setup(void)
684 hi_freq = cur_freq; 693 hi_freq = cur_freq;
685 low_freq = 400000; 694 low_freq = 400000;
686 set_speed_proc = pmu_set_cpu_speed; 695 set_speed_proc = pmu_set_cpu_speed;
696 is_pmu_based = 1;
687 } 697 }
688 /* Else check for TiPb 400 & 500 */ 698 /* Else check for TiPb 400 & 500 */
689 else if (machine_is_compatible("PowerBook3,2")) { 699 else if (machine_is_compatible("PowerBook3,2")) {
@@ -695,6 +705,7 @@ static int __init pmac_cpufreq_setup(void)
695 hi_freq = cur_freq; 705 hi_freq = cur_freq;
696 low_freq = 300000; 706 low_freq = 300000;
697 set_speed_proc = pmu_set_cpu_speed; 707 set_speed_proc = pmu_set_cpu_speed;
708 is_pmu_based = 1;
698 } 709 }
699 /* Else check for 750FX */ 710 /* Else check for 750FX */
700 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000) 711 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index cf5e5dd06d63..067d9a5aebc1 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -49,10 +49,10 @@
49/* PCI interrupt controller */ 49/* PCI interrupt controller */
50#define PCI_INT_STAT_REG 0xF8200000 50#define PCI_INT_STAT_REG 0xF8200000
51#define PCI_INT_MASK_REG 0xF8200004 51#define PCI_INT_MASK_REG 0xF8200004
52#define PIRQA (NR_SIU_INTS + 0) 52#define PIRQA (NR_CPM_INTS + 0)
53#define PIRQB (NR_SIU_INTS + 1) 53#define PIRQB (NR_CPM_INTS + 1)
54#define PIRQC (NR_SIU_INTS + 2) 54#define PIRQC (NR_CPM_INTS + 2)
55#define PIRQD (NR_SIU_INTS + 3) 55#define PIRQD (NR_CPM_INTS + 3)
56 56
57/* 57/*
58 * PCI memory map definitions for MPC8266ADS-PCI. 58 * PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
68 * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory 68 * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
69 */ 69 */
70 70
71/* window for a PCI master to access MPC8266 memory */ 71/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
72#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */ 72 Here we should redefine what is unique for this board */
73#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 73#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
74#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
75#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
74 76
75/* window for the processor to access PCI memory with prefetching */ 77#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
76#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 78#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
77#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
78#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
79 79
80/* window for the processor to access PCI memory without prefetching */ 80#if defined(CONFIG_ADS8272)
81#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ 81#define PCI_INT_TO_SIU SIU_INT_IRQ2
82#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ 82#elif defined(CONFIG_PQ2FADS)
83#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ 83#define PCI_INT_TO_SIU SIU_INT_IRQ6
84#else
85#warning PCI Bridge will be without interrupts support
86#endif
84 87
85/* window for the processor to access PCI I/O */
86#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
87#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
88#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
89
90#define _IO_BASE PCI_MSTR_IO_LOCAL
91#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
92#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
93#endif /* CONFIG_PCI */ 88#endif /* CONFIG_PCI */
94 89
95#endif /* __MACH_ADS8260_DEFS */ 90#endif /* __MACH_ADS8260_DEFS */
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index dd418ea3426c..96acf85800d4 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -81,7 +81,7 @@ obj-$(CONFIG_SBC82xx) += todc_time.o
81obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \ 81obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
82 todc_time.o 82 todc_time.o
83obj-$(CONFIG_8260) += m8260_setup.o 83obj-$(CONFIG_8260) += m8260_setup.o
84obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o 84obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
85obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o 85obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
86obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o 86obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
87ifeq ($(CONFIG_PPC_GEN550),y) 87ifeq ($(CONFIG_PPC_GEN550),y)
@@ -97,7 +97,7 @@ obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o
97obj-$(CONFIG_40x) += dcr.o 97obj-$(CONFIG_40x) += dcr.o
98obj-$(CONFIG_BOOKE) += dcr.o 98obj-$(CONFIG_BOOKE) += dcr.o
99obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \ 99obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
100 ppc_sys.o mpc85xx_sys.o \ 100 ppc_sys.o i8259.o mpc85xx_sys.o \
101 mpc85xx_devices.o 101 mpc85xx_devices.o
102ifeq ($(CONFIG_85xx),y) 102ifeq ($(CONFIG_85xx),y)
103obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o 103obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
diff --git a/arch/ppc/syslib/m8260_pci.c b/arch/ppc/syslib/m8260_pci.c
deleted file mode 100644
index 057cc3f8ff37..000000000000
--- a/arch/ppc/syslib/m8260_pci.c
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004 Red Hat, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31
32#include <asm/byteorder.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/uaccess.h>
36#include <asm/machdep.h>
37#include <asm/pci-bridge.h>
38#include <asm/immap_cpm2.h>
39#include <asm/mpc8260.h>
40
41#include "m8260_pci.h"
42
43
44/* PCI bus configuration registers.
45 */
46
47static void __init m8260_setup_pci(struct pci_controller *hose)
48{
49 volatile cpm2_map_t *immap = cpm2_immr;
50 unsigned long pocmr;
51 u16 tempShort;
52
53#ifndef CONFIG_ATC /* already done in U-Boot */
54 /*
55 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
56 * and local bus for PCI (SIUMCR [LBPC]).
57 */
58 immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
59#endif
60
61 /* Make PCI lowest priority */
62 /* Each 4 bits is a device bus request and the MS 4bits
63 is highest priority */
64 /* Bus 4bit value
65 --- ----------
66 CPM high 0b0000
67 CPM middle 0b0001
68 CPM low 0b0010
69 PCI reguest 0b0011
70 Reserved 0b0100
71 Reserved 0b0101
72 Internal Core 0b0110
73 External Master 1 0b0111
74 External Master 2 0b1000
75 External Master 3 0b1001
76 The rest are reserved */
77 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
78
79 /* Park bus on core while modifying PCI Bus accesses */
80 immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
81
82 /*
83 * Set up master window that allows the CPU to access PCI space. This
84 * window is set up using the first SIU PCIBR registers.
85 */
86 immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
87 immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
88
89 /* Disable machine check on no response or target abort */
90 immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
91 /* Release PCI RST (by default the PCI RST signal is held low) */
92 immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
93
94 /* give it some time */
95 mdelay(1);
96
97 /*
98 * Set up master window that allows the CPU to access PCI Memory (prefetch)
99 * space. This window is set up using the first set of Outbound ATU registers.
100 */
101 immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
102 immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
103 pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
104 immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
105
106 /*
107 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
108 * space. This window is set up using the second set of Outbound ATU registers.
109 */
110 immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
111 immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
112 pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
113 immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
114
115 /*
116 * Set up master window that allows the CPU to access PCI IO space. This window
117 * is set up using the third set of Outbound ATU registers.
118 */
119 immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
120 immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
121 pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
122 immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
123
124 /*
125 * Set up slave window that allows PCI masters to access MPC826x local memory.
126 * This window is set up using the first set of Inbound ATU registers
127 */
128
129 immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
130 immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
131 pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
132 immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
133
134 /* See above for description - puts PCI request as highest priority */
135 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
136
137 /* Park the bus on the PCI */
138 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
139
140 /* Host mode - specify the bridge as a host-PCI bridge */
141 early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
142
143 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
144 early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
145 early_write_config_word(hose, 0, 0, PCI_COMMAND,
146 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
147}
148
149void __init m8260_find_bridges(void)
150{
151 extern int pci_assign_all_busses;
152 struct pci_controller * hose;
153
154 pci_assign_all_busses = 1;
155
156 hose = pcibios_alloc_controller();
157
158 if (!hose)
159 return;
160
161 ppc_md.pci_swizzle = common_swizzle;
162
163 hose->first_busno = 0;
164 hose->bus_offset = 0;
165 hose->last_busno = 0xff;
166
167 setup_m8260_indirect_pci(hose,
168 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
169 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
170
171 m8260_setup_pci(hose);
172 hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
173
174 hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
175 MPC826x_PCI_IO_SIZE);
176 isa_io_base = (unsigned long) hose->io_base_virt;
177
178 /* setup resources */
179 pci_init_resource(&hose->mem_resources[0],
180 MPC826x_PCI_LOWER_MEM,
181 MPC826x_PCI_UPPER_MEM,
182 IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
183
184 pci_init_resource(&hose->mem_resources[1],
185 MPC826x_PCI_LOWER_MMIO,
186 MPC826x_PCI_UPPER_MMIO,
187 IORESOURCE_MEM, "PCI memory");
188
189 pci_init_resource(&hose->io_resource,
190 MPC826x_PCI_LOWER_IO,
191 MPC826x_PCI_UPPER_IO,
192 IORESOURCE_IO, "PCI I/O");
193}
diff --git a/arch/ppc/syslib/m8260_pci.h b/arch/ppc/syslib/m8260_pci.h
deleted file mode 100644
index d1352120acd7..000000000000
--- a/arch/ppc/syslib/m8260_pci.h
+++ /dev/null
@@ -1,76 +0,0 @@
1
2#ifndef _PPC_KERNEL_M8260_PCI_H
3#define _PPC_KERNEL_M8260_PCI_H
4
5#include <asm/m8260_pci.h>
6
7/*
8 * Local->PCI map (from CPU) controlled by
9 * MPC826x master window
10 *
11 * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
12 *
13 * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
14 * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
15 * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3)
16 *
17 * PCI->Local map (from PCI)
18 * MPC826x slave window controlled by
19 *
20 * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
21 */
22
23/*
24 * Slave window that allows PCI masters to access MPC826x local memory.
25 * This window is set up using the first set of Inbound ATU registers
26 */
27
28#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
29#define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
30#define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
31#define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
32#endif
33
34/*
35 * This is the window that allows the CPU to access PCI address space.
36 * It will be setup with the SIU PCIBR0 register. All three PCI master
37 * windows, which allow the CPU to access PCI prefetch, non prefetch,
38 * and IO space (see below), must all fit within this window.
39 */
40#ifndef MPC826x_PCI_BASE
41#define MPC826x_PCI_BASE 0x80000000
42#define MPC826x_PCI_MASK 0xc0000000
43#endif
44
45#ifndef MPC826x_PCI_LOWER_MEM
46#define MPC826x_PCI_LOWER_MEM 0x80000000
47#define MPC826x_PCI_UPPER_MEM 0x9fffffff
48#define MPC826x_PCI_MEM_OFFSET 0x00000000
49#endif
50
51#ifndef MPC826x_PCI_LOWER_MMIO
52#define MPC826x_PCI_LOWER_MMIO 0xa0000000
53#define MPC826x_PCI_UPPER_MMIO 0xafffffff
54#define MPC826x_PCI_MMIO_OFFSET 0x00000000
55#endif
56
57#ifndef MPC826x_PCI_LOWER_IO
58#define MPC826x_PCI_LOWER_IO 0x00000000
59#define MPC826x_PCI_UPPER_IO 0x00ffffff
60#define MPC826x_PCI_IO_BASE 0xb0000000
61#define MPC826x_PCI_IO_SIZE 0x01000000
62#endif
63
64#ifndef _IO_BASE
65#define _IO_BASE isa_io_base
66#endif
67
68#ifdef CONFIG_8260_PCI9
69struct pci_controller;
70extern void setup_m8260_indirect_pci(struct pci_controller* hose,
71 u32 cfg_addr, u32 cfg_data);
72#else
73#define setup_m8260_indirect_pci setup_indirect_pci
74#endif
75
76#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/ppc/syslib/m8260_pci_erratum9.c b/arch/ppc/syslib/m8260_pci_erratum9.c
index 9c0582d639e0..1dc7e4e1d491 100644
--- a/arch/ppc/syslib/m8260_pci_erratum9.c
+++ b/arch/ppc/syslib/m8260_pci_erratum9.c
@@ -31,7 +31,7 @@
31#include <asm/immap_cpm2.h> 31#include <asm/immap_cpm2.h>
32#include <asm/cpm2.h> 32#include <asm/cpm2.h>
33 33
34#include "m8260_pci.h" 34#include "m82xx_pci.h"
35 35
36#ifdef CONFIG_8260_PCI9 36#ifdef CONFIG_8260_PCI9
37/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */ 37/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
@@ -248,11 +248,11 @@ EXPORT_SYMBOL(idma_pci9_read_le);
248 248
249static inline int is_pci_mem(unsigned long addr) 249static inline int is_pci_mem(unsigned long addr)
250{ 250{
251 if (addr >= MPC826x_PCI_LOWER_MMIO && 251 if (addr >= M82xx_PCI_LOWER_MMIO &&
252 addr <= MPC826x_PCI_UPPER_MMIO) 252 addr <= M82xx_PCI_UPPER_MMIO)
253 return 1; 253 return 1;
254 if (addr >= MPC826x_PCI_LOWER_MEM && 254 if (addr >= M82xx_PCI_LOWER_MEM &&
255 addr <= MPC826x_PCI_UPPER_MEM) 255 addr <= M82xx_PCI_UPPER_MEM)
256 return 1; 256 return 1;
257 return 0; 257 return 0;
258} 258}
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
index 23ea3f694de2..fda75d79050c 100644
--- a/arch/ppc/syslib/m8260_setup.c
+++ b/arch/ppc/syslib/m8260_setup.c
@@ -34,7 +34,8 @@
34unsigned char __res[sizeof(bd_t)]; 34unsigned char __res[sizeof(bd_t)];
35 35
36extern void cpm2_reset(void); 36extern void cpm2_reset(void);
37extern void m8260_find_bridges(void); 37extern void pq2_find_bridges(void);
38extern void pq2pci_init_irq(void);
38extern void idma_pci9_init(void); 39extern void idma_pci9_init(void);
39 40
40/* Place-holder for board-specific init */ 41/* Place-holder for board-specific init */
@@ -56,7 +57,7 @@ m8260_setup_arch(void)
56 idma_pci9_init(); 57 idma_pci9_init();
57#endif 58#endif
58#ifdef CONFIG_PCI_8260 59#ifdef CONFIG_PCI_8260
59 m8260_find_bridges(); 60 pq2_find_bridges();
60#endif 61#endif
61#ifdef CONFIG_BLK_DEV_INITRD 62#ifdef CONFIG_BLK_DEV_INITRD
62 if (initrd_start) 63 if (initrd_start)
@@ -173,6 +174,12 @@ m8260_init_IRQ(void)
173 * in case the boot rom changed something on us. 174 * in case the boot rom changed something on us.
174 */ 175 */
175 cpm2_immr->im_intctl.ic_siprr = 0x05309770; 176 cpm2_immr->im_intctl.ic_siprr = 0x05309770;
177
178#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
179 /* Initialize stuff for the 82xx CPLD IC and install demux */
180 pq2pci_init_irq();
181#endif
182
176} 183}
177 184
178/* 185/*
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
new file mode 100644
index 000000000000..5e7a7edcea74
--- /dev/null
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -0,0 +1,383 @@
1/*
2 *
3 * (C) Copyright 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004 Red Hat, Inc.
7 *
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <linux/slab.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/interrupt.h>
37
38#include <asm/byteorder.h>
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/uaccess.h>
42#include <asm/machdep.h>
43#include <asm/pci-bridge.h>
44#include <asm/immap_cpm2.h>
45#include <asm/mpc8260.h>
46#include <asm/cpm2.h>
47
48#include "m82xx_pci.h"
49
50/*
51 * Interrupt routing
52 */
53
54static inline int
55pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
56{
57 static char pci_irq_table[][4] =
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 {
63 { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
64 { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
65 { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
66 };
67
68 const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70}
71
72static void
73pq2pci_mask_irq(unsigned int irq)
74{
75 int bit = irq - NR_CPM_INTS;
76
77 *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
78 return;
79}
80
81static void
82pq2pci_unmask_irq(unsigned int irq)
83{
84 int bit = irq - NR_CPM_INTS;
85
86 *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
87 return;
88}
89
90static void
91pq2pci_mask_and_ack(unsigned int irq)
92{
93 int bit = irq - NR_CPM_INTS;
94
95 *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
96 return;
97}
98
99static void
100pq2pci_end_irq(unsigned int irq)
101{
102 int bit = irq - NR_CPM_INTS;
103
104 *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
105 return;
106}
107
108struct hw_interrupt_type pq2pci_ic = {
109 "PQ2 PCI",
110 NULL,
111 NULL,
112 pq2pci_unmask_irq,
113 pq2pci_mask_irq,
114 pq2pci_mask_and_ack,
115 pq2pci_end_irq,
116 0
117};
118
119static irqreturn_t
120pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
121{
122 unsigned long stat, mask, pend;
123 int bit;
124
125 for(;;) {
126 stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
127 mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
128 pend = stat & ~mask & 0xf0000000;
129 if (!pend)
130 break;
131 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
132 if (pend & 0x80000000)
133 __do_IRQ(NR_CPM_INTS + bit, regs);
134 }
135 }
136
137 return IRQ_HANDLED;
138}
139
140static struct irqaction pq2pci_irqaction = {
141 .handler = pq2pci_irq_demux,
142 .flags = SA_INTERRUPT,
143 .mask = CPU_MASK_NONE,
144 .name = "PQ2 PCI cascade",
145};
146
147
148void
149pq2pci_init_irq(void)
150{
151 int irq;
152 volatile cpm2_map_t *immap = cpm2_immr;
153#if defined CONFIG_ADS8272
154 /* configure chip select for PCI interrupt controller */
155 immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
156 immap->im_memctl.memc_or3 = 0xffff8010;
157#elif defined CONFIG_PQ2FADS
158 immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
159 immap->im_memctl.memc_or8 = 0xffff8010;
160#endif
161 for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
162 irq_desc[irq].handler = &pq2pci_ic;
163
164 /* make PCI IRQ level sensitive */
165 immap->im_intctl.ic_siexr &=
166 ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
167
168 /* mask all PCI interrupts */
169 *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
170
171 /* install the demultiplexer for the PCI cascade interrupt */
172 setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
173 return;
174}
175
176static int
177pq2pci_exclude_device(u_char bus, u_char devfn)
178{
179 return PCIBIOS_SUCCESSFUL;
180}
181
182/* PCI bus configuration registers.
183 */
184static void
185pq2ads_setup_pci(struct pci_controller *hose)
186{
187 __u32 val;
188 volatile cpm2_map_t *immap = cpm2_immr;
189 bd_t* binfo = (bd_t*) __res;
190 u32 sccr = immap->im_clkrst.car_sccr;
191 uint pci_div,freq,time;
192 /* PCI int lowest prio */
193 /* Each 4 bits is a device bus request and the MS 4bits
194 is highest priority */
195 /* Bus 4bit value
196 --- ----------
197 CPM high 0b0000
198 CPM middle 0b0001
199 CPM low 0b0010
200 PCI reguest 0b0011
201 Reserved 0b0100
202 Reserved 0b0101
203 Internal Core 0b0110
204 External Master 1 0b0111
205 External Master 2 0b1000
206 External Master 3 0b1001
207 The rest are reserved
208 */
209 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
210 /* park bus on core */
211 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
212 /*
213 * Set up master windows that allow the CPU to access PCI space. These
214 * windows are set up using the two SIU PCIBR registers.
215 */
216
217 immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
218 immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
219
220#ifdef M82xx_PCI_SEC_WND_SIZE
221 immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
222 immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
223#endif
224
225#if defined CONFIG_ADS8272
226 immap->im_siu_conf.siu_82xx.sc_siumcr =
227 (immap->im_siu_conf.siu_82xx.sc_siumcr &
228 ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
229 SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
230 SIUMCR_LBPC11 | SIUMCR_APPC11 |
231 SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
232 SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
233 SIUMCR_APPC10 | SIUMCR_CS10PC00 |
234 SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
235
236#elif defined CONFIG_PQ2FADS
237 /*
238 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
239 * and local bus for PCI (SIUMCR [LBPC]).
240 */
241 immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
242 ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
243 SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
244#endif
245 /* Enable PCI */
246 immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
247
248 pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
249 ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
250 freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
251 time = (int)666666/freq;
252 /* due to PCI Local Bus spec, some devices needs to wait such a long
253 time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
254 printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
255 (time==1) ? "0.5 seconds":"1 second" );
256
257 {
258 int i;
259 for(i=0;i<(500*time);i++)
260 udelay(1000);
261 }
262
263 /* setup ATU registers */
264 immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
265 ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
266 immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
267 immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
268
269 /* Set-up non-prefetchable window */
270 immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
271 immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
272 immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
273
274 /* Set-up prefetchable window */
275 immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
276 (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
277 immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
278 immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
279
280 /* Inbound transactions from PCI memory space */
281 immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
282 ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
283 immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
284 immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
285
286#if defined CONFIG_ADS8272
287 /* PCI int highest prio */
288 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
289#elif defined CONFIG_PQ2FADS
290 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
291#endif
292 /* park bus on PCI */
293 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
294
295 /* Enable bus mastering and inbound memory transactions */
296 early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
297 val &= 0xffff0000;
298 val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
299 early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
300
301}
302
303void __init pq2_find_bridges(void)
304{
305 extern int pci_assign_all_busses;
306 struct pci_controller * hose;
307 int host_bridge;
308
309 pci_assign_all_busses = 1;
310
311 hose = pcibios_alloc_controller();
312
313 if (!hose)
314 return;
315
316 ppc_md.pci_swizzle = common_swizzle;
317
318 hose->first_busno = 0;
319 hose->bus_offset = 0;
320 hose->last_busno = 0xff;
321
322#ifdef CONFIG_ADS8272
323 hose->set_cfg_type = 1;
324#endif
325
326 setup_m8260_indirect_pci(hose,
327 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
328 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
329
330 /* Make sure it is a supported bridge */
331 early_read_config_dword(hose,
332 0,
333 PCI_DEVFN(0,0),
334 PCI_VENDOR_ID,
335 &host_bridge);
336 switch (host_bridge) {
337 case PCI_DEVICE_ID_MPC8265:
338 break;
339 case PCI_DEVICE_ID_MPC8272:
340 break;
341 default:
342 printk("Attempting to use unrecognized host bridge ID"
343 " 0x%08x.\n", host_bridge);
344 break;
345 }
346
347 pq2ads_setup_pci(hose);
348
349 hose->io_space.start = M82xx_PCI_LOWER_IO;
350 hose->io_space.end = M82xx_PCI_UPPER_IO;
351 hose->mem_space.start = M82xx_PCI_LOWER_MEM;
352 hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
353 hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
354
355 isa_io_base =
356 (unsigned long) ioremap(M82xx_PCI_IO_BASE,
357 M82xx_PCI_IO_SIZE);
358 hose->io_base_virt = (void *) isa_io_base;
359
360 /* setup resources */
361 pci_init_resource(&hose->mem_resources[0],
362 M82xx_PCI_LOWER_MEM,
363 M82xx_PCI_UPPER_MEM,
364 IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
365
366 pci_init_resource(&hose->mem_resources[1],
367 M82xx_PCI_LOWER_MMIO,
368 M82xx_PCI_UPPER_MMIO,
369 IORESOURCE_MEM, "PCI memory");
370
371 pci_init_resource(&hose->io_resource,
372 M82xx_PCI_LOWER_IO,
373 M82xx_PCI_UPPER_IO,
374 IORESOURCE_IO | 1, "PCI I/O");
375
376 ppc_md.pci_exclude_device = pq2pci_exclude_device;
377 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
378
379 ppc_md.pci_map_irq = pq2pci_map_irq;
380 ppc_md.pcibios_fixup = NULL;
381 ppc_md.pcibios_fixup_bus = NULL;
382
383}
diff --git a/arch/ppc/syslib/m82xx_pci.h b/arch/ppc/syslib/m82xx_pci.h
new file mode 100644
index 000000000000..924f73f8e595
--- /dev/null
+++ b/arch/ppc/syslib/m82xx_pci.h
@@ -0,0 +1,92 @@
1
2#ifndef _PPC_KERNEL_M82XX_PCI_H
3#define _PPC_KERNEL_M82XX_PCI_H
4
5#include <asm/m8260_pci.h>
6/*
7 * Local->PCI map (from CPU) controlled by
8 * MPC826x master window
9 *
10 * 0xF6000000 - 0xF7FFFFFF IO space
11 * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
12 *
13 * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
14 * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
15 * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
16 *
17 * PCI->Local map (from PCI)
18 * MPC826x slave window controlled by
19 *
20 * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
21 */
22
23/*
24 * Slave window that allows PCI masters to access MPC826x local memory.
25 * This window is set up using the first set of Inbound ATU registers
26 */
27
28#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
29#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
30#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
31#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
32#endif
33
34/*
35 * This is the window that allows the CPU to access PCI address space.
36 * It will be setup with the SIU PCIBR0 register. All three PCI master
37 * windows, which allow the CPU to access PCI prefetch, non prefetch,
38 * and IO space (see below), must all fit within this window.
39 */
40
41#ifndef M82xx_PCI_LOWER_MEM
42#define M82xx_PCI_LOWER_MEM 0x80000000
43#define M82xx_PCI_UPPER_MEM 0x9fffffff
44#define M82xx_PCI_MEM_OFFSET 0x00000000
45#define M82xx_PCI_MEM_SIZE 0x20000000
46#endif
47
48#ifndef M82xx_PCI_LOWER_MMIO
49#define M82xx_PCI_LOWER_MMIO 0xa0000000
50#define M82xx_PCI_UPPER_MMIO 0xafffffff
51#define M82xx_PCI_MMIO_OFFSET 0x00000000
52#define M82xx_PCI_MMIO_SIZE 0x20000000
53#endif
54
55#ifndef M82xx_PCI_LOWER_IO
56#define M82xx_PCI_LOWER_IO 0x00000000
57#define M82xx_PCI_UPPER_IO 0x01ffffff
58#define M82xx_PCI_IO_BASE 0xf6000000
59#define M82xx_PCI_IO_SIZE 0x02000000
60#endif
61
62#ifndef M82xx_PCI_PRIM_WND_SIZE
63#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
64#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
65#endif
66
67#ifndef M82xx_PCI_SEC_WND_SIZE
68#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
69#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
70#endif
71
72#ifndef POTA_ADDR_SHIFT
73#define POTA_ADDR_SHIFT 12
74#endif
75
76#ifndef PITA_ADDR_SHIFT
77#define PITA_ADDR_SHIFT 12
78#endif
79
80#ifndef _IO_BASE
81#define _IO_BASE isa_io_base
82#endif
83
84#ifdef CONFIG_8260_PCI9
85struct pci_controller;
86extern void setup_m8260_indirect_pci(struct pci_controller* hose,
87 u32 cfg_addr, u32 cfg_data);
88#else
89#define setup_m8260_indirect_pci setup_indirect_pci
90#endif
91
92#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index a5156c5179a6..e5fd2ae503ea 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -68,7 +68,7 @@ static int ocp_inited;
68/* Sysfs support */ 68/* Sysfs support */
69#define OCP_DEF_ATTR(field, format_string) \ 69#define OCP_DEF_ATTR(field, format_string) \
70static ssize_t \ 70static ssize_t \
71show_##field(struct device *dev, char *buf) \ 71show_##field(struct device *dev, struct device_attribute *attr, char *buf) \
72{ \ 72{ \
73 struct ocp_device *odev = to_ocp_dev(dev); \ 73 struct ocp_device *odev = to_ocp_dev(dev); \
74 \ 74 \
diff --git a/arch/ppc/syslib/of_device.c b/arch/ppc/syslib/of_device.c
index 46269ed21aee..49c0e34e2d6b 100644
--- a/arch/ppc/syslib/of_device.c
+++ b/arch/ppc/syslib/of_device.c
@@ -161,7 +161,7 @@ void of_unregister_driver(struct of_platform_driver *drv)
161} 161}
162 162
163 163
164static ssize_t dev_show_devspec(struct device *dev, char *buf) 164static ssize_t dev_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
165{ 165{
166 struct of_device *ofdev; 166 struct of_device *ofdev;
167 167
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 9d4ed68b5804..000ba47c67cb 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -275,7 +275,7 @@ static void __init openpic_enable_sie(void)
275} 275}
276#endif 276#endif
277 277
278#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM) 278#if defined(CONFIG_EPIC_SERIAL_MODE)
279static void openpic_reset(void) 279static void openpic_reset(void)
280{ 280{
281 openpic_setfield(&OpenPIC->Global.Global_Configuration0, 281 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
@@ -993,8 +993,6 @@ int openpic_resume(struct sys_device *sysdev)
993 return 0; 993 return 0;
994 } 994 }
995 995
996 openpic_reset();
997
998 /* OpenPIC sometimes seem to need some time to be fully back up... */ 996 /* OpenPIC sometimes seem to need some time to be fully back up... */
999 do { 997 do {
1000 openpic_set_spurious(OPENPIC_VEC_SPURIOUS); 998 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index c28f9d679484..843cf8873e60 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -29,6 +29,7 @@
29#include <asm/mmu.h> 29#include <asm/mmu.h>
30#include <asm/ppc_sys.h> 30#include <asm/ppc_sys.h>
31#include <asm/kgdb.h> 31#include <asm/kgdb.h>
32#include <asm/delay.h>
32 33
33#include <syslib/ppc83xx_setup.h> 34#include <syslib/ppc83xx_setup.h>
34 35
@@ -117,7 +118,34 @@ mpc83xx_early_serial_map(void)
117void 118void
118mpc83xx_restart(char *cmd) 119mpc83xx_restart(char *cmd)
119{ 120{
121 volatile unsigned char __iomem *reg;
122 unsigned char tmp;
123
124 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
125
120 local_irq_disable(); 126 local_irq_disable();
127
128 /*
129 * Unlock the BCSR bits so a PRST will update the contents.
130 * Otherwise the reset asserts but doesn't clear.
131 */
132 tmp = in_8(reg + BCSR_MISC_REG3_OFF);
133 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
134 out_8(reg + BCSR_MISC_REG3_OFF, tmp);
135
136 /*
137 * Trigger a reset via a low->high transition of the
138 * PORESET bit.
139 */
140 tmp = in_8(reg + BCSR_MISC_REG2_OFF);
141 tmp &= ~BCSR_MISC_REG2_PORESET;
142 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
143
144 udelay(1);
145
146 tmp |= BCSR_MISC_REG2_PORESET;
147 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
148
121 for(;;); 149 for(;;);
122} 150}
123 151
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index 152c3ef1312a..f3277f469e78 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -132,6 +132,12 @@ mpc85xx_halt(void)
132} 132}
133 133
134#ifdef CONFIG_PCI 134#ifdef CONFIG_PCI
135
136#if defined(CONFIG_MPC8555_CDS)
137extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
138extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
139#endif
140
135static void __init 141static void __init
136mpc85xx_setup_pci1(struct pci_controller *hose) 142mpc85xx_setup_pci1(struct pci_controller *hose)
137{ 143{
@@ -302,8 +308,18 @@ mpc85xx_setup_hose(void)
302 308
303 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 309 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
304 310
311#if defined(CONFIG_MPC8555_CDS)
312 /* Pre pciauto_bus_scan VIA init */
313 mpc85xx_cds_enable_via(hose_a);
314#endif
315
305 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); 316 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
306 317
318#if defined(CONFIG_MPC8555_CDS)
319 /* Post pciauto_bus_scan VIA fixup */
320 mpc85xx_cds_fixup_via(hose_a);
321#endif
322
307#ifdef CONFIG_85xx_PCI2 323#ifdef CONFIG_85xx_PCI2
308 hose_b = pcibios_alloc_controller(); 324 hose_b = pcibios_alloc_controller();
309 325
diff --git a/arch/ppc/syslib/prom_init.c b/arch/ppc/syslib/prom_init.c
index 2cee87137f2e..7f15136830f4 100644
--- a/arch/ppc/syslib/prom_init.c
+++ b/arch/ppc/syslib/prom_init.c
@@ -626,8 +626,18 @@ inspect_node(phandle node, struct device_node *dad,
626 l = call_prom("package-to-path", 3, 1, node, 626 l = call_prom("package-to-path", 3, 1, node,
627 mem_start, mem_end - mem_start); 627 mem_start, mem_end - mem_start);
628 if (l >= 0) { 628 if (l >= 0) {
629 char *p, *ep;
630
629 np->full_name = PTRUNRELOC((char *) mem_start); 631 np->full_name = PTRUNRELOC((char *) mem_start);
630 *(char *)(mem_start + l) = 0; 632 *(char *)(mem_start + l) = 0;
633 /* Fixup an Apple bug where they have bogus \0 chars in the
634 * middle of the path in some properties
635 */
636 for (p = (char *)mem_start, ep = p + l; p < ep; p++)
637 if ((*p) == '\0') {
638 memmove(p, p+1, ep - p);
639 ep--;
640 }
631 mem_start = ALIGNUL(mem_start + l + 1); 641 mem_start = ALIGNUL(mem_start + l + 1);
632 } 642 }
633 643
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 09:40:53 -0500