1 files changed, 3 insertions, 6 deletions

diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c
index 3d103d66870d..e469610efde5 100644
--- a/arch/ppc64/oprofile/op_model_power4.c
+++ b/arch/ppc64/oprofile/op_model_power4.c
@@ -23,7 +23,6 @@
 
 static unsigned long reset_value[OP_MAX_COUNTER];
 
-static int num_counters;
 static int oprofile_running;
 static int mmcra_has_sihv;
 
@@ -45,8 +44,6 @@ static void power4_reg_setup(struct op_counter_config *ctr,
 {
         int i;
 
-        num_counters = num_ctrs;
-
         /*
          * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
          * However we disable it on all POWER4 until we verify it works
@@ -68,7 +65,7 @@ static void power4_reg_setup(struct op_counter_config *ctr,
 
         backtrace_spinlocks = sys->backtrace_spinlocks;
 
-        for (i = 0; i < num_counters; ++i)
+        for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
                 reset_value[i] = 0x80000000UL - ctr[i].count;
 
         /* setup user and kernel profiling */
@@ -121,7 +118,7 @@ static void power4_start(struct op_counter_config *ctr)
         /* set the PMM bit (see comment below) */
         mtmsrd(mfmsr() | MSR_PMM);
 
-        for (i = 0; i < num_counters; ++i) {
+        for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
                 if (ctr[i].enabled) {
                         ctr_write(i, reset_value[i]);
                 } else {
@@ -272,7 +269,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
         /* set the PMM bit (see comment below) */
         mtmsrd(mfmsr() | MSR_PMM);
 
-        for (i = 0; i < num_counters; ++i) {
+        for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
                 val = ctr_read(i);
                 if (val < 0) {
                         if (oprofile_running && ctr[i].enabled) {