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-rw-r--r--arch/ppc64/kernel/mpic.c859
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diff --git a/arch/ppc64/kernel/mpic.c b/arch/ppc64/kernel/mpic.c
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1/*
2 * arch/ppc64/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#undef DEBUG
16
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/smp.h>
23#include <linux/interrupt.h>
24#include <linux/bootmem.h>
25#include <linux/spinlock.h>
26#include <linux/pci.h>
27
28#include <asm/ptrace.h>
29#include <asm/signal.h>
30#include <asm/io.h>
31#include <asm/pgtable.h>
32#include <asm/irq.h>
33#include <asm/machdep.h>
34
35#include "mpic.h"
36
37#ifdef DEBUG
38#define DBG(fmt...) printk(fmt)
39#else
40#define DBG(fmt...)
41#endif
42
43static struct mpic *mpics;
44static struct mpic *mpic_primary;
45static DEFINE_SPINLOCK(mpic_lock);
46
47
48/*
49 * Register accessor functions
50 */
51
52
53static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
54 unsigned int reg)
55{
56 if (be)
57 return in_be32(base + (reg >> 2));
58 else
59 return in_le32(base + (reg >> 2));
60}
61
62static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
63 unsigned int reg, u32 value)
64{
65 if (be)
66 out_be32(base + (reg >> 2), value);
67 else
68 out_le32(base + (reg >> 2), value);
69}
70
71static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
72{
73 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
74 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
75
76 if (mpic->flags & MPIC_BROKEN_IPI)
77 be = !be;
78 return _mpic_read(be, mpic->gregs, offset);
79}
80
81static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
82{
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
84
85 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
86}
87
88static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
89{
90 unsigned int cpu = 0;
91
92 if (mpic->flags & MPIC_PRIMARY)
93 cpu = hard_smp_processor_id();
94
95 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
96}
97
98static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
99{
100 unsigned int cpu = 0;
101
102 if (mpic->flags & MPIC_PRIMARY)
103 cpu = hard_smp_processor_id();
104
105 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
106}
107
108static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
109{
110 unsigned int isu = src_no >> mpic->isu_shift;
111 unsigned int idx = src_no & mpic->isu_mask;
112
113 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
114 reg + (idx * MPIC_IRQ_STRIDE));
115}
116
117static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
118 unsigned int reg, u32 value)
119{
120 unsigned int isu = src_no >> mpic->isu_shift;
121 unsigned int idx = src_no & mpic->isu_mask;
122
123 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
124 reg + (idx * MPIC_IRQ_STRIDE), value);
125}
126
127#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
128#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
129#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
130#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
131#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
132#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
133#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
134#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
135
136
137/*
138 * Low level utility functions
139 */
140
141
142
143/* Check if we have one of those nice broken MPICs with a flipped endian on
144 * reads from IPI registers
145 */
146static void __init mpic_test_broken_ipi(struct mpic *mpic)
147{
148 u32 r;
149
150 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
151 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
152
153 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
154 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
155 mpic->flags |= MPIC_BROKEN_IPI;
156 }
157}
158
159#ifdef CONFIG_MPIC_BROKEN_U3
160
161/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
162 * to force the edge setting on the MPIC and do the ack workaround.
163 */
164static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no)
165{
166 if (source_no >= 128 || !mpic->fixups)
167 return 0;
168 return mpic->fixups[source_no].base != NULL;
169}
170
171static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
172{
173 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
174 u32 tmp;
175
176 spin_lock(&mpic->fixup_lock);
177 writeb(0x11 + 2 * fixup->irq, fixup->base);
178 tmp = readl(fixup->base + 2);
179 writel(tmp | 0x80000000ul, fixup->base + 2);
180 /* config writes shouldn't be posted but let's be safe ... */
181 (void)readl(fixup->base + 2);
182 spin_unlock(&mpic->fixup_lock);
183}
184
185
186static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase)
187{
188 int i, irq;
189 u32 tmp;
190
191 printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase);
192
193 for (i=0; i < 24; i++) {
194 writeb(0x10 + 2*i, devbase + 0xf2);
195 tmp = readl(devbase + 0xf4);
196 if ((tmp & 0x1) || !(tmp & 0x20))
197 continue;
198 irq = (tmp >> 16) & 0xff;
199 mpic->fixups[irq].irq = i;
200 mpic->fixups[irq].base = devbase + 0xf2;
201 }
202}
203
204static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase)
205{
206 int i, irq;
207 u32 tmp;
208
209 printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase);
210
211 for (i=0; i < 4; i++) {
212 writeb(0x10 + 2*i, devbase + 0xba);
213 tmp = readl(devbase + 0xbc);
214 if ((tmp & 0x1) || !(tmp & 0x20))
215 continue;
216 irq = (tmp >> 16) & 0xff;
217 mpic->fixups[irq].irq = i;
218 mpic->fixups[irq].base = devbase + 0xba;
219 }
220}
221
222static void __init mpic_scan_ioapics(struct mpic *mpic)
223{
224 unsigned int devfn;
225 u8 __iomem *cfgspace;
226
227 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n");
228
229 /* Allocate fixups array */
230 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
231 BUG_ON(mpic->fixups == NULL);
232 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
233
234 /* Init spinlock */
235 spin_lock_init(&mpic->fixup_lock);
236
237 /* Map u3 config space. We assume all IO-APICs are on the primary bus
238 * and slot will never be above "0xf" so we only need to map 32k
239 */
240 cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000);
241 BUG_ON(cfgspace == NULL);
242
243 /* Now we scan all slots. We do a very quick scan, we read the header type,
244 * vendor ID and device ID only, that's plenty enough
245 */
246 for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) {
247 u8 __iomem *devbase = cfgspace + (devfn << 8);
248 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
249 u32 l = readl(devbase + PCI_VENDOR_ID);
250 u16 vendor_id, device_id;
251 int multifunc = 0;
252
253 DBG("devfn %x, l: %x\n", devfn, l);
254
255 /* If no device, skip */
256 if (l == 0xffffffff || l == 0x00000000 ||
257 l == 0x0000ffff || l == 0xffff0000)
258 goto next;
259
260 /* Check if it's a multifunction device (only really used
261 * to function 0 though
262 */
263 multifunc = !!(hdr_type & 0x80);
264 vendor_id = l & 0xffff;
265 device_id = (l >> 16) & 0xffff;
266
267 /* If a known device, go to fixup setup code */
268 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460)
269 mpic_amd8111_read_irq(mpic, devbase);
270 if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450)
271 mpic_amd8131_read_irq(mpic, devbase);
272 next:
273 /* next device, if function 0 */
274 if ((PCI_FUNC(devfn) == 0) && !multifunc)
275 devfn += 7;
276 }
277}
278
279#endif /* CONFIG_MPIC_BROKEN_U3 */
280
281
282/* Find an mpic associated with a given linux interrupt */
283static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
284{
285 struct mpic *mpic = mpics;
286
287 while(mpic) {
288 /* search IPIs first since they may override the main interrupts */
289 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
290 if (is_ipi)
291 *is_ipi = 1;
292 return mpic;
293 }
294 if (irq >= mpic->irq_offset &&
295 irq < (mpic->irq_offset + mpic->irq_count)) {
296 if (is_ipi)
297 *is_ipi = 0;
298 return mpic;
299 }
300 mpic = mpic -> next;
301 }
302 return NULL;
303}
304
305/* Convert a cpu mask from logical to physical cpu numbers. */
306static inline u32 mpic_physmask(u32 cpumask)
307{
308 int i;
309 u32 mask = 0;
310
311 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
312 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
313 return mask;
314}
315
316#ifdef CONFIG_SMP
317/* Get the mpic structure from the IPI number */
318static inline struct mpic * mpic_from_ipi(unsigned int ipi)
319{
320 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
321}
322#endif
323
324/* Get the mpic structure from the irq number */
325static inline struct mpic * mpic_from_irq(unsigned int irq)
326{
327 return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
328}
329
330/* Send an EOI */
331static inline void mpic_eoi(struct mpic *mpic)
332{
333 mpic_cpu_write(MPIC_CPU_EOI, 0);
334 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
335}
336
337#ifdef CONFIG_SMP
338static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
339{
340 struct mpic *mpic = dev_id;
341
342 smp_message_recv(irq - mpic->ipi_offset, regs);
343 return IRQ_HANDLED;
344}
345#endif /* CONFIG_SMP */
346
347/*
348 * Linux descriptor level callbacks
349 */
350
351
352static void mpic_enable_irq(unsigned int irq)
353{
354 unsigned int loops = 100000;
355 struct mpic *mpic = mpic_from_irq(irq);
356 unsigned int src = irq - mpic->irq_offset;
357
358 DBG("%s: enable_irq: %d (src %d)\n", mpic->name, irq, src);
359
360 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
361 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & ~MPIC_VECPRI_MASK);
362
363 /* make sure mask gets to controller before we return to user */
364 do {
365 if (!loops--) {
366 printk(KERN_ERR "mpic_enable_irq timeout\n");
367 break;
368 }
369 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
370}
371
372static void mpic_disable_irq(unsigned int irq)
373{
374 unsigned int loops = 100000;
375 struct mpic *mpic = mpic_from_irq(irq);
376 unsigned int src = irq - mpic->irq_offset;
377
378 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
379
380 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
381 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | MPIC_VECPRI_MASK);
382
383 /* make sure mask gets to controller before we return to user */
384 do {
385 if (!loops--) {
386 printk(KERN_ERR "mpic_enable_irq timeout\n");
387 break;
388 }
389 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
390}
391
392static void mpic_end_irq(unsigned int irq)
393{
394 struct mpic *mpic = mpic_from_irq(irq);
395
396 DBG("%s: end_irq: %d\n", mpic->name, irq);
397
398 /* We always EOI on end_irq() even for edge interrupts since that
399 * should only lower the priority, the MPIC should have properly
400 * latched another edge interrupt coming in anyway
401 */
402
403#ifdef CONFIG_MPIC_BROKEN_U3
404 if (mpic->flags & MPIC_BROKEN_U3) {
405 unsigned int src = irq - mpic->irq_offset;
406 if (mpic_is_ht_interrupt(mpic, src))
407 mpic_apic_end_irq(mpic, src);
408 }
409#endif /* CONFIG_MPIC_BROKEN_U3 */
410
411 mpic_eoi(mpic);
412}
413
414#ifdef CONFIG_SMP
415
416static void mpic_enable_ipi(unsigned int irq)
417{
418 struct mpic *mpic = mpic_from_ipi(irq);
419 unsigned int src = irq - mpic->ipi_offset;
420
421 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
422 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
423}
424
425static void mpic_disable_ipi(unsigned int irq)
426{
427 /* NEVER disable an IPI... that's just plain wrong! */
428}
429
430static void mpic_end_ipi(unsigned int irq)
431{
432 struct mpic *mpic = mpic_from_ipi(irq);
433
434 /*
435 * IPIs are marked IRQ_PER_CPU. This has the side effect of
436 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
437 * applying to them. We EOI them late to avoid re-entering.
438 * We mark IPI's with SA_INTERRUPT as they must run with
439 * irqs disabled.
440 */
441 mpic_eoi(mpic);
442}
443
444#endif /* CONFIG_SMP */
445
446static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
447{
448 struct mpic *mpic = mpic_from_irq(irq);
449
450 cpumask_t tmp;
451
452 cpus_and(tmp, cpumask, cpu_online_map);
453
454 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
455 mpic_physmask(cpus_addr(tmp)[0]));
456}
457
458
459/*
460 * Exported functions
461 */
462
463
464struct mpic * __init mpic_alloc(unsigned long phys_addr,
465 unsigned int flags,
466 unsigned int isu_size,
467 unsigned int irq_offset,
468 unsigned int irq_count,
469 unsigned int ipi_offset,
470 unsigned char *senses,
471 unsigned int senses_count,
472 const char *name)
473{
474 struct mpic *mpic;
475 u32 reg;
476 const char *vers;
477 int i;
478
479 mpic = alloc_bootmem(sizeof(struct mpic));
480 if (mpic == NULL)
481 return NULL;
482
483 memset(mpic, 0, sizeof(struct mpic));
484 mpic->name = name;
485
486 mpic->hc_irq.typename = name;
487 mpic->hc_irq.enable = mpic_enable_irq;
488 mpic->hc_irq.disable = mpic_disable_irq;
489 mpic->hc_irq.end = mpic_end_irq;
490 if (flags & MPIC_PRIMARY)
491 mpic->hc_irq.set_affinity = mpic_set_affinity;
492#ifdef CONFIG_SMP
493 mpic->hc_ipi.typename = name;
494 mpic->hc_ipi.enable = mpic_enable_ipi;
495 mpic->hc_ipi.disable = mpic_disable_ipi;
496 mpic->hc_ipi.end = mpic_end_ipi;
497#endif /* CONFIG_SMP */
498
499 mpic->flags = flags;
500 mpic->isu_size = isu_size;
501 mpic->irq_offset = irq_offset;
502 mpic->irq_count = irq_count;
503 mpic->ipi_offset = ipi_offset;
504 mpic->num_sources = 0; /* so far */
505 mpic->senses = senses;
506 mpic->senses_count = senses_count;
507
508 /* Map the global registers */
509 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
510 mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2);
511 BUG_ON(mpic->gregs == NULL);
512
513 /* Reset */
514 if (flags & MPIC_WANTS_RESET) {
515 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
516 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
517 | MPIC_GREG_GCONF_RESET);
518 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
519 & MPIC_GREG_GCONF_RESET)
520 mb();
521 }
522
523 /* Read feature register, calculate num CPUs and, for non-ISU
524 * MPICs, num sources as well. On ISU MPICs, sources are counted
525 * as ISUs are added
526 */
527 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
528 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
529 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
530 if (isu_size == 0)
531 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
532 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
533
534 /* Map the per-CPU registers */
535 for (i = 0; i < mpic->num_cpus; i++) {
536 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
537 i * MPIC_CPU_STRIDE, 0x1000);
538 BUG_ON(mpic->cpuregs[i] == NULL);
539 }
540
541 /* Initialize main ISU if none provided */
542 if (mpic->isu_size == 0) {
543 mpic->isu_size = mpic->num_sources;
544 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
545 MPIC_IRQ_STRIDE * mpic->isu_size);
546 BUG_ON(mpic->isus[0] == NULL);
547 }
548 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
549 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
550
551 /* Display version */
552 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
553 case 1:
554 vers = "1.0";
555 break;
556 case 2:
557 vers = "1.2";
558 break;
559 case 3:
560 vers = "1.3";
561 break;
562 default:
563 vers = "<unknown>";
564 break;
565 }
566 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
567 name, vers, phys_addr, mpic->num_cpus);
568 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
569 mpic->isu_shift, mpic->isu_mask);
570
571 mpic->next = mpics;
572 mpics = mpic;
573
574 if (flags & MPIC_PRIMARY)
575 mpic_primary = mpic;
576
577 return mpic;
578}
579
580void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
581 unsigned long phys_addr)
582{
583 unsigned int isu_first = isu_num * mpic->isu_size;
584
585 BUG_ON(isu_num >= MPIC_MAX_ISU);
586
587 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
588 if ((isu_first + mpic->isu_size) > mpic->num_sources)
589 mpic->num_sources = isu_first + mpic->isu_size;
590}
591
592void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
593 void *data)
594{
595 struct mpic *mpic = mpic_find(irq, NULL);
596 unsigned long flags;
597
598 /* Synchronization here is a bit dodgy, so don't try to replace cascade
599 * interrupts on the fly too often ... but normally it's set up at boot.
600 */
601 spin_lock_irqsave(&mpic_lock, flags);
602 if (mpic->cascade)
603 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
604 mpic->cascade = NULL;
605 wmb();
606 mpic->cascade_vec = irq - mpic->irq_offset;
607 mpic->cascade_data = data;
608 wmb();
609 mpic->cascade = handler;
610 mpic_enable_irq(irq);
611 spin_unlock_irqrestore(&mpic_lock, flags);
612}
613
614void __init mpic_init(struct mpic *mpic)
615{
616 int i;
617
618 BUG_ON(mpic->num_sources == 0);
619
620 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
621
622 /* Set current processor priority to max */
623 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
624
625 /* Initialize timers: just disable them all */
626 for (i = 0; i < 4; i++) {
627 mpic_write(mpic->tmregs,
628 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
629 mpic_write(mpic->tmregs,
630 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
631 MPIC_VECPRI_MASK |
632 (MPIC_VEC_TIMER_0 + i));
633 }
634
635 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
636 mpic_test_broken_ipi(mpic);
637 for (i = 0; i < 4; i++) {
638 mpic_ipi_write(i,
639 MPIC_VECPRI_MASK |
640 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
641 (MPIC_VEC_IPI_0 + i));
642#ifdef CONFIG_SMP
643 if (!(mpic->flags & MPIC_PRIMARY))
644 continue;
645 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
646 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
647
648#endif /* CONFIG_SMP */
649 }
650
651 /* Initialize interrupt sources */
652 if (mpic->irq_count == 0)
653 mpic->irq_count = mpic->num_sources;
654
655#ifdef CONFIG_MPIC_BROKEN_U3
656 /* Do the ioapic fixups on U3 broken mpic */
657 DBG("MPIC flags: %x\n", mpic->flags);
658 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
659 mpic_scan_ioapics(mpic);
660#endif /* CONFIG_MPIC_BROKEN_U3 */
661
662 for (i = 0; i < mpic->num_sources; i++) {
663 /* start with vector = source number, and masked */
664 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
665 int level = 0;
666
667 /* if it's an IPI, we skip it */
668 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
669 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
670 continue;
671
672 /* do senses munging */
673 if (mpic->senses && i < mpic->senses_count) {
674 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
675 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
676 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
677 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
678 } else
679 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
680
681 /* remember if it was a level interrupts */
682 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
683
684 /* deal with broken U3 */
685 if (mpic->flags & MPIC_BROKEN_U3) {
686#ifdef CONFIG_MPIC_BROKEN_U3
687 if (mpic_is_ht_interrupt(mpic, i)) {
688 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
689 MPIC_VECPRI_POLARITY_MASK);
690 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
691 }
692#else
693 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
694#endif
695 }
696
697 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
698 (level != 0));
699
700 /* init hw */
701 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
702 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
703 1 << get_hard_smp_processor_id(boot_cpuid));
704
705 /* init linux descriptors */
706 if (i < mpic->irq_count) {
707 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
708 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
709 }
710 }
711
712 /* Init spurrious vector */
713 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
714
715 /* Disable 8259 passthrough */
716 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
717 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
718 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
719
720 /* Set current processor priority to 0 */
721 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
722}
723
724
725
726void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
727{
728 int is_ipi;
729 struct mpic *mpic = mpic_find(irq, &is_ipi);
730 unsigned long flags;
731 u32 reg;
732
733 spin_lock_irqsave(&mpic_lock, flags);
734 if (is_ipi) {
735 reg = mpic_ipi_read(irq - mpic->ipi_offset) & MPIC_VECPRI_PRIORITY_MASK;
736 mpic_ipi_write(irq - mpic->ipi_offset,
737 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
738 } else {
739 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI)
740 & MPIC_VECPRI_PRIORITY_MASK;
741 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
742 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
743 }
744 spin_unlock_irqrestore(&mpic_lock, flags);
745}
746
747unsigned int mpic_irq_get_priority(unsigned int irq)
748{
749 int is_ipi;
750 struct mpic *mpic = mpic_find(irq, &is_ipi);
751 unsigned long flags;
752 u32 reg;
753
754 spin_lock_irqsave(&mpic_lock, flags);
755 if (is_ipi)
756 reg = mpic_ipi_read(irq - mpic->ipi_offset);
757 else
758 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
759 spin_unlock_irqrestore(&mpic_lock, flags);
760 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
761}
762
763void mpic_setup_this_cpu(void)
764{
765#ifdef CONFIG_SMP
766 struct mpic *mpic = mpic_primary;
767 unsigned long flags;
768 u32 msk = 1 << hard_smp_processor_id();
769 unsigned int i;
770
771 BUG_ON(mpic == NULL);
772
773 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
774
775 spin_lock_irqsave(&mpic_lock, flags);
776
777 /* let the mpic know we want intrs. default affinity is 0xffffffff
778 * until changed via /proc. That's how it's done on x86. If we want
779 * it differently, then we should make sure we also change the default
780 * values of irq_affinity in irq.c.
781 */
782 if (distribute_irqs) {
783 for (i = 0; i < mpic->num_sources ; i++)
784 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
785 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
786 }
787
788 /* Set current processor priority to 0 */
789 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
790
791 spin_unlock_irqrestore(&mpic_lock, flags);
792#endif /* CONFIG_SMP */
793}
794
795void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
796{
797 struct mpic *mpic = mpic_primary;
798
799 BUG_ON(mpic == NULL);
800
801 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
802
803 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
804 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
805}
806
807int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
808{
809 u32 irq;
810
811 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
812 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
813
814 if (mpic->cascade && irq == mpic->cascade_vec) {
815 DBG("%s: cascading ...\n", mpic->name);
816 irq = mpic->cascade(regs, mpic->cascade_data);
817 mpic_eoi(mpic);
818 return irq;
819 }
820 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
821 return -1;
822 if (irq < MPIC_VEC_IPI_0)
823 return irq + mpic->irq_offset;
824 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
825 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
826}
827
828int mpic_get_irq(struct pt_regs *regs)
829{
830 struct mpic *mpic = mpic_primary;
831
832 BUG_ON(mpic == NULL);
833
834 return mpic_get_one_irq(mpic, regs);
835}
836
837
838#ifdef CONFIG_SMP
839void mpic_request_ipis(void)
840{
841 struct mpic *mpic = mpic_primary;
842
843 BUG_ON(mpic == NULL);
844
845 printk("requesting IPIs ... \n");
846
847 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
848 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
849 "IPI0 (call function)", mpic);
850 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
851 "IPI1 (reschedule)", mpic);
852 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
853 "IPI2 (unused)", mpic);
854 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
855 "IPI3 (debugger break)", mpic);
856
857 printk("IPIs requested... \n");
858}
859#endif /* CONFIG_SMP */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:55:58 -0500