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-rw-r--r--arch/ppc64/kernel/cputable.c90
1 files changed, 77 insertions, 13 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 4847f2ac8c9f..8831a28c3c4e 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -19,6 +19,7 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/module.h> 20#include <linux/module.h>
21 21
22#include <asm/oprofile_impl.h>
22#include <asm/cputable.h> 23#include <asm/cputable.h>
23 24
24struct cpu_spec* cur_cpu_spec = NULL; 25struct cpu_spec* cur_cpu_spec = NULL;
@@ -54,24 +55,32 @@ struct cpu_spec cpu_specs[] = {
54 .pvr_value = 0x00400000, 55 .pvr_value = 0x00400000,
55 .cpu_name = "POWER3 (630)", 56 .cpu_name = "POWER3 (630)",
56 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 57 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
57 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 58 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
58 CPU_FTR_PMC8,
59 .cpu_user_features = COMMON_USER_PPC64, 59 .cpu_user_features = COMMON_USER_PPC64,
60 .icache_bsize = 128, 60 .icache_bsize = 128,
61 .dcache_bsize = 128, 61 .dcache_bsize = 128,
62 .num_pmcs = 8,
62 .cpu_setup = __setup_cpu_power3, 63 .cpu_setup = __setup_cpu_power3,
64#ifdef CONFIG_OPROFILE
65 .oprofile_cpu_type = "ppc64/power3",
66 .oprofile_model = &op_model_rs64,
67#endif
63 }, 68 },
64 { /* Power3+ */ 69 { /* Power3+ */
65 .pvr_mask = 0xffff0000, 70 .pvr_mask = 0xffff0000,
66 .pvr_value = 0x00410000, 71 .pvr_value = 0x00410000,
67 .cpu_name = "POWER3 (630+)", 72 .cpu_name = "POWER3 (630+)",
68 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 73 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
69 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 74 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
70 CPU_FTR_PMC8,
71 .cpu_user_features = COMMON_USER_PPC64, 75 .cpu_user_features = COMMON_USER_PPC64,
72 .icache_bsize = 128, 76 .icache_bsize = 128,
73 .dcache_bsize = 128, 77 .dcache_bsize = 128,
78 .num_pmcs = 8,
74 .cpu_setup = __setup_cpu_power3, 79 .cpu_setup = __setup_cpu_power3,
80#ifdef CONFIG_OPROFILE
81 .oprofile_cpu_type = "ppc64/power3",
82 .oprofile_model = &op_model_rs64,
83#endif
75 }, 84 },
76 { /* Northstar */ 85 { /* Northstar */
77 .pvr_mask = 0xffff0000, 86 .pvr_mask = 0xffff0000,
@@ -79,11 +88,16 @@ struct cpu_spec cpu_specs[] = {
79 .cpu_name = "RS64-II (northstar)", 88 .cpu_name = "RS64-II (northstar)",
80 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 89 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
81 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 90 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
82 CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, 91 CPU_FTR_MMCRA | CPU_FTR_CTRL,
83 .cpu_user_features = COMMON_USER_PPC64, 92 .cpu_user_features = COMMON_USER_PPC64,
84 .icache_bsize = 128, 93 .icache_bsize = 128,
85 .dcache_bsize = 128, 94 .dcache_bsize = 128,
95 .num_pmcs = 8,
86 .cpu_setup = __setup_cpu_power3, 96 .cpu_setup = __setup_cpu_power3,
97#ifdef CONFIG_OPROFILE
98 .oprofile_cpu_type = "ppc64/rs64",
99 .oprofile_model = &op_model_rs64,
100#endif
87 }, 101 },
88 { /* Pulsar */ 102 { /* Pulsar */
89 .pvr_mask = 0xffff0000, 103 .pvr_mask = 0xffff0000,
@@ -91,11 +105,16 @@ struct cpu_spec cpu_specs[] = {
91 .cpu_name = "RS64-III (pulsar)", 105 .cpu_name = "RS64-III (pulsar)",
92 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 106 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
93 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 107 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
94 CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, 108 CPU_FTR_MMCRA | CPU_FTR_CTRL,
95 .cpu_user_features = COMMON_USER_PPC64, 109 .cpu_user_features = COMMON_USER_PPC64,
96 .icache_bsize = 128, 110 .icache_bsize = 128,
97 .dcache_bsize = 128, 111 .dcache_bsize = 128,
112 .num_pmcs = 8,
98 .cpu_setup = __setup_cpu_power3, 113 .cpu_setup = __setup_cpu_power3,
114#ifdef CONFIG_OPROFILE
115 .oprofile_cpu_type = "ppc64/rs64",
116 .oprofile_model = &op_model_rs64,
117#endif
99 }, 118 },
100 { /* I-star */ 119 { /* I-star */
101 .pvr_mask = 0xffff0000, 120 .pvr_mask = 0xffff0000,
@@ -103,11 +122,16 @@ struct cpu_spec cpu_specs[] = {
103 .cpu_name = "RS64-III (icestar)", 122 .cpu_name = "RS64-III (icestar)",
104 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 123 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
105 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 124 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
106 CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, 125 CPU_FTR_MMCRA | CPU_FTR_CTRL,
107 .cpu_user_features = COMMON_USER_PPC64, 126 .cpu_user_features = COMMON_USER_PPC64,
108 .icache_bsize = 128, 127 .icache_bsize = 128,
109 .dcache_bsize = 128, 128 .dcache_bsize = 128,
129 .num_pmcs = 8,
110 .cpu_setup = __setup_cpu_power3, 130 .cpu_setup = __setup_cpu_power3,
131#ifdef CONFIG_OPROFILE
132 .oprofile_cpu_type = "ppc64/rs64",
133 .oprofile_model = &op_model_rs64,
134#endif
111 }, 135 },
112 { /* S-star */ 136 { /* S-star */
113 .pvr_mask = 0xffff0000, 137 .pvr_mask = 0xffff0000,
@@ -115,11 +139,16 @@ struct cpu_spec cpu_specs[] = {
115 .cpu_name = "RS64-IV (sstar)", 139 .cpu_name = "RS64-IV (sstar)",
116 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 140 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
117 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | 141 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
118 CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL, 142 CPU_FTR_MMCRA | CPU_FTR_CTRL,
119 .cpu_user_features = COMMON_USER_PPC64, 143 .cpu_user_features = COMMON_USER_PPC64,
120 .icache_bsize = 128, 144 .icache_bsize = 128,
121 .dcache_bsize = 128, 145 .dcache_bsize = 128,
146 .num_pmcs = 8,
122 .cpu_setup = __setup_cpu_power3, 147 .cpu_setup = __setup_cpu_power3,
148#ifdef CONFIG_OPROFILE
149 .oprofile_cpu_type = "ppc64/rs64",
150 .oprofile_model = &op_model_rs64,
151#endif
123 }, 152 },
124 { /* Power4 */ 153 { /* Power4 */
125 .pvr_mask = 0xffff0000, 154 .pvr_mask = 0xffff0000,
@@ -127,11 +156,16 @@ struct cpu_spec cpu_specs[] = {
127 .cpu_name = "POWER4 (gp)", 156 .cpu_name = "POWER4 (gp)",
128 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 157 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
129 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 158 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
130 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, 159 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
131 .cpu_user_features = COMMON_USER_PPC64, 160 .cpu_user_features = COMMON_USER_PPC64,
132 .icache_bsize = 128, 161 .icache_bsize = 128,
133 .dcache_bsize = 128, 162 .dcache_bsize = 128,
163 .num_pmcs = 8,
134 .cpu_setup = __setup_cpu_power4, 164 .cpu_setup = __setup_cpu_power4,
165#ifdef CONFIG_OPROFILE
166 .oprofile_cpu_type = "ppc64/power4",
167 .oprofile_model = &op_model_rs64,
168#endif
135 }, 169 },
136 { /* Power4+ */ 170 { /* Power4+ */
137 .pvr_mask = 0xffff0000, 171 .pvr_mask = 0xffff0000,
@@ -139,11 +173,16 @@ struct cpu_spec cpu_specs[] = {
139 .cpu_name = "POWER4+ (gq)", 173 .cpu_name = "POWER4+ (gq)",
140 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 174 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
141 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 175 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
142 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, 176 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
143 .cpu_user_features = COMMON_USER_PPC64, 177 .cpu_user_features = COMMON_USER_PPC64,
144 .icache_bsize = 128, 178 .icache_bsize = 128,
145 .dcache_bsize = 128, 179 .dcache_bsize = 128,
180 .num_pmcs = 8,
146 .cpu_setup = __setup_cpu_power4, 181 .cpu_setup = __setup_cpu_power4,
182#ifdef CONFIG_OPROFILE
183 .oprofile_cpu_type = "ppc64/power4",
184 .oprofile_model = &op_model_power4,
185#endif
147 }, 186 },
148 { /* PPC970 */ 187 { /* PPC970 */
149 .pvr_mask = 0xffff0000, 188 .pvr_mask = 0xffff0000,
@@ -152,12 +191,17 @@ struct cpu_spec cpu_specs[] = {
152 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 191 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
153 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 192 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
154 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | 193 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
155 CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, 194 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
156 .cpu_user_features = COMMON_USER_PPC64 | 195 .cpu_user_features = COMMON_USER_PPC64 |
157 PPC_FEATURE_HAS_ALTIVEC_COMP, 196 PPC_FEATURE_HAS_ALTIVEC_COMP,
158 .icache_bsize = 128, 197 .icache_bsize = 128,
159 .dcache_bsize = 128, 198 .dcache_bsize = 128,
199 .num_pmcs = 8,
160 .cpu_setup = __setup_cpu_ppc970, 200 .cpu_setup = __setup_cpu_ppc970,
201#ifdef CONFIG_OPROFILE
202 .oprofile_cpu_type = "ppc64/970",
203 .oprofile_model = &op_model_power4,
204#endif
161 }, 205 },
162 { /* PPC970FX */ 206 { /* PPC970FX */
163 .pvr_mask = 0xffff0000, 207 .pvr_mask = 0xffff0000,
@@ -166,12 +210,17 @@ struct cpu_spec cpu_specs[] = {
166 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 210 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
167 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 211 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
168 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | 212 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
169 CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, 213 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
170 .cpu_user_features = COMMON_USER_PPC64 | 214 .cpu_user_features = COMMON_USER_PPC64 |
171 PPC_FEATURE_HAS_ALTIVEC_COMP, 215 PPC_FEATURE_HAS_ALTIVEC_COMP,
172 .icache_bsize = 128, 216 .icache_bsize = 128,
173 .dcache_bsize = 128, 217 .dcache_bsize = 128,
218 .num_pmcs = 8,
174 .cpu_setup = __setup_cpu_ppc970, 219 .cpu_setup = __setup_cpu_ppc970,
220#ifdef CONFIG_OPROFILE
221 .oprofile_cpu_type = "ppc64/970",
222 .oprofile_model = &op_model_power4,
223#endif
175 }, 224 },
176 { /* PPC970MP */ 225 { /* PPC970MP */
177 .pvr_mask = 0xffff0000, 226 .pvr_mask = 0xffff0000,
@@ -180,12 +229,16 @@ struct cpu_spec cpu_specs[] = {
180 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 229 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
181 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 230 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
182 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | 231 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
183 CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, 232 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
184 .cpu_user_features = COMMON_USER_PPC64 | 233 .cpu_user_features = COMMON_USER_PPC64 |
185 PPC_FEATURE_HAS_ALTIVEC_COMP, 234 PPC_FEATURE_HAS_ALTIVEC_COMP,
186 .icache_bsize = 128, 235 .icache_bsize = 128,
187 .dcache_bsize = 128, 236 .dcache_bsize = 128,
188 .cpu_setup = __setup_cpu_ppc970, 237 .cpu_setup = __setup_cpu_ppc970,
238#ifdef CONFIG_OPROFILE
239 .oprofile_cpu_type = "ppc64/970",
240 .oprofile_model = &op_model_power4,
241#endif
189 }, 242 },
190 { /* Power5 */ 243 { /* Power5 */
191 .pvr_mask = 0xffff0000, 244 .pvr_mask = 0xffff0000,
@@ -199,7 +252,12 @@ struct cpu_spec cpu_specs[] = {
199 .cpu_user_features = COMMON_USER_PPC64, 252 .cpu_user_features = COMMON_USER_PPC64,
200 .icache_bsize = 128, 253 .icache_bsize = 128,
201 .dcache_bsize = 128, 254 .dcache_bsize = 128,
255 .num_pmcs = 6,
202 .cpu_setup = __setup_cpu_power4, 256 .cpu_setup = __setup_cpu_power4,
257#ifdef CONFIG_OPROFILE
258 .oprofile_cpu_type = "ppc64/power5",
259 .oprofile_model = &op_model_power4,
260#endif
203 }, 261 },
204 { /* Power5 */ 262 { /* Power5 */
205 .pvr_mask = 0xffff0000, 263 .pvr_mask = 0xffff0000,
@@ -213,7 +271,12 @@ struct cpu_spec cpu_specs[] = {
213 .cpu_user_features = COMMON_USER_PPC64, 271 .cpu_user_features = COMMON_USER_PPC64,
214 .icache_bsize = 128, 272 .icache_bsize = 128,
215 .dcache_bsize = 128, 273 .dcache_bsize = 128,
274 .num_pmcs = 6,
216 .cpu_setup = __setup_cpu_power4, 275 .cpu_setup = __setup_cpu_power4,
276#ifdef CONFIG_OPROFILE
277 .oprofile_cpu_type = "ppc64/power5",
278 .oprofile_model = &op_model_power4,
279#endif
217 }, 280 },
218 { /* BE DD1.x */ 281 { /* BE DD1.x */
219 .pvr_mask = 0xffff0000, 282 .pvr_mask = 0xffff0000,
@@ -239,6 +302,7 @@ struct cpu_spec cpu_specs[] = {
239 .cpu_user_features = COMMON_USER_PPC64, 302 .cpu_user_features = COMMON_USER_PPC64,
240 .icache_bsize = 128, 303 .icache_bsize = 128,
241 .dcache_bsize = 128, 304 .dcache_bsize = 128,
305 .num_pmcs = 6,
242 .cpu_setup = __setup_cpu_power4, 306 .cpu_setup = __setup_cpu_power4,
243 } 307 }
244}; 308};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:29:59 -0500