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-rw-r--r--arch/ppc64/kernel/cputable.c40
1 files changed, 1 insertions, 39 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 77cec42f9525..4847f2ac8c9f 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Modifications for ppc64: 6 * Modifications for ppc64:
7 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 7 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 11 * as published by the Free Software Foundation; either version
@@ -60,7 +60,6 @@ struct cpu_spec cpu_specs[] = {
60 .icache_bsize = 128, 60 .icache_bsize = 128,
61 .dcache_bsize = 128, 61 .dcache_bsize = 128,
62 .cpu_setup = __setup_cpu_power3, 62 .cpu_setup = __setup_cpu_power3,
63 .firmware_features = COMMON_PPC64_FW,
64 }, 63 },
65 { /* Power3+ */ 64 { /* Power3+ */
66 .pvr_mask = 0xffff0000, 65 .pvr_mask = 0xffff0000,
@@ -73,7 +72,6 @@ struct cpu_spec cpu_specs[] = {
73 .icache_bsize = 128, 72 .icache_bsize = 128,
74 .dcache_bsize = 128, 73 .dcache_bsize = 128,
75 .cpu_setup = __setup_cpu_power3, 74 .cpu_setup = __setup_cpu_power3,
76 .firmware_features = COMMON_PPC64_FW,
77 }, 75 },
78 { /* Northstar */ 76 { /* Northstar */
79 .pvr_mask = 0xffff0000, 77 .pvr_mask = 0xffff0000,
@@ -86,7 +84,6 @@ struct cpu_spec cpu_specs[] = {
86 .icache_bsize = 128, 84 .icache_bsize = 128,
87 .dcache_bsize = 128, 85 .dcache_bsize = 128,
88 .cpu_setup = __setup_cpu_power3, 86 .cpu_setup = __setup_cpu_power3,
89 .firmware_features = COMMON_PPC64_FW,
90 }, 87 },
91 { /* Pulsar */ 88 { /* Pulsar */
92 .pvr_mask = 0xffff0000, 89 .pvr_mask = 0xffff0000,
@@ -99,7 +96,6 @@ struct cpu_spec cpu_specs[] = {
99 .icache_bsize = 128, 96 .icache_bsize = 128,
100 .dcache_bsize = 128, 97 .dcache_bsize = 128,
101 .cpu_setup = __setup_cpu_power3, 98 .cpu_setup = __setup_cpu_power3,
102 .firmware_features = COMMON_PPC64_FW,
103 }, 99 },
104 { /* I-star */ 100 { /* I-star */
105 .pvr_mask = 0xffff0000, 101 .pvr_mask = 0xffff0000,
@@ -112,7 +108,6 @@ struct cpu_spec cpu_specs[] = {
112 .icache_bsize = 128, 108 .icache_bsize = 128,
113 .dcache_bsize = 128, 109 .dcache_bsize = 128,
114 .cpu_setup = __setup_cpu_power3, 110 .cpu_setup = __setup_cpu_power3,
115 .firmware_features = COMMON_PPC64_FW,
116 }, 111 },
117 { /* S-star */ 112 { /* S-star */
118 .pvr_mask = 0xffff0000, 113 .pvr_mask = 0xffff0000,
@@ -125,7 +120,6 @@ struct cpu_spec cpu_specs[] = {
125 .icache_bsize = 128, 120 .icache_bsize = 128,
126 .dcache_bsize = 128, 121 .dcache_bsize = 128,
127 .cpu_setup = __setup_cpu_power3, 122 .cpu_setup = __setup_cpu_power3,
128 .firmware_features = COMMON_PPC64_FW,
129 }, 123 },
130 { /* Power4 */ 124 { /* Power4 */
131 .pvr_mask = 0xffff0000, 125 .pvr_mask = 0xffff0000,
@@ -138,7 +132,6 @@ struct cpu_spec cpu_specs[] = {
138 .icache_bsize = 128, 132 .icache_bsize = 128,
139 .dcache_bsize = 128, 133 .dcache_bsize = 128,
140 .cpu_setup = __setup_cpu_power4, 134 .cpu_setup = __setup_cpu_power4,
141 .firmware_features = COMMON_PPC64_FW,
142 }, 135 },
143 { /* Power4+ */ 136 { /* Power4+ */
144 .pvr_mask = 0xffff0000, 137 .pvr_mask = 0xffff0000,
@@ -151,7 +144,6 @@ struct cpu_spec cpu_specs[] = {
151 .icache_bsize = 128, 144 .icache_bsize = 128,
152 .dcache_bsize = 128, 145 .dcache_bsize = 128,
153 .cpu_setup = __setup_cpu_power4, 146 .cpu_setup = __setup_cpu_power4,
154 .firmware_features = COMMON_PPC64_FW,
155 }, 147 },
156 { /* PPC970 */ 148 { /* PPC970 */
157 .pvr_mask = 0xffff0000, 149 .pvr_mask = 0xffff0000,
@@ -166,7 +158,6 @@ struct cpu_spec cpu_specs[] = {
166 .icache_bsize = 128, 158 .icache_bsize = 128,
167 .dcache_bsize = 128, 159 .dcache_bsize = 128,
168 .cpu_setup = __setup_cpu_ppc970, 160 .cpu_setup = __setup_cpu_ppc970,
169 .firmware_features = COMMON_PPC64_FW,
170 }, 161 },
171 { /* PPC970FX */ 162 { /* PPC970FX */
172 .pvr_mask = 0xffff0000, 163 .pvr_mask = 0xffff0000,
@@ -181,7 +172,6 @@ struct cpu_spec cpu_specs[] = {
181 .icache_bsize = 128, 172 .icache_bsize = 128,
182 .dcache_bsize = 128, 173 .dcache_bsize = 128,
183 .cpu_setup = __setup_cpu_ppc970, 174 .cpu_setup = __setup_cpu_ppc970,
184 .firmware_features = COMMON_PPC64_FW,
185 }, 175 },
186 { /* PPC970MP */ 176 { /* PPC970MP */
187 .pvr_mask = 0xffff0000, 177 .pvr_mask = 0xffff0000,
@@ -196,7 +186,6 @@ struct cpu_spec cpu_specs[] = {
196 .icache_bsize = 128, 186 .icache_bsize = 128,
197 .dcache_bsize = 128, 187 .dcache_bsize = 128,
198 .cpu_setup = __setup_cpu_ppc970, 188 .cpu_setup = __setup_cpu_ppc970,
199 .firmware_features = COMMON_PPC64_FW,
200 }, 189 },
201 { /* Power5 */ 190 { /* Power5 */
202 .pvr_mask = 0xffff0000, 191 .pvr_mask = 0xffff0000,
@@ -211,7 +200,6 @@ struct cpu_spec cpu_specs[] = {
211 .icache_bsize = 128, 200 .icache_bsize = 128,
212 .dcache_bsize = 128, 201 .dcache_bsize = 128,
213 .cpu_setup = __setup_cpu_power4, 202 .cpu_setup = __setup_cpu_power4,
214 .firmware_features = COMMON_PPC64_FW,
215 }, 203 },
216 { /* Power5 */ 204 { /* Power5 */
217 .pvr_mask = 0xffff0000, 205 .pvr_mask = 0xffff0000,
@@ -226,7 +214,6 @@ struct cpu_spec cpu_specs[] = {
226 .icache_bsize = 128, 214 .icache_bsize = 128,
227 .dcache_bsize = 128, 215 .dcache_bsize = 128,
228 .cpu_setup = __setup_cpu_power4, 216 .cpu_setup = __setup_cpu_power4,
229 .firmware_features = COMMON_PPC64_FW,
230 }, 217 },
231 { /* BE DD1.x */ 218 { /* BE DD1.x */
232 .pvr_mask = 0xffff0000, 219 .pvr_mask = 0xffff0000,
@@ -241,7 +228,6 @@ struct cpu_spec cpu_specs[] = {
241 .icache_bsize = 128, 228 .icache_bsize = 128,
242 .dcache_bsize = 128, 229 .dcache_bsize = 128,
243 .cpu_setup = __setup_cpu_be, 230 .cpu_setup = __setup_cpu_be,
244 .firmware_features = COMMON_PPC64_FW,
245 }, 231 },
246 { /* default match */ 232 { /* default match */
247 .pvr_mask = 0x00000000, 233 .pvr_mask = 0x00000000,
@@ -254,29 +240,5 @@ struct cpu_spec cpu_specs[] = {
254 .icache_bsize = 128, 240 .icache_bsize = 128,
255 .dcache_bsize = 128, 241 .dcache_bsize = 128,
256 .cpu_setup = __setup_cpu_power4, 242 .cpu_setup = __setup_cpu_power4,
257 .firmware_features = COMMON_PPC64_FW,
258 } 243 }
259}; 244};
260
261firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
262 {FW_FEATURE_PFT, "hcall-pft"},
263 {FW_FEATURE_TCE, "hcall-tce"},
264 {FW_FEATURE_SPRG0, "hcall-sprg0"},
265 {FW_FEATURE_DABR, "hcall-dabr"},
266 {FW_FEATURE_COPY, "hcall-copy"},
267 {FW_FEATURE_ASR, "hcall-asr"},
268 {FW_FEATURE_DEBUG, "hcall-debug"},
269 {FW_FEATURE_PERF, "hcall-perf"},
270 {FW_FEATURE_DUMP, "hcall-dump"},
271 {FW_FEATURE_INTERRUPT, "hcall-interrupt"},
272 {FW_FEATURE_MIGRATE, "hcall-migrate"},
273 {FW_FEATURE_PERFMON, "hcall-perfmon"},
274 {FW_FEATURE_CRQ, "hcall-crq"},
275 {FW_FEATURE_VIO, "hcall-vio"},
276 {FW_FEATURE_RDMA, "hcall-rdma"},
277 {FW_FEATURE_LLAN, "hcall-lLAN"},
278 {FW_FEATURE_BULK, "hcall-bulk"},
279 {FW_FEATURE_XDABR, "hcall-xdabr"},
280 {FW_FEATURE_MULTITCE, "hcall-multi-tce"},
281 {FW_FEATURE_SPLPAR, "hcall-splpar"},
282};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 05:06:37 -0500