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1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <linux/posix_types.h>
22#include "ansidecl.h"
23#include "ppc.h"
24
25/* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
30 the .text section.
31
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
34 file. */
35
36/* Local insertion and extraction functions. */
37
38static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
39static long extract_bat PARAMS ((unsigned long, int *));
40static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
41static long extract_bba PARAMS ((unsigned long, int *));
42static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
43static long extract_bd PARAMS ((unsigned long, int *));
44static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
45static long extract_bdm PARAMS ((unsigned long, int *));
46static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
47static long extract_bdp PARAMS ((unsigned long, int *));
48static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
49static long extract_bo PARAMS ((unsigned long, int *));
50static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
51static long extract_boe PARAMS ((unsigned long, int *));
52static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
53static long extract_ds PARAMS ((unsigned long, int *));
54static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
55static long extract_li PARAMS ((unsigned long, int *));
56static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
57static long extract_mbe PARAMS ((unsigned long, int *));
58static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
59static long extract_mb6 PARAMS ((unsigned long, int *));
60static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
61static long extract_nb PARAMS ((unsigned long, int *));
62static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
63static long extract_nsi PARAMS ((unsigned long, int *));
64static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
65static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
66static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
67static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
68static long extract_rbs PARAMS ((unsigned long, int *));
69static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
70static long extract_sh6 PARAMS ((unsigned long, int *));
71static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
72static long extract_spr PARAMS ((unsigned long, int *));
73static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
74static long extract_tbr PARAMS ((unsigned long, int *));
75
76/* The operands table.
77
78 The fields are bits, shift, signed, insert, extract, flags. */
79
80const struct powerpc_operand powerpc_operands[] =
81{
82 /* The zero index is used to indicate the end of the list of
83 operands. */
84#define UNUSED (0)
85 { 0, 0, NULL, NULL, 0 },
86
87 /* The BA field in an XL form instruction. */
88#define BA (1)
89#define BA_MASK (0x1f << 16)
90 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
91
92 /* The BA field in an XL form instruction when it must be the same
93 as the BT field in the same instruction. */
94#define BAT (2)
95 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
96
97 /* The BB field in an XL form instruction. */
98#define BB (3)
99#define BB_MASK (0x1f << 11)
100 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
101
102 /* The BB field in an XL form instruction when it must be the same
103 as the BA field in the same instruction. */
104#define BBA (4)
105 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
106
107 /* The BD field in a B form instruction. The lower two bits are
108 forced to zero. */
109#define BD (5)
110 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
111
112 /* The BD field in a B form instruction when absolute addressing is
113 used. */
114#define BDA (6)
115 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
116
117 /* The BD field in a B form instruction when the - modifier is used.
118 This sets the y bit of the BO field appropriately. */
119#define BDM (7)
120 { 16, 0, insert_bdm, extract_bdm,
121 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
122
123 /* The BD field in a B form instruction when the - modifier is used
124 and absolute address is used. */
125#define BDMA (8)
126 { 16, 0, insert_bdm, extract_bdm,
127 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
128
129 /* The BD field in a B form instruction when the + modifier is used.
130 This sets the y bit of the BO field appropriately. */
131#define BDP (9)
132 { 16, 0, insert_bdp, extract_bdp,
133 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
134
135 /* The BD field in a B form instruction when the + modifier is used
136 and absolute addressing is used. */
137#define BDPA (10)
138 { 16, 0, insert_bdp, extract_bdp,
139 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
140
141 /* The BF field in an X or XL form instruction. */
142#define BF (11)
143 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
144
145 /* An optional BF field. This is used for comparison instructions,
146 in which an omitted BF field is taken as zero. */
147#define OBF (12)
148 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
149
150 /* The BFA field in an X or XL form instruction. */
151#define BFA (13)
152 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
153
154 /* The BI field in a B form or XL form instruction. */
155#define BI (14)
156#define BI_MASK (0x1f << 16)
157 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
158
159 /* The BO field in a B form instruction. Certain values are
160 illegal. */
161#define BO (15)
162#define BO_MASK (0x1f << 21)
163 { 5, 21, insert_bo, extract_bo, 0 },
164
165 /* The BO field in a B form instruction when the + or - modifier is
166 used. This is like the BO field, but it must be even. */
167#define BOE (16)
168 { 5, 21, insert_boe, extract_boe, 0 },
169
170 /* The BT field in an X or XL form instruction. */
171#define BT (17)
172 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
173
174 /* The condition register number portion of the BI field in a B form
175 or XL form instruction. This is used for the extended
176 conditional branch mnemonics, which set the lower two bits of the
177 BI field. This field is optional. */
178#define CR (18)
179 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
180
181 /* The D field in a D form instruction. This is a displacement off
182 a register, and implies that the next operand is a register in
183 parentheses. */
184#define D (19)
185 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
186
187 /* The DS field in a DS form instruction. This is like D, but the
188 lower two bits are forced to zero. */
189#define DS (20)
190 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
191
192 /* The FL1 field in a POWER SC form instruction. */
193#define FL1 (21)
194 { 4, 12, NULL, NULL, 0 },
195
196 /* The FL2 field in a POWER SC form instruction. */
197#define FL2 (22)
198 { 3, 2, NULL, NULL, 0 },
199
200 /* The FLM field in an XFL form instruction. */
201#define FLM (23)
202 { 8, 17, NULL, NULL, 0 },
203
204 /* The FRA field in an X or A form instruction. */
205#define FRA (24)
206#define FRA_MASK (0x1f << 16)
207 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
208
209 /* The FRB field in an X or A form instruction. */
210#define FRB (25)
211#define FRB_MASK (0x1f << 11)
212 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
213
214 /* The FRC field in an A form instruction. */
215#define FRC (26)
216#define FRC_MASK (0x1f << 6)
217 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
218
219 /* The FRS field in an X form instruction or the FRT field in a D, X
220 or A form instruction. */
221#define FRS (27)
222#define FRT (FRS)
223 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
224
225 /* The FXM field in an XFX instruction. */
226#define FXM (28)
227#define FXM_MASK (0xff << 12)
228 { 8, 12, NULL, NULL, 0 },
229
230 /* The L field in a D or X form instruction. */
231#define L (29)
232 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
233
234 /* The LEV field in a POWER SC form instruction. */
235#define LEV (30)
236 { 7, 5, NULL, NULL, 0 },
237
238 /* The LI field in an I form instruction. The lower two bits are
239 forced to zero. */
240#define LI (31)
241 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
242
243 /* The LI field in an I form instruction when used as an absolute
244 address. */
245#define LIA (32)
246 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
247
248 /* The MB field in an M form instruction. */
249#define MB (33)
250#define MB_MASK (0x1f << 6)
251 { 5, 6, NULL, NULL, 0 },
252
253 /* The ME field in an M form instruction. */
254#define ME (34)
255#define ME_MASK (0x1f << 1)
256 { 5, 1, NULL, NULL, 0 },
257
258 /* The MB and ME fields in an M form instruction expressed a single
259 operand which is a bitmask indicating which bits to select. This
260 is a two operand form using PPC_OPERAND_NEXT. See the
261 description in opcode/ppc.h for what this means. */
262#define MBE (35)
263 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
264 { 32, 0, insert_mbe, extract_mbe, 0 },
265
266 /* The MB or ME field in an MD or MDS form instruction. The high
267 bit is wrapped to the low end. */
268#define MB6 (37)
269#define ME6 (MB6)
270#define MB6_MASK (0x3f << 5)
271 { 6, 5, insert_mb6, extract_mb6, 0 },
272
273 /* The NB field in an X form instruction. The value 32 is stored as
274 0. */
275#define NB (38)
276 { 6, 11, insert_nb, extract_nb, 0 },
277
278 /* The NSI field in a D form instruction. This is the same as the
279 SI field, only negated. */
280#define NSI (39)
281 { 16, 0, insert_nsi, extract_nsi,
282 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
283
284 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
285#define RA (40)
286#define RA_MASK (0x1f << 16)
287 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
288
289 /* The RA field in a D or X form instruction which is an updating
290 load, which means that the RA field may not be zero and may not
291 equal the RT field. */
292#define RAL (41)
293 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
294
295 /* The RA field in an lmw instruction, which has special value
296 restrictions. */
297#define RAM (42)
298 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
299
300 /* The RA field in a D or X form instruction which is an updating
301 store or an updating floating point load, which means that the RA
302 field may not be zero. */
303#define RAS (43)
304 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
305
306 /* The RB field in an X, XO, M, or MDS form instruction. */
307#define RB (44)
308#define RB_MASK (0x1f << 11)
309 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
310
311 /* The RB field in an X form instruction when it must be the same as
312 the RS field in the instruction. This is used for extended
313 mnemonics like mr. */
314#define RBS (45)
315 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
316
317 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
318 instruction or the RT field in a D, DS, X, XFX or XO form
319 instruction. */
320#define RS (46)
321#define RT (RS)
322#define RT_MASK (0x1f << 21)
323 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
324
325 /* The SH field in an X or M form instruction. */
326#define SH (47)
327#define SH_MASK (0x1f << 11)
328 { 5, 11, NULL, NULL, 0 },
329
330 /* The SH field in an MD form instruction. This is split. */
331#define SH6 (48)
332#define SH6_MASK ((0x1f << 11) | (1 << 1))
333 { 6, 1, insert_sh6, extract_sh6, 0 },
334
335 /* The SI field in a D form instruction. */
336#define SI (49)
337 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
338
339 /* The SI field in a D form instruction when we accept a wide range
340 of positive values. */
341#define SISIGNOPT (50)
342 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
343
344 /* The SPR field in an XFX form instruction. This is flipped--the
345 lower 5 bits are stored in the upper 5 and vice- versa. */
346#define SPR (51)
347#define SPR_MASK (0x3ff << 11)
348 { 10, 11, insert_spr, extract_spr, 0 },
349
350 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
351#define SPRBAT (52)
352#define SPRBAT_MASK (0x3 << 17)
353 { 2, 17, NULL, NULL, 0 },
354
355 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
356#define SPRG (53)
357#define SPRG_MASK (0x3 << 16)
358 { 2, 16, NULL, NULL, 0 },
359
360 /* The SR field in an X form instruction. */
361#define SR (54)
362 { 4, 16, NULL, NULL, 0 },
363
364 /* The SV field in a POWER SC form instruction. */
365#define SV (55)
366 { 14, 2, NULL, NULL, 0 },
367
368 /* The TBR field in an XFX form instruction. This is like the SPR
369 field, but it is optional. */
370#define TBR (56)
371 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
372
373 /* The TO field in a D or X form instruction. */
374#define TO (57)
375#define TO_MASK (0x1f << 21)
376 { 5, 21, NULL, NULL, 0 },
377
378 /* The U field in an X form instruction. */
379#define U (58)
380 { 4, 12, NULL, NULL, 0 },
381
382 /* The UI field in a D form instruction. */
383#define UI (59)
384 { 16, 0, NULL, NULL, 0 },
385};
386
387/* The functions used to insert and extract complicated operands. */
388
389/* The BA field in an XL form instruction when it must be the same as
390 the BT field in the same instruction. This operand is marked FAKE.
391 The insertion function just copies the BT field into the BA field,
392 and the extraction function just checks that the fields are the
393 same. */
394
395/*ARGSUSED*/
396static unsigned long
397insert_bat(unsigned long insn, long value, const char **errmsg)
398{
399 return insn | (((insn >> 21) & 0x1f) << 16);
400}
401
402static long
403extract_bat(unsigned long insn, int *invalid)
404{
405 if (invalid != (int *) NULL
406 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
407 *invalid = 1;
408 return 0;
409}
410
411/* The BB field in an XL form instruction when it must be the same as
412 the BA field in the same instruction. This operand is marked FAKE.
413 The insertion function just copies the BA field into the BB field,
414 and the extraction function just checks that the fields are the
415 same. */
416
417/*ARGSUSED*/
418static unsigned long
419insert_bba(unsigned long insn, long value, const char **errmsg)
420{
421 return insn | (((insn >> 16) & 0x1f) << 11);
422}
423
424static long
425extract_bba(unsigned long insn, int *invalid)
426{
427 if (invalid != (int *) NULL
428 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
429 *invalid = 1;
430 return 0;
431}
432
433/* The BD field in a B form instruction. The lower two bits are
434 forced to zero. */
435
436/*ARGSUSED*/
437static unsigned long
438insert_bd(unsigned long insn, long value, const char **errmsg)
439{
440 return insn | (value & 0xfffc);
441}
442
443/*ARGSUSED*/
444static long
445extract_bd(unsigned long insn, int *invalid)
446{
447 if ((insn & 0x8000) != 0)
448 return (insn & 0xfffc) - 0x10000;
449 else
450 return insn & 0xfffc;
451}
452
453/* The BD field in a B form instruction when the - modifier is used.
454 This modifier means that the branch is not expected to be taken.
455 We must set the y bit of the BO field to 1 if the offset is
456 negative. When extracting, we require that the y bit be 1 and that
457 the offset be positive, since if the y bit is 0 we just want to
458 print the normal form of the instruction. */
459
460/*ARGSUSED*/
461static unsigned long
462insert_bdm(unsigned long insn, long value, const char **errmsg)
463{
464 if ((value & 0x8000) != 0)
465 insn |= 1 << 21;
466 return insn | (value & 0xfffc);
467}
468
469static long
470extract_bdm(unsigned long insn, int *invalid)
471{
472 if (invalid != (int *) NULL
473 && ((insn & (1 << 21)) == 0
474 || (insn & (1 << 15)) == 0))
475 *invalid = 1;
476 if ((insn & 0x8000) != 0)
477 return (insn & 0xfffc) - 0x10000;
478 else
479 return insn & 0xfffc;
480}
481
482/* The BD field in a B form instruction when the + modifier is used.
483 This is like BDM, above, except that the branch is expected to be
484 taken. */
485
486/*ARGSUSED*/
487static unsigned long
488insert_bdp(unsigned long insn, long value, const char **errmsg)
489{
490 if ((value & 0x8000) == 0)
491 insn |= 1 << 21;
492 return insn | (value & 0xfffc);
493}
494
495static long
496extract_bdp(unsigned long insn, int *invalid)
497{
498 if (invalid != (int *) NULL
499 && ((insn & (1 << 21)) == 0
500 || (insn & (1 << 15)) != 0))
501 *invalid = 1;
502 if ((insn & 0x8000) != 0)
503 return (insn & 0xfffc) - 0x10000;
504 else
505 return insn & 0xfffc;
506}
507
508/* Check for legal values of a BO field. */
509
510static int
511valid_bo (long value)
512{
513 /* Certain encodings have bits that are required to be zero. These
514 are (z must be zero, y may be anything):
515 001zy
516 011zy
517 1z00y
518 1z01y
519 1z1zz
520 */
521 switch (value & 0x14)
522 {
523 default:
524 case 0:
525 return 1;
526 case 0x4:
527 return (value & 0x2) == 0;
528 case 0x10:
529 return (value & 0x8) == 0;
530 case 0x14:
531 return value == 0x14;
532 }
533}
534
535/* The BO field in a B form instruction. Warn about attempts to set
536 the field to an illegal value. */
537
538static unsigned long
539insert_bo(unsigned long insn, long value, const char **errmsg)
540{
541 if (errmsg != (const char **) NULL
542 && ! valid_bo (value))
543 *errmsg = "invalid conditional option";
544 return insn | ((value & 0x1f) << 21);
545}
546
547static long
548extract_bo(unsigned long insn, int *invalid)
549{
550 long value;
551
552 value = (insn >> 21) & 0x1f;
553 if (invalid != (int *) NULL
554 && ! valid_bo (value))
555 *invalid = 1;
556 return value;
557}
558
559/* The BO field in a B form instruction when the + or - modifier is
560 used. This is like the BO field, but it must be even. When
561 extracting it, we force it to be even. */
562
563static unsigned long
564insert_boe(unsigned long insn, long value, const char **errmsg)
565{
566 if (errmsg != (const char **) NULL)
567 {
568 if (! valid_bo (value))
569 *errmsg = "invalid conditional option";
570 else if ((value & 1) != 0)
571 *errmsg = "attempt to set y bit when using + or - modifier";
572 }
573 return insn | ((value & 0x1f) << 21);
574}
575
576static long
577extract_boe(unsigned long insn, int *invalid)
578{
579 long value;
580
581 value = (insn >> 21) & 0x1f;
582 if (invalid != (int *) NULL
583 && ! valid_bo (value))
584 *invalid = 1;
585 return value & 0x1e;
586}
587
588/* The DS field in a DS form instruction. This is like D, but the
589 lower two bits are forced to zero. */
590
591/*ARGSUSED*/
592static unsigned long
593insert_ds(unsigned long insn, long value, const char **errmsg)
594{
595 return insn | (value & 0xfffc);
596}
597
598/*ARGSUSED*/
599static long
600extract_ds(unsigned long insn, int *invalid)
601{
602 if ((insn & 0x8000) != 0)
603 return (insn & 0xfffc) - 0x10000;
604 else
605 return insn & 0xfffc;
606}
607
608/* The LI field in an I form instruction. The lower two bits are
609 forced to zero. */
610
611/*ARGSUSED*/
612static unsigned long
613insert_li(unsigned long insn, long value, const char **errmsg)
614{
615 return insn | (value & 0x3fffffc);
616}
617
618/*ARGSUSED*/
619static long
620extract_li(unsigned long insn, int *invalid)
621{
622 if ((insn & 0x2000000) != 0)
623 return (insn & 0x3fffffc) - 0x4000000;
624 else
625 return insn & 0x3fffffc;
626}
627
628/* The MB and ME fields in an M form instruction expressed as a single
629 operand which is itself a bitmask. The extraction function always
630 marks it as invalid, since we never want to recognize an
631 instruction which uses a field of this type. */
632
633static unsigned long
634insert_mbe(unsigned long insn, long value, const char **errmsg)
635{
636 unsigned long uval;
637 int mb, me;
638
639 uval = value;
640
641 if (uval == 0)
642 {
643 if (errmsg != (const char **) NULL)
644 *errmsg = "illegal bitmask";
645 return insn;
646 }
647
648 me = 31;
649 while ((uval & 1) == 0)
650 {
651 uval >>= 1;
652 --me;
653 }
654
655 mb = me;
656 uval >>= 1;
657 while ((uval & 1) != 0)
658 {
659 uval >>= 1;
660 --mb;
661 }
662
663 if (uval != 0)
664 {
665 if (errmsg != (const char **) NULL)
666 *errmsg = "illegal bitmask";
667 }
668
669 return insn | (mb << 6) | (me << 1);
670}
671
672static long
673extract_mbe(unsigned long insn, int *invalid)
674{
675 long ret;
676 int mb, me;
677 int i;
678
679 if (invalid != (int *) NULL)
680 *invalid = 1;
681
682 ret = 0;
683 mb = (insn >> 6) & 0x1f;
684 me = (insn >> 1) & 0x1f;
685 for (i = mb; i < me; i++)
686 ret |= 1 << (31 - i);
687 return ret;
688}
689
690/* The MB or ME field in an MD or MDS form instruction. The high bit
691 is wrapped to the low end. */
692
693/*ARGSUSED*/
694static unsigned long
695insert_mb6(unsigned long insn, long value, const char **errmsg)
696{
697 return insn | ((value & 0x1f) << 6) | (value & 0x20);
698}
699
700/*ARGSUSED*/
701static long
702extract_mb6(unsigned long insn, int *invalid)
703{
704 return ((insn >> 6) & 0x1f) | (insn & 0x20);
705}
706
707/* The NB field in an X form instruction. The value 32 is stored as
708 0. */
709
710static unsigned long
711insert_nb(unsigned long insn, long value, const char **errmsg)
712{
713 if (value < 0 || value > 32)
714 *errmsg = "value out of range";
715 if (value == 32)
716 value = 0;
717 return insn | ((value & 0x1f) << 11);
718}
719
720/*ARGSUSED*/
721static long
722extract_nb(unsigned long insn, int *invalid)
723{
724 long ret;
725
726 ret = (insn >> 11) & 0x1f;
727 if (ret == 0)
728 ret = 32;
729 return ret;
730}
731
732/* The NSI field in a D form instruction. This is the same as the SI
733 field, only negated. The extraction function always marks it as
734 invalid, since we never want to recognize an instruction which uses
735 a field of this type. */
736
737/*ARGSUSED*/
738static unsigned long
739insert_nsi(unsigned long insn, long value, const char **errmsg)
740{
741 return insn | ((- value) & 0xffff);
742}
743
744static long
745extract_nsi(unsigned long insn, int *invalid)
746{
747 if (invalid != (int *) NULL)
748 *invalid = 1;
749 if ((insn & 0x8000) != 0)
750 return - ((insn & 0xffff) - 0x10000);
751 else
752 return - (insn & 0xffff);
753}
754
755/* The RA field in a D or X form instruction which is an updating
756 load, which means that the RA field may not be zero and may not
757 equal the RT field. */
758
759static unsigned long
760insert_ral(unsigned long insn, long value, const char **errmsg)
761{
762 if (value == 0
763 || value == ((insn >> 21) & 0x1f))
764 *errmsg = "invalid register operand when updating";
765 return insn | ((value & 0x1f) << 16);
766}
767
768/* The RA field in an lmw instruction, which has special value
769 restrictions. */
770
771static unsigned long
772insert_ram(unsigned long insn, long value, const char **errmsg)
773{
774 if (value >= ((insn >> 21) & 0x1f))
775 *errmsg = "index register in load range";
776 return insn | ((value & 0x1f) << 16);
777}
778
779/* The RA field in a D or X form instruction which is an updating
780 store or an updating floating point load, which means that the RA
781 field may not be zero. */
782
783static unsigned long
784insert_ras(unsigned long insn, long value, const char **errmsg)
785{
786 if (value == 0)
787 *errmsg = "invalid register operand when updating";
788 return insn | ((value & 0x1f) << 16);
789}
790
791/* The RB field in an X form instruction when it must be the same as
792 the RS field in the instruction. This is used for extended
793 mnemonics like mr. This operand is marked FAKE. The insertion
794 function just copies the BT field into the BA field, and the
795 extraction function just checks that the fields are the same. */
796
797/*ARGSUSED*/
798static unsigned long
799insert_rbs(unsigned long insn, long value, const char **errmsg)
800{
801 return insn | (((insn >> 21) & 0x1f) << 11);
802}
803
804static long
805extract_rbs(unsigned long insn, int *invalid)
806{
807 if (invalid != (int *) NULL
808 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
809 *invalid = 1;
810 return 0;
811}
812
813/* The SH field in an MD form instruction. This is split. */
814
815/*ARGSUSED*/
816static unsigned long
817insert_sh6(unsigned long insn, long value, const char **errmsg)
818{
819 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
820}
821
822/*ARGSUSED*/
823static long
824extract_sh6(unsigned long insn, int *invalid)
825{
826 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
827}
828
829/* The SPR field in an XFX form instruction. This is flipped--the
830 lower 5 bits are stored in the upper 5 and vice- versa. */
831
832static unsigned long
833insert_spr(unsigned long insn, long value, const char **errmsg)
834{
835 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
836}
837
838static long
839extract_spr(unsigned long insn, int *invalid)
840{
841 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
842}
843
844/* The TBR field in an XFX instruction. This is just like SPR, but it
845 is optional. When TBR is omitted, it must be inserted as 268 (the
846 magic number of the TB register). These functions treat 0
847 (indicating an omitted optional operand) as 268. This means that
848 ``mftb 4,0'' is not handled correctly. This does not matter very
849 much, since the architecture manual does not define mftb as
850 accepting any values other than 268 or 269. */
851
852#define TB (268)
853
854static unsigned long
855insert_tbr(unsigned long insn, long value, const char **errmsg)
856{
857 if (value == 0)
858 value = TB;
859 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
860}
861
862static long
863extract_tbr(unsigned long insn, int *invalid)
864{
865 long ret;
866
867 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
868 if (ret == TB)
869 ret = 0;
870 return ret;
871}
872
873/* Macros used to form opcodes. */
874
875/* The main opcode. */
876#define OP(x) (((x) & 0x3f) << 26)
877#define OP_MASK OP (0x3f)
878
879/* The main opcode combined with a trap code in the TO field of a D
880 form instruction. Used for extended mnemonics for the trap
881 instructions. */
882#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
883#define OPTO_MASK (OP_MASK | TO_MASK)
884
885/* The main opcode combined with a comparison size bit in the L field
886 of a D form or X form instruction. Used for extended mnemonics for
887 the comparison instructions. */
888#define OPL(x,l) (OP (x) | (((l) & 1) << 21))
889#define OPL_MASK OPL (0x3f,1)
890
891/* An A form instruction. */
892#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
893#define A_MASK A (0x3f, 0x1f, 1)
894
895/* An A_MASK with the FRB field fixed. */
896#define AFRB_MASK (A_MASK | FRB_MASK)
897
898/* An A_MASK with the FRC field fixed. */
899#define AFRC_MASK (A_MASK | FRC_MASK)
900
901/* An A_MASK with the FRA and FRC fields fixed. */
902#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
903
904/* A B form instruction. */
905#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
906#define B_MASK B (0x3f, 1, 1)
907
908/* A B form instruction setting the BO field. */
909#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
910#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
911
912/* A BBO_MASK with the y bit of the BO field removed. This permits
913 matching a conditional branch regardless of the setting of the y
914 bit. */
915#define Y_MASK (1 << 21)
916#define BBOY_MASK (BBO_MASK &~ Y_MASK)
917
918/* A B form instruction setting the BO field and the condition bits of
919 the BI field. */
920#define BBOCB(op, bo, cb, aa, lk) \
921 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
922#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
923
924/* A BBOCB_MASK with the y bit of the BO field removed. */
925#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
926
927/* A BBOYCB_MASK in which the BI field is fixed. */
928#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
929
930/* The main opcode mask with the RA field clear. */
931#define DRA_MASK (OP_MASK | RA_MASK)
932
933/* A DS form instruction. */
934#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
935#define DS_MASK DSO (0x3f, 3)
936
937/* An M form instruction. */
938#define M(op, rc) (OP (op) | ((rc) & 1))
939#define M_MASK M (0x3f, 1)
940
941/* An M form instruction with the ME field specified. */
942#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
943
944/* An M_MASK with the MB and ME fields fixed. */
945#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
946
947/* An M_MASK with the SH and ME fields fixed. */
948#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
949
950/* An MD form instruction. */
951#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
952#define MD_MASK MD (0x3f, 0x7, 1)
953
954/* An MD_MASK with the MB field fixed. */
955#define MDMB_MASK (MD_MASK | MB6_MASK)
956
957/* An MD_MASK with the SH field fixed. */
958#define MDSH_MASK (MD_MASK | SH6_MASK)
959
960/* An MDS form instruction. */
961#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
962#define MDS_MASK MDS (0x3f, 0xf, 1)
963
964/* An MDS_MASK with the MB field fixed. */
965#define MDSMB_MASK (MDS_MASK | MB6_MASK)
966
967/* An SC form instruction. */
968#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
969#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
970
971/* An X form instruction. */
972#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
973
974/* An X form instruction with the RC bit specified. */
975#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
976
977/* The mask for an X form instruction. */
978#define X_MASK XRC (0x3f, 0x3ff, 1)
979
980/* An X_MASK with the RA field fixed. */
981#define XRA_MASK (X_MASK | RA_MASK)
982
983/* An X_MASK with the RB field fixed. */
984#define XRB_MASK (X_MASK | RB_MASK)
985
986/* An X_MASK with the RT field fixed. */
987#define XRT_MASK (X_MASK | RT_MASK)
988
989/* An X_MASK with the RA and RB fields fixed. */
990#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
991
992/* An X_MASK with the RT and RA fields fixed. */
993#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
994
995/* An X form comparison instruction. */
996#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
997
998/* The mask for an X form comparison instruction. */
999#define XCMP_MASK (X_MASK | (1 << 22))
1000
1001/* The mask for an X form comparison instruction with the L field
1002 fixed. */
1003#define XCMPL_MASK (XCMP_MASK | (1 << 21))
1004
1005/* An X form trap instruction with the TO field specified. */
1006#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1007#define XTO_MASK (X_MASK | TO_MASK)
1008
1009/* An XFL form instruction. */
1010#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1011#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1012
1013/* An XL form instruction with the LK field set to 0. */
1014#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1015
1016/* An XL form instruction which uses the LK field. */
1017#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1018
1019/* The mask for an XL form instruction. */
1020#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1021
1022/* An XL form instruction which explicitly sets the BO field. */
1023#define XLO(op, bo, xop, lk) \
1024 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1025#define XLO_MASK (XL_MASK | BO_MASK)
1026
1027/* An XL form instruction which explicitly sets the y bit of the BO
1028 field. */
1029#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1030#define XLYLK_MASK (XL_MASK | Y_MASK)
1031
1032/* An XL form instruction which sets the BO field and the condition
1033 bits of the BI field. */
1034#define XLOCB(op, bo, cb, xop, lk) \
1035 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1036#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1037
1038/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1039#define XLBB_MASK (XL_MASK | BB_MASK)
1040#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1041#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1042
1043/* An XL_MASK with the BO and BB fields fixed. */
1044#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1045
1046/* An XL_MASK with the BO, BI and BB fields fixed. */
1047#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1048
1049/* An XO form instruction. */
1050#define XO(op, xop, oe, rc) \
1051 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1052#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1053
1054/* An XO_MASK with the RB field fixed. */
1055#define XORB_MASK (XO_MASK | RB_MASK)
1056
1057/* An XS form instruction. */
1058#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1059#define XS_MASK XS (0x3f, 0x1ff, 1)
1060
1061/* A mask for the FXM version of an XFX form instruction. */
1062#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1063
1064/* An XFX form instruction with the FXM field filled in. */
1065#define XFXM(op, xop, fxm) \
1066 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1067
1068/* An XFX form instruction with the SPR field filled in. */
1069#define XSPR(op, xop, spr) \
1070 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1071#define XSPR_MASK (X_MASK | SPR_MASK)
1072
1073/* An XFX form instruction with the SPR field filled in except for the
1074 SPRBAT field. */
1075#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1076
1077/* An XFX form instruction with the SPR field filled in except for the
1078 SPRG field. */
1079#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1080
1081/* The BO encodings used in extended conditional branch mnemonics. */
1082#define BODNZF (0x0)
1083#define BODNZFP (0x1)
1084#define BODZF (0x2)
1085#define BODZFP (0x3)
1086#define BOF (0x4)
1087#define BOFP (0x5)
1088#define BODNZT (0x8)
1089#define BODNZTP (0x9)
1090#define BODZT (0xa)
1091#define BODZTP (0xb)
1092#define BOT (0xc)
1093#define BOTP (0xd)
1094#define BODNZ (0x10)
1095#define BODNZP (0x11)
1096#define BODZ (0x12)
1097#define BODZP (0x13)
1098#define BOU (0x14)
1099
1100/* The BI condition bit encodings used in extended conditional branch
1101 mnemonics. */
1102#define CBLT (0)
1103#define CBGT (1)
1104#define CBEQ (2)
1105#define CBSO (3)
1106
1107/* The TO encodings used in extended trap mnemonics. */
1108#define TOLGT (0x1)
1109#define TOLLT (0x2)
1110#define TOEQ (0x4)
1111#define TOLGE (0x5)
1112#define TOLNL (0x5)
1113#define TOLLE (0x6)
1114#define TOLNG (0x6)
1115#define TOGT (0x8)
1116#define TOGE (0xc)
1117#define TONL (0xc)
1118#define TOLT (0x10)
1119#define TOLE (0x14)
1120#define TONG (0x14)
1121#define TONE (0x18)
1122#define TOU (0x1f)
1123
1124/* Smaller names for the flags so each entry in the opcodes table will
1125 fit on a single line. */
1126#undef PPC
1127#define PPC PPC_OPCODE_PPC
1128#define POWER PPC_OPCODE_POWER
1129#define POWER2 PPC_OPCODE_POWER2
1130#define B32 PPC_OPCODE_32
1131#define B64 PPC_OPCODE_64
1132#define M601 PPC_OPCODE_601
1133
1134/* The opcode table.
1135
1136 The format of the opcode table is:
1137
1138 NAME OPCODE MASK FLAGS { OPERANDS }
1139
1140 NAME is the name of the instruction.
1141 OPCODE is the instruction opcode.
1142 MASK is the opcode mask; this is used to tell the disassembler
1143 which bits in the actual opcode must match OPCODE.
1144 FLAGS are flags indicated what processors support the instruction.
1145 OPERANDS is the list of operands.
1146
1147 The disassembler reads the table in order and prints the first
1148 instruction which matches, so this table is sorted to put more
1149 specific instructions before more general instructions. It is also
1150 sorted by major opcode. */
1151
1152const struct powerpc_opcode powerpc_opcodes[] = {
1153{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1154{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1155{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1156{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1157{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1158{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1159{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1160{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1161{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1162{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1163{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1164{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1165{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1166{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1167{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1168
1169{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1170{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1171{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1172{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1173{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1174{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1175{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1176{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1177{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1178{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1179{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1180{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1181{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1182{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1183{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1184{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1185{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1186{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1187{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1188{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1189{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1190{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1191{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1192{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1193{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1194{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1195{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1196{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1197{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1198{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1199
1200{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1201{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1202
1203{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1204{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1205
1206{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1207
1208{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1209{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1210{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1211{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1212
1213{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1214{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1215{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1216{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1217
1218{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1219{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1220{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1221
1222{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1223{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1224{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1225
1226{ "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1227{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1228{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1229{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1230{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1231{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1232
1233{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1234{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1235{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1236{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1237{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1238
1239{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1240{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1241{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1242{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1243{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1244{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1245{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1246{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1247{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1248{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1249{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1250{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1251{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1252{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1253{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1254{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1255{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1256{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1257{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1258{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1259{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1260{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1261{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1262{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1263{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1264{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1265{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1266{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1267{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1268{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1269{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1270{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1271{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1272{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1273{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1274{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1275{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1276{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1277{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1278{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1279{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1280{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1281{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1282{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1283{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1284{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1285{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1286{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1287{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1288{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1289{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1290{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1291{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1292{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1293{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1294{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1295{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1296{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1297{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1298{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1299{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1300{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1301{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1302{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1303{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1304{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1305{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1306{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1307{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1308{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1309{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1310{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1311{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1312{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1313{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1314{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1315{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1316{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1317{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1318{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1319{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1320{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1321{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1322{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1323{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1324{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1325{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1326{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1327{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1328{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1329{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1330{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1331{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1332{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1333{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1334{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1335{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1336{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1337{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1338{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1339{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1340{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1341{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1342{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1343{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1344{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1345{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1346{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1347{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1348{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1349{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1350{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1351{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1352{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1353{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1354{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1355{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1356{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1357{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1358{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1359{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1360{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1361{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1362{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1363{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1364{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1365{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1366{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1367{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1368{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1369{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1370{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1371{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1372{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1373{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1374{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1375{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1376{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1377{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1378{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1379{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1380{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1381{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1382{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1383{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1384{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1385{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1386{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1387{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1388{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1389{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1390{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1391{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1392{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1393{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1394{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1395{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1396{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1397{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1398{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1399{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1400{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1401{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1402{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1403{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1404{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1405{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1406{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1407{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1408{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1409{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1410{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1411{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1412{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1413{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1414{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1415{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1416{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1417{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1418{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1419{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1420{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1421{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1422{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1423{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1424{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1425{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1426{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1427{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1428{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1429{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1430{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1431{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1432{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1433{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1434{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1435{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1436{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1437{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1438{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1439{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1440{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1441{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1442{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1443{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1444{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1445{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1446{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1447{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1448{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1449{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1450{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1451{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1452{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1453{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1454{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1455{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1456{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1457{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1458{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1459{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1460{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1461{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1462{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1463{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1464{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1465{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1466{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1467{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1468{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1469{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1470{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1471{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1472{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1473{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1474{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1475{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1476{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1477{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1478{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1479{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1480{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1481{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1482{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1483{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1484{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1485{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1486{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1487{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1488{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1489{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1490{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1491{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1492{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1493{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1494{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1495{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1496{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1497{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1498{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1499{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1500{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1501{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1502{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1503
1504{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1505{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1506{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1507{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1508{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1509
1510{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1511{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1512{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1513{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1514
1515{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1516
1517{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1518{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1519{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1520{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1521{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1522{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1523{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1524{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1525{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1526{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1527{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1528{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1529{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1530{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1531{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1532{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1533{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1534{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1535{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1536{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1537{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1538{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1539{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1540{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1541{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1542{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1543{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1544{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1545{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1546{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1547{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1548{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1549{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1550{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1551{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1552{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1553{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1554{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1555{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1556{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1557{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1558{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1559{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1560{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1561{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1562{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1563{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1564{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1565{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1566{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1567{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1568{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1569{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1570{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1571{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1572{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1573{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1574{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1575{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1576{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1577{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1578{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1579{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1580{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1581{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1582{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1583{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1584{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1585{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1586{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1587{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1588{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1589{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1590{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1591{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1592{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1593{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1594{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1595{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1596{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1597{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1598{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1599{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1600{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1601{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1602{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1603{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1604{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1605{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1606{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1607{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1608{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1609{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1610{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1611{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1612{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1613{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1614{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1615{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1616{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1617{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1618{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1619{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1620{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1621{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1622{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1623{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1624{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1625{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1626{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1627{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1628{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1629{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1630{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1631{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1632{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1633{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1634{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1635{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1636{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1637{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1638{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1639{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1640{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1641{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1642{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1643{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1644{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1645{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1646{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1647{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1648{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1649{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1650{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1651{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1652{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1653{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1654{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1655{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1656{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1657{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1658{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1659{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1660{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1661{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1662{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1663{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1664{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1665{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1666{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1667{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1668{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1669{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1670{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1671{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1672{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1673
1674{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1675{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1676
1677{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1678{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
1679
1680{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1681
1682{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1683
1684{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1685{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1686
1687{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1688{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1689
1690{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1691
1692{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1693
1694{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1695{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1696
1697{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1698
1699{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1700{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1701
1702{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1703{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1704{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1705{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1706{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1707{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1708{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1709{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1710{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1711{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1712{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1713{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1714{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1715{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1716{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1717{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1718{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1719{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1720{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1721{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1722{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1723{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1724{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1725{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1726{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1727{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1728{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1729{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1730{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1731{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1732{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1733{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1734{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1735{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1736{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1737{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1738{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1739{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1740{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1741{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1742{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1743{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1744{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1745{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1746{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1747{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1748{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1749{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1750{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1751{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1752{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1753{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1754{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1755{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1756{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1757{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1758{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1759{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1760{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1761{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1762{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1763{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1764{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1765{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1766{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1767{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1768{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1769{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1770{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1771{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1772{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1773{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1774{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1775{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1776{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1777{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1778{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1779{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1780{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1781{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1782{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1783{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1784{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1785{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1786{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1787{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1788{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1789{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1790{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1791{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1792{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1793{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1794{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1795{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1796
1797{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1798{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1799
1800{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1801{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1802
1803{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1804{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1805{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1806{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1807{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1808{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1809{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1810{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1811
1812{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1813{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1814
1815{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1816{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1817{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1818{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1819{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1820{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1821
1822{ "nop", OP(24), 0xffffffff, PPC, { 0 } },
1823{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1824{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1825
1826{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1827{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1828
1829{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1830{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1831
1832{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1833{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1834
1835{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1836{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1837
1838{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1839{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1840
1841{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1842{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1843{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1844{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1845{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1846{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1847
1848{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1849{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1850
1851{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1852{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1853
1854{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1855{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1856
1857{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1858{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1859{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1860{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1861
1862{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1863{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1864
1865{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1866{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1867{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
1868{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
1869
1870{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1871{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1872{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1873{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1874{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1875{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1876{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1877{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1878{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1879{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1880{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
1881{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
1882{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
1883{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
1884{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
1885{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
1886{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
1887{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
1888{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
1889{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
1890{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
1891{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
1892{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
1893{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
1894{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
1895{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
1896{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
1897{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
1898{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
1899{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
1900{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
1901
1902{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
1903{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
1904{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
1905{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
1906{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
1907{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
1908{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
1909{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
1910{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
1911{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
1912{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
1913{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
1914
1915{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1916{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1917
1918{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
1919{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
1920{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
1921{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
1922{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
1923{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
1924{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
1925{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
1926
1927{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
1928{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
1929
1930{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
1931
1932{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
1933
1934{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
1935
1936{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
1937{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
1938
1939{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
1940{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
1941{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
1942{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
1943
1944{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
1945{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
1946{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
1947{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
1948
1949{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
1950{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
1951
1952{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1953{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1954
1955{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
1956{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
1957
1958{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1959{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1960{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
1961{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
1962
1963{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
1964{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
1965{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
1966{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
1967{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
1968{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
1969{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
1970{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
1971
1972{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
1973
1974{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
1975
1976{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
1977{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
1978
1979{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
1980{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
1981
1982{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1983{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1984
1985{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
1986{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
1987{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
1988{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
1989{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
1990{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
1991{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
1992{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
1993{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
1994{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
1995{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
1996{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
1997{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
1998{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
1999{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2000
2001{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2002{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2003
2004{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2005{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2006
2007{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2008
2009{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2010
2011{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2012
2013{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2014
2015{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2016{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2017{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2018{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2019
2020{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2021{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2022{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2023{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2024
2025{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2026
2027{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2028
2029{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2030{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2031{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2032{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2033
2034{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2035{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2036{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2037{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2038{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2039{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2040{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2041{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2042
2043{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2044{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2045{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2046{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2047{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2048{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2049{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2050{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2051
2052{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2053{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
2054
2055{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2056
2057{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2058
2059{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2060
2061{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2062{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2063
2064{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2065{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2066
2067{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2068{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2069
2070{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2071
2072{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2073{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2074
2075{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2076{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2077
2078{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2079{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2080{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2081{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2082{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2083{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2084{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2085{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2086
2087{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2088{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2089{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2090{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2091{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2092{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2093{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2094{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2095
2096{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2097
2098{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2099
2100{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2101
2102{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2103{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2104
2105{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2106{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2107
2108{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2109{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2110{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2111{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2112{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2113{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2114{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2115{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2116
2117{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2118{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2119{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2120{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2121
2122{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2123{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2124{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2125{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2126{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2127{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2128{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2129{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2130
2131{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2132{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2133{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2134{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2135{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2136{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2137{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2138{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2139
2140{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2141{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2142
2143{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2144
2145{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2146
2147{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2148{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2149
2150{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2151{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2152{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2153{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2154
2155{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2156{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2157{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2158{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2159{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2160{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2161{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2162{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2163
2164{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2165{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2166
2167{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2168
2169{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2170
2171{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2172
2173{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2174{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2175
2176{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2177{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2178
2179{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2180
2181{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2182
2183{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2184{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2185
2186{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2187
2188{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2189{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2190{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2191{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2192
2193{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
2194{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2195{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2196{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2197{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
2198{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2199{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2200{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2201{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2202{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2203{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2204{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2205{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2206{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2207{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2208{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2209{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2210{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2211{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2212{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2213{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2214{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2215{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2216{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2217
2218{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2219
2220{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2221
2222{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2223
2224{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2225{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2226{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2227{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2228
2229{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2230{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2231{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2232{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2233
2234{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2235
2236{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2237{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2238
2239{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2240
2241{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2242
2243{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2244
2245{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2246
2247{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2248
2249{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2250
2251{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2252
2253{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2254{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2255
2256{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2257{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2258
2259{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2260
2261{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2262
2263{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2264
2265{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2266{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2267{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2268{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2269
2270{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2271
2272{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2273{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2274{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2275{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2276
2277{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2278{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2279{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2280{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2281
2282{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
2283{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2284{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2285{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2286{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2287{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2288{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2289{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2290{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2291{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2292{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2293{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2294{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2295{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2296{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2297{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2298{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2299{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2300{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2301{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2302{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2303{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2304{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2305{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2306
2307{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2308
2309{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2310{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2311
2312{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2313{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2314{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2315{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2316
2317{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2318{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2319{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2320{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2321
2322{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2323{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2324{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2325{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2326
2327{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2328
2329{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2330
2331{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2332
2333{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
2334
2335{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2336{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2337
2338{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2339{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2340
2341{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2342
2343{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2344{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2345{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2346{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2347
2348{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2349{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2350
2351{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2352{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2353
2354{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2355{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2356
2357{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2358
2359{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2360
2361{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2362
2363{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2364{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2365
2366{ "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2367{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2368
2369{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2370
2371{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2372
2373{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2374
2375{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2376
2377{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2378
2379{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2380{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2381
2382{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2383{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2384
2385{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2386
2387{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2388{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2389
2390{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2391{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2392
2393{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2394
2395{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2396{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2397
2398{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2399{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2400
2401{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2402
2403{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2404{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2405
2406{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2407{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2408
2409{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2410
2411{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2412{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2413
2414{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2415
2416{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2417{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2418{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2419{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2420
2421{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2422{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2423
2424{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2425
2426{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2427{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2428{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2429{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2430
2431{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2432
2433{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2434
2435{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2436{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2437
2438{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2439{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2440
2441{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2442{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2443{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2444{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2445
2446{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2447{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2448
2449{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2450{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2451
2452{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2453
2454{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2455
2456{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2457
2458{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2459{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2460
2461{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2462{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2463
2464{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2465{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2466
2467{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
2468{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2469
2470{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2471
2472{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
2473
2474{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2475{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2476
2477{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
2478{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2479
2480{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2481
2482{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
2483
2484{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2485
2486{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
2487
2488{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2489
2490{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
2491
2492{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2493
2494{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
2495
2496{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
2497{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2498
2499{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2500{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2501
2502{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2503
2504{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2505
2506{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2507
2508{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2509
2510{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2511
2512{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2513
2514{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2515
2516{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2517
2518{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2519
2520{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2521
2522{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2523
2524{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
2525
2526{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2527
2528{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2529{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2530
2531{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2532{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2533
2534{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2535{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2536
2537{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2538{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2539
2540{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2541{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2542
2543{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2544{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2545
2546{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2547{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2548
2549{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2550{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2551
2552{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2553{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2554
2555{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2556{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2557
2558{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2559
2560{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2561
2562{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2563
2564{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
2565
2566{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2567
2568{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2569{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2570
2571{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2572{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2573{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2574{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2575
2576{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2577{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2578{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2579{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2580
2581{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2582{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2583{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2584{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2585
2586{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2587{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2588{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2589{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2590
2591{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2592{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2593{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2594{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2595
2596{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2597{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2598
2599{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2600{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2601
2602{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2603{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2604{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2605{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2606
2607{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2608{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2609
2610{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2611{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2612{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2613{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2614
2615{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2616{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2617{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2618{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2619
2620{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2621{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2622{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2623{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2624
2625{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2626{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2627{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2628{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2629
2630{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2631
2632{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2633{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2634
2635{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2636{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2637
2638{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2639
2640{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2641{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2642
2643{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2644{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2645
2646{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2647{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2648
2649{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2650{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2651
2652{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2653{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2654
2655{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
2656{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
2657
2658{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
2659{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
2660
2661{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2662{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2663
2664{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2665{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2666
2667{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2668{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2669
2670};
2671
2672const int powerpc_num_opcodes =
2673 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
2674
2675/* The macro table. This is only used by the assembler. */
2676
2677const struct powerpc_macro powerpc_macros[] = {
2678{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
2679{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
2680{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2681{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2682{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2683{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2684{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
2685{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
2686{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
2687{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
2688{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
2689{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
2690{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
2691{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
2692{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
2693{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
2694
2695{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
2696{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
2697{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2698{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2699{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2700{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2701{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2702{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2703{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
2704{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
2705{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
2706{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
2707{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
2708{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
2709{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
2710{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
2711{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
2712{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
2713{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
2714{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
2715{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2716{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2717
2718};
2719
2720const int powerpc_num_macros =
2721 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:06:19 -0500