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-rw-r--r--arch/ppc/syslib/Makefile3
-rw-r--r--arch/ppc/syslib/cpc710.h81
-rw-r--r--arch/ppc/syslib/m8xx_setup.c2
-rw-r--r--arch/ppc/syslib/ppc4xx_sgdma.c1
-rw-r--r--arch/ppc/syslib/virtex_devices.c233
-rw-r--r--arch/ppc/syslib/virtex_devices.h27
6 files changed, 264 insertions, 83 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 09911118c675..95694159b226 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -18,7 +18,8 @@ obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
18obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o 18obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
19ifeq ($(CONFIG_4xx),y) 19ifeq ($(CONFIG_4xx),y)
20ifeq ($(CONFIG_XILINX_VIRTEX),y) 20ifeq ($(CONFIG_XILINX_VIRTEX),y)
21obj-$(CONFIG_40x) += xilinx_pic.o ppc_sys.o 21obj-$(CONFIG_40x) += xilinx_pic.o
22obj-y += virtex_devices.o
22else 23else
23ifeq ($(CONFIG_403),y) 24ifeq ($(CONFIG_403),y)
24obj-$(CONFIG_40x) += ppc403_pic.o 25obj-$(CONFIG_40x) += ppc403_pic.o
diff --git a/arch/ppc/syslib/cpc710.h b/arch/ppc/syslib/cpc710.h
deleted file mode 100644
index 5299bf8b5d01..000000000000
--- a/arch/ppc/syslib/cpc710.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Definitions for the IBM CPC710 PCI Host Bridge
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __PPC_PLATFORMS_CPC710_H
13#define __PPC_PLATFORMS_CPC710_H
14
15/* General bridge and memory controller registers */
16#define PIDR 0xff000008
17#define CNFR 0xff00000c
18#define RSTR 0xff000010
19#define UCTL 0xff001000
20#define MPSR 0xff001010
21#define SIOC 0xff001020
22#define ABCNTL 0xff001030
23#define SRST 0xff001040
24#define ERRC 0xff001050
25#define SESR 0xff001060
26#define SEAR 0xff001070
27#define SIOC1 0xff001090
28#define PGCHP 0xff001100
29#define GPDIR 0xff001130
30#define GPOUT 0xff001150
31#define ATAS 0xff001160
32#define AVDG 0xff001170
33#define MCCR 0xff001200
34#define MESR 0xff001220
35#define MEAR 0xff001230
36#define MCER0 0xff001300
37#define MCER1 0xff001310
38#define MCER2 0xff001320
39#define MCER3 0xff001330
40#define MCER4 0xff001340
41#define MCER5 0xff001350
42#define MCER6 0xff001360
43#define MCER7 0xff001370
44
45/*
46 * PCI32/64 configuration registers
47 * Given as offsets from their
48 * respective physical segment BAR
49 */
50#define PIBAR 0x000f7800
51#define PMBAR 0x000f7810
52#define MSIZE 0x000f7f40
53#define IOSIZE 0x000f7f60
54#define SMBAR 0x000f7f80
55#define SIBAR 0x000f7fc0
56#define PSSIZE 0x000f8100
57#define PPSIZE 0x000f8110
58#define BARPS 0x000f8120
59#define BARPP 0x000f8130
60#define PSBAR 0x000f8140
61#define PPBAR 0x000f8150
62#define BPMDLK 0x000f8200 /* Bottom of Peripheral Memory Space */
63#define TPMDLK 0x000f8210 /* Top of Peripheral Memory Space */
64#define BIODLK 0x000f8220 /* Bottom of Peripheral I/O Space */
65#define TIODLK 0x000f8230 /* Top of Perioheral I/O Space */
66#define DLKCTRL 0x000f8240 /* Deadlock control */
67#define DLKDEV 0x000f8250 /* Deadlock device */
68
69/* System standard configuration registers space */
70#define DCR 0xff200000
71#define DID 0xff200004
72#define BAR 0xff200018
73
74/* Device specific configuration space */
75#define PCIENB 0xff201000
76
77/* Configuration space registers */
78#define CPC710_BUS_NUMBER 0x40
79#define CPC710_SUB_BUS_NUMBER 0x41
80
81#endif /* __PPC_PLATFORMS_CPC710_H */
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 01e48d88f22d..9caf850c9b38 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -413,7 +413,7 @@ m8xx_map_io(void)
413 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO); 413 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
414#endif 414#endif
415#endif 415#endif
416#if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX) 416#if defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
417 io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO); 417 io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
418#endif 418#endif
419#ifdef CONFIG_FADS 419#ifdef CONFIG_FADS
diff --git a/arch/ppc/syslib/ppc4xx_sgdma.c b/arch/ppc/syslib/ppc4xx_sgdma.c
index 2f83e162971f..939abe3c1f45 100644
--- a/arch/ppc/syslib/ppc4xx_sgdma.c
+++ b/arch/ppc/syslib/ppc4xx_sgdma.c
@@ -27,6 +27,7 @@
27 27
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/io.h> 29#include <asm/io.h>
30#include <asm/dma-mapping.h>
30#include <asm/ppc4xx_dma.h> 31#include <asm/ppc4xx_dma.h>
31 32
32void 33void
diff --git a/arch/ppc/syslib/virtex_devices.c b/arch/ppc/syslib/virtex_devices.c
new file mode 100644
index 000000000000..16546788e23b
--- /dev/null
+++ b/arch/ppc/syslib/virtex_devices.c
@@ -0,0 +1,233 @@
1/*
2 * Virtex hard ppc405 core common device listing
3 *
4 * Copyright 2005-2007 Secret Lab Technologies Ltd.
5 * Copyright 2005 Freescale Semiconductor Inc.
6 * Copyright 2002-2004 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <syslib/virtex_devices.h>
19#include <platforms/4xx/xparameters/xparameters.h>
20#include <asm/io.h>
21
22/*
23 * UARTLITE: shortcut macro for single instance
24 */
25#define XPAR_UARTLITE(num) { \
26 .name = "uartlite", \
27 .id = num, \
28 .num_resources = 2, \
29 .resource = (struct resource[]) { \
30 { \
31 .start = XPAR_UARTLITE_##num##_BASEADDR + 3, \
32 .end = XPAR_UARTLITE_##num##_HIGHADDR, \
33 .flags = IORESOURCE_MEM, \
34 }, \
35 { \
36 .start = XPAR_INTC_0_UARTLITE_##num##_VEC_ID, \
37 .flags = IORESOURCE_IRQ, \
38 }, \
39 }, \
40}
41
42/*
43 * Full UART: shortcut macro for single instance + platform data structure
44 */
45#define XPAR_UART(num) { \
46 .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \
47 .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
48 .iotype = UPIO_MEM, \
49 .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \
50 .flags = UPF_BOOT_AUTOCONF, \
51 .regshift = 2, \
52}
53
54/*
55 * SystemACE: shortcut macro for single instance
56 */
57#define XPAR_SYSACE(num) { \
58 .name = "xsysace", \
59 .id = XPAR_SYSACE_##num##_DEVICE_ID, \
60 .num_resources = 2, \
61 .resource = (struct resource[]) { \
62 { \
63 .start = XPAR_SYSACE_##num##_BASEADDR, \
64 .end = XPAR_SYSACE_##num##_HIGHADDR, \
65 .flags = IORESOURCE_MEM, \
66 }, \
67 { \
68 .start = XPAR_INTC_0_SYSACE_##num##_VEC_ID, \
69 .flags = IORESOURCE_IRQ, \
70 }, \
71 }, \
72}
73
74
75/* UART 8250 driver platform data table */
76struct plat_serial8250_port virtex_serial_platform_data[] = {
77#if defined(XPAR_UARTNS550_0_BASEADDR)
78 XPAR_UART(0),
79#endif
80#if defined(XPAR_UARTNS550_1_BASEADDR)
81 XPAR_UART(1),
82#endif
83#if defined(XPAR_UARTNS550_2_BASEADDR)
84 XPAR_UART(2),
85#endif
86#if defined(XPAR_UARTNS550_3_BASEADDR)
87 XPAR_UART(3),
88#endif
89#if defined(XPAR_UARTNS550_4_BASEADDR)
90 XPAR_UART(4),
91#endif
92#if defined(XPAR_UARTNS550_5_BASEADDR)
93 XPAR_UART(5),
94#endif
95#if defined(XPAR_UARTNS550_6_BASEADDR)
96 XPAR_UART(6),
97#endif
98#if defined(XPAR_UARTNS550_7_BASEADDR)
99 XPAR_UART(7),
100#endif
101 { }, /* terminated by empty record */
102};
103
104
105struct platform_device virtex_platform_devices[] = {
106 /* UARTLITE instances */
107#if defined(XPAR_UARTLITE_0_BASEADDR)
108 XPAR_UARTLITE(0),
109#endif
110#if defined(XPAR_UARTLITE_1_BASEADDR)
111 XPAR_UARTLITE(1),
112#endif
113#if defined(XPAR_UARTLITE_2_BASEADDR)
114 XPAR_UARTLITE(2),
115#endif
116#if defined(XPAR_UARTLITE_3_BASEADDR)
117 XPAR_UARTLITE(3),
118#endif
119#if defined(XPAR_UARTLITE_4_BASEADDR)
120 XPAR_UARTLITE(4),
121#endif
122#if defined(XPAR_UARTLITE_5_BASEADDR)
123 XPAR_UARTLITE(5),
124#endif
125#if defined(XPAR_UARTLITE_6_BASEADDR)
126 XPAR_UARTLITE(6),
127#endif
128#if defined(XPAR_UARTLITE_7_BASEADDR)
129 XPAR_UARTLITE(7),
130#endif
131
132 /* Full UART instances */
133#if defined(XPAR_UARTNS550_0_BASEADDR)
134 {
135 .name = "serial8250",
136 .id = 0,
137 .dev.platform_data = virtex_serial_platform_data,
138 },
139#endif
140
141 /* SystemACE instances */
142#if defined(XPAR_SYSACE_0_BASEADDR)
143 XPAR_SYSACE(0),
144#endif
145#if defined(XPAR_SYSACE_1_BASEADDR)
146 XPAR_SYSACE(1),
147#endif
148
149 /* ML300/403 reference design framebuffer */
150#if defined(XPAR_TFT_0_BASEADDR)
151 {
152 .name = "xilinxfb",
153 .id = 0,
154 .num_resources = 1,
155 .resource = (struct resource[]) {
156 {
157 .start = XPAR_TFT_0_BASEADDR,
158 .end = XPAR_TFT_0_BASEADDR+7,
159 .flags = IORESOURCE_IO,
160 },
161 },
162 },
163#endif
164};
165
166/* Early serial support functions */
167static void __init
168virtex_early_serial_init(int num, struct plat_serial8250_port *pdata)
169{
170#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
171 struct uart_port serial_req;
172
173 memset(&serial_req, 0, sizeof(serial_req));
174 serial_req.mapbase = pdata->mapbase;
175 serial_req.membase = pdata->membase;
176 serial_req.irq = pdata->irq;
177 serial_req.uartclk = pdata->uartclk;
178 serial_req.regshift = pdata->regshift;
179 serial_req.iotype = pdata->iotype;
180 serial_req.flags = pdata->flags;
181 gen550_init(num, &serial_req);
182#endif
183}
184
185void __init
186virtex_early_serial_map(void)
187{
188#ifdef CONFIG_SERIAL_8250
189 struct plat_serial8250_port *pdata;
190 int i = 0;
191
192 pdata = virtex_serial_platform_data;
193 while(pdata && pdata->flags) {
194 pdata->membase = ioremap(pdata->mapbase, 0x100);
195 virtex_early_serial_init(i, pdata);
196 pdata++;
197 i++;
198 }
199#endif /* CONFIG_SERIAL_8250 */
200}
201
202/*
203 * default fixup routine; do nothing and return success.
204 *
205 * Reimplement this routine in your custom board support file to
206 * override the default behaviour
207 */
208int __attribute__ ((weak))
209virtex_device_fixup(struct platform_device *dev)
210{
211 return 0;
212}
213
214static int __init virtex_init(void)
215{
216 struct platform_device *index = virtex_platform_devices;
217 unsigned int ret = 0;
218 int i;
219
220 for (i = 0; i < ARRAY_SIZE(virtex_platform_devices); i++, index++) {
221 if (virtex_device_fixup(index) != 0)
222 continue;
223
224 if (platform_device_register(index)) {
225 ret = 1;
226 printk(KERN_ERR "cannot register dev %s:%d\n",
227 index->name, index->id);
228 }
229 }
230 return ret;
231}
232
233subsys_initcall(virtex_init);
diff --git a/arch/ppc/syslib/virtex_devices.h b/arch/ppc/syslib/virtex_devices.h
new file mode 100644
index 000000000000..4a17dd3927c1
--- /dev/null
+++ b/arch/ppc/syslib/virtex_devices.h
@@ -0,0 +1,27 @@
1/*
2 * Common support header for virtex ppc405 platforms
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#ifndef __ASM_VIRTEX_DEVICES_H__
12#define __ASM_VIRTEX_DEVICES_H__
13
14#include <linux/platform_device.h>
15
16void __init virtex_early_serial_map(void);
17
18/* Prototype for device fixup routine. Implement this routine in the
19 * board specific fixup code and the generic setup code will call it for
20 * each device is the platform device list.
21 *
22 * If the hook returns a non-zero value, then the device will not get
23 * registered with the platform bus
24 */
25int virtex_device_fixup(struct platform_device *dev);
26
27#endif /* __ASM_VIRTEX_DEVICES_H__ */
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