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-rw-r--r--arch/ppc/syslib/Makefile3
-rw-r--r--arch/ppc/syslib/cpm2_common.c2
-rw-r--r--arch/ppc/syslib/indirect_pci.c1
-rw-r--r--arch/ppc/syslib/ipic.c14
-rw-r--r--arch/ppc/syslib/mpc10x_common.c203
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c187
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c105
-rw-r--r--arch/ppc/syslib/mv64x60.c1
-rw-r--r--arch/ppc/syslib/mv64x60_win.c1
-rw-r--r--arch/ppc/syslib/ocp.c2
-rw-r--r--arch/ppc/syslib/of_device.c2
-rw-r--r--arch/ppc/syslib/open_pic.c27
-rw-r--r--arch/ppc/syslib/open_pic2.c1
-rw-r--r--arch/ppc/syslib/ppc4xx_kgdb.c124
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c1
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c9
16 files changed, 484 insertions, 199 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 96acf85800d4..dec5bf4f6879 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -92,7 +92,7 @@ ifeq ($(CONFIG_SERIAL_MPSC_CONSOLE),y)
92obj-$(CONFIG_SERIAL_TEXT_DEBUG) += mv64x60_dbg.o 92obj-$(CONFIG_SERIAL_TEXT_DEBUG) += mv64x60_dbg.o
93endif 93endif
94obj-$(CONFIG_BOOTX_TEXT) += btext.o 94obj-$(CONFIG_BOOTX_TEXT) += btext.o
95obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o 95obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o ppc_sys.o
96obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o 96obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o
97obj-$(CONFIG_40x) += dcr.o 97obj-$(CONFIG_40x) += dcr.o
98obj-$(CONFIG_BOOKE) += dcr.o 98obj-$(CONFIG_BOOKE) += dcr.o
@@ -107,6 +107,7 @@ obj-$(CONFIG_83xx) += ipic.o ppc83xx_setup.o ppc_sys.o \
107ifeq ($(CONFIG_83xx),y) 107ifeq ($(CONFIG_83xx),y)
108obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o 108obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
109endif 109endif
110obj-$(CONFIG_MPC8548_CDS) += todc_time.o
110obj-$(CONFIG_MPC8555_CDS) += todc_time.o 111obj-$(CONFIG_MPC8555_CDS) += todc_time.o
111obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ 112obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
112 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o 113 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o
diff --git a/arch/ppc/syslib/cpm2_common.c b/arch/ppc/syslib/cpm2_common.c
index ea5e77080e8d..4c19a4ac7163 100644
--- a/arch/ppc/syslib/cpm2_common.c
+++ b/arch/ppc/syslib/cpm2_common.c
@@ -21,8 +21,8 @@
21#include <linux/string.h> 21#include <linux/string.h>
22#include <linux/mm.h> 22#include <linux/mm.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/bootmem.h>
25#include <linux/module.h> 24#include <linux/module.h>
25#include <asm/io.h>
26#include <asm/irq.h> 26#include <asm/irq.h>
27#include <asm/mpc8260.h> 27#include <asm/mpc8260.h>
28#include <asm/page.h> 28#include <asm/page.h>
diff --git a/arch/ppc/syslib/indirect_pci.c b/arch/ppc/syslib/indirect_pci.c
index a5a752609e2c..e71488469704 100644
--- a/arch/ppc/syslib/indirect_pci.c
+++ b/arch/ppc/syslib/indirect_pci.c
@@ -14,7 +14,6 @@
14#include <linux/delay.h> 14#include <linux/delay.h>
15#include <linux/string.h> 15#include <linux/string.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/bootmem.h>
18 17
19#include <asm/io.h> 18#include <asm/io.h>
20#include <asm/prom.h> 19#include <asm/prom.h>
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
index 580ed658e872..8f01e0f1d847 100644
--- a/arch/ppc/syslib/ipic.c
+++ b/arch/ppc/syslib/ipic.c
@@ -79,7 +79,7 @@ static struct ipic_info ipic_info[] = {
79 .prio_mask = 7, 79 .prio_mask = 7,
80 }, 80 },
81 [17] = { 81 [17] = {
82 .pend = IPIC_SIPNR_H, 82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR, 83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A, 84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR, 85 .force = IPIC_SEFCR,
@@ -87,7 +87,7 @@ static struct ipic_info ipic_info[] = {
87 .prio_mask = 5, 87 .prio_mask = 5,
88 }, 88 },
89 [18] = { 89 [18] = {
90 .pend = IPIC_SIPNR_H, 90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR, 91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A, 92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR, 93 .force = IPIC_SEFCR,
@@ -95,7 +95,7 @@ static struct ipic_info ipic_info[] = {
95 .prio_mask = 6, 95 .prio_mask = 6,
96 }, 96 },
97 [19] = { 97 [19] = {
98 .pend = IPIC_SIPNR_H, 98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR, 99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A, 100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR, 101 .force = IPIC_SEFCR,
@@ -103,7 +103,7 @@ static struct ipic_info ipic_info[] = {
103 .prio_mask = 7, 103 .prio_mask = 7,
104 }, 104 },
105 [20] = { 105 [20] = {
106 .pend = IPIC_SIPNR_H, 106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR, 107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B, 108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR, 109 .force = IPIC_SEFCR,
@@ -111,7 +111,7 @@ static struct ipic_info ipic_info[] = {
111 .prio_mask = 4, 111 .prio_mask = 4,
112 }, 112 },
113 [21] = { 113 [21] = {
114 .pend = IPIC_SIPNR_H, 114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR, 115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B, 116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR, 117 .force = IPIC_SEFCR,
@@ -119,7 +119,7 @@ static struct ipic_info ipic_info[] = {
119 .prio_mask = 5, 119 .prio_mask = 5,
120 }, 120 },
121 [22] = { 121 [22] = {
122 .pend = IPIC_SIPNR_H, 122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR, 123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B, 124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR, 125 .force = IPIC_SEFCR,
@@ -127,7 +127,7 @@ static struct ipic_info ipic_info[] = {
127 .prio_mask = 6, 127 .prio_mask = 6,
128 }, 128 },
129 [23] = { 129 [23] = {
130 .pend = IPIC_SIPNR_H, 130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR, 131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B, 132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR, 133 .force = IPIC_SEFCR,
diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c
index fd93adfd464c..8fc5f4154521 100644
--- a/arch/ppc/syslib/mpc10x_common.c
+++ b/arch/ppc/syslib/mpc10x_common.c
@@ -21,6 +21,9 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/pci.h> 22#include <linux/pci.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/serial_8250.h>
25#include <linux/fsl_devices.h>
26#include <linux/device.h>
24 27
25#include <asm/byteorder.h> 28#include <asm/byteorder.h>
26#include <asm/io.h> 29#include <asm/io.h>
@@ -30,16 +33,7 @@
30#include <asm/pci-bridge.h> 33#include <asm/pci-bridge.h>
31#include <asm/open_pic.h> 34#include <asm/open_pic.h>
32#include <asm/mpc10x.h> 35#include <asm/mpc10x.h>
33#include <asm/ocp.h> 36#include <asm/ppc_sys.h>
34
35/* The OCP structure is fixed by code below, before OCP initialises.
36 paddr depends on where the board places the EUMB.
37 - fixed in mpc10x_bridge_init().
38 irq depends on two things:
39 > does the board use the EPIC at all? (PCORE does not).
40 > is the EPIC in serial or parallel mode?
41 - fixed in mpc10x_set_openpic().
42*/
43 37
44#ifdef CONFIG_MPC10X_OPENPIC 38#ifdef CONFIG_MPC10X_OPENPIC
45#ifdef CONFIG_EPIC_SERIAL_MODE 39#ifdef CONFIG_EPIC_SERIAL_MODE
@@ -50,35 +44,140 @@
50#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS) 44#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
51#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS) 45#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
52#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS) 46#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
47#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
53#else 48#else
54#define MPC10X_I2C_IRQ OCP_IRQ_NA 49#define MPC10X_I2C_IRQ -1
55#define MPC10X_DMA0_IRQ OCP_IRQ_NA 50#define MPC10X_DMA0_IRQ -1
56#define MPC10X_DMA1_IRQ OCP_IRQ_NA 51#define MPC10X_DMA1_IRQ -1
52#define MPC10X_UART0_IRQ -1
57#endif 53#endif
58 54
59 55static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
60struct ocp_def core_ocp[] = { 56 .device_flags = 0,
61 { .vendor = OCP_VENDOR_INVALID
62 }
63}; 57};
64 58
65static struct ocp_fs_i2c_data mpc10x_i2c_data = { 59static struct plat_serial8250_port serial_platform_data[] = {
66 .flags = 0 60 [0] = {
61 .mapbase = 0x4500,
62 .iotype = UPIO_MEM,
63 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
64 },
65 [1] = {
66 .mapbase = 0x4600,
67 .iotype = UPIO_MEM,
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
69 },
70 { },
67}; 71};
68static struct ocp_def mpc10x_i2c_ocp = { 72
69 .vendor = OCP_VENDOR_MOTOROLA, 73struct platform_device ppc_sys_platform_devices[] = {
70 .function = OCP_FUNC_IIC, 74 [MPC10X_IIC1] = {
71 .index = 0, 75 .name = "fsl-i2c",
72 .additions = &mpc10x_i2c_data 76 .id = 1,
77 .dev.platform_data = &mpc10x_i2c_pdata,
78 .num_resources = 2,
79 .resource = (struct resource[]) {
80 {
81 .start = MPC10X_EUMB_I2C_OFFSET,
82 .end = MPC10X_EUMB_I2C_OFFSET +
83 MPC10X_EUMB_I2C_SIZE - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .flags = IORESOURCE_IRQ
88 },
89 },
90 },
91 [MPC10X_DMA0] = {
92 .name = "fsl-dma",
93 .id = 0,
94 .num_resources = 2,
95 .resource = (struct resource[]) {
96 {
97 .start = MPC10X_EUMB_DMA_OFFSET + 0x10,
98 .end = MPC10X_EUMB_DMA_OFFSET + 0x1f,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .flags = IORESOURCE_IRQ,
103 },
104 },
105 },
106 [MPC10X_DMA1] = {
107 .name = "fsl-dma",
108 .id = 1,
109 .num_resources = 2,
110 .resource = (struct resource[]) {
111 {
112 .start = MPC10X_EUMB_DMA_OFFSET + 0x20,
113 .end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .flags = IORESOURCE_IRQ,
118 },
119 },
120 },
121 [MPC10X_DMA1] = {
122 .name = "fsl-dma",
123 .id = 1,
124 .num_resources = 2,
125 .resource = (struct resource[]) {
126 {
127 .start = MPC10X_EUMB_DMA_OFFSET + 0x20,
128 .end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .flags = IORESOURCE_IRQ,
133 },
134 },
135 },
136 [MPC10X_DUART] = {
137 .name = "serial8250",
138 .id = 0,
139 .dev.platform_data = serial_platform_data,
140 },
73}; 141};
74 142
75static struct ocp_def mpc10x_dma_ocp[2] = { 143/* We use the PCI ID to match on */
76{ .vendor = OCP_VENDOR_MOTOROLA, 144struct ppc_sys_spec *cur_ppc_sys_spec;
77 .function = OCP_FUNC_DMA, 145struct ppc_sys_spec ppc_sys_specs[] = {
78 .index = 0 }, 146 {
79{ .vendor = OCP_VENDOR_MOTOROLA, 147 .ppc_sys_name = "8245",
80 .function = OCP_FUNC_DMA, 148 .mask = 0xFFFFFFFF,
81 .index = 1 } 149 .value = MPC10X_BRIDGE_8245,
150 .num_devices = 4,
151 .device_list = (enum ppc_sys_devices[])
152 {
153 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
154 },
155 },
156 {
157 .ppc_sys_name = "8240",
158 .mask = 0xFFFFFFFF,
159 .value = MPC10X_BRIDGE_8240,
160 .num_devices = 3,
161 .device_list = (enum ppc_sys_devices[])
162 {
163 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
164 },
165 },
166 {
167 .ppc_sys_name = "107",
168 .mask = 0xFFFFFFFF,
169 .value = MPC10X_BRIDGE_107,
170 .num_devices = 3,
171 .device_list = (enum ppc_sys_devices[])
172 {
173 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
174 },
175 },
176 { /* default match */
177 .ppc_sys_name = "",
178 .mask = 0x00000000,
179 .value = 0x00000000,
180 },
82}; 181};
83 182
84/* Set resources to match bridge memory map */ 183/* Set resources to match bridge memory map */
@@ -132,7 +231,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
132 uint new_map, 231 uint new_map,
133 uint phys_eumb_base) 232 uint phys_eumb_base)
134{ 233{
135 int host_bridge, picr1, picr1_bit; 234 int host_bridge, picr1, picr1_bit, i;
136 ulong pci_config_addr, pci_config_data; 235 ulong pci_config_addr, pci_config_data;
137 u_char pir, byte; 236 u_char pir, byte;
138 237
@@ -273,7 +372,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
273 printk("Host bridge in Agent mode\n"); 372 printk("Host bridge in Agent mode\n");
274 /* Read or Set LMBAR & PCSRBAR? */ 373 /* Read or Set LMBAR & PCSRBAR? */
275 } 374 }
276 375
277 /* Set base addr of the 8240/107 EUMB. */ 376 /* Set base addr of the 8240/107 EUMB. */
278 early_write_config_dword(hose, 377 early_write_config_dword(hose,
279 0, 378 0,
@@ -287,17 +386,6 @@ mpc10x_bridge_init(struct pci_controller *hose,
287 ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET, 386 ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
288 MPC10X_EUMB_EPIC_SIZE); 387 MPC10X_EUMB_EPIC_SIZE);
289#endif 388#endif
290 mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET;
291 mpc10x_i2c_ocp.irq = MPC10X_I2C_IRQ;
292 ocp_add_one_device(&mpc10x_i2c_ocp);
293 mpc10x_dma_ocp[0].paddr = phys_eumb_base +
294 MPC10X_EUMB_DMA_OFFSET + 0x100;
295 mpc10x_dma_ocp[0].irq = MPC10X_DMA0_IRQ;
296 ocp_add_one_device(&mpc10x_dma_ocp[0]);
297 mpc10x_dma_ocp[1].paddr = phys_eumb_base +
298 MPC10X_EUMB_DMA_OFFSET + 0x200;
299 mpc10x_dma_ocp[1].irq = MPC10X_DMA1_IRQ;
300 ocp_add_one_device(&mpc10x_dma_ocp[1]);
301 } 389 }
302 390
303#ifdef CONFIG_MPC10X_STORE_GATHERING 391#ifdef CONFIG_MPC10X_STORE_GATHERING
@@ -306,6 +394,29 @@ mpc10x_bridge_init(struct pci_controller *hose,
306 mpc10x_disable_store_gathering(hose); 394 mpc10x_disable_store_gathering(hose);
307#endif 395#endif
308 396
397 /* setup platform devices for MPC10x bridges */
398 identify_ppc_sys_by_id (host_bridge);
399
400 for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
401 unsigned int dev_id = cur_ppc_sys_spec->device_list[i];
402 ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id],
403 phys_eumb_base);
404 }
405
406 /* IRQ's are determined at runtime */
407 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ;
408 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ;
409 ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ;
410 ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ;
411 ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
412 ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
413
414 serial_platform_data[0].mapbase += phys_eumb_base;
415 serial_platform_data[0].irq = MPC10X_UART0_IRQ;
416
417 serial_platform_data[1].mapbase += phys_eumb_base;
418 serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1;
419
309 /* 420 /*
310 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative 421 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
311 * PCI reads may return stale data so turn off. 422 * PCI reads may return stale data so turn off.
@@ -330,7 +441,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
330 * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd. 441 * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd.
331 */ 442 */
332 if (host_bridge == MPC10X_BRIDGE_8245) { 443 if (host_bridge == MPC10X_BRIDGE_8245) {
333 ulong picr2; 444 u32 picr2;
334 445
335 early_read_config_dword(hose, 0, PCI_DEVFN(0,0), 446 early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
336 MPC10X_CFG_PICR2_REG, &picr2); 447 MPC10X_CFG_PICR2_REG, &picr2);
@@ -504,6 +615,8 @@ void __init mpc10x_set_openpic(void)
504 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020); 615 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
505 /* Skip reserved space and map Message Unit Interrupt (I2O) */ 616 /* Skip reserved space and map Message Unit Interrupt (I2O) */
506 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0); 617 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
618 /* Skip reserved space and map Serial Interupts */
619 openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120);
507 620
508 openpic_init(NUM_8259_INTERRUPTS); 621 openpic_init(NUM_8259_INTERRUPTS);
509} 622}
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index 1e658ef57e75..8af322dd476a 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -40,6 +40,42 @@ static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41}; 41};
42 42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
50};
51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
59};
60
61static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
62 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
63 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
68};
69
70static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
71 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
72 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
77};
78
43static struct gianfar_platform_data mpc85xx_fec_pdata = { 79static struct gianfar_platform_data mpc85xx_fec_pdata = {
44 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 80 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
45}; 81};
@@ -48,6 +84,10 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
48 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, 84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49}; 85};
50 86
87static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
88 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
89};
90
51static struct plat_serial8250_port serial_platform_data[] = { 91static struct plat_serial8250_port serial_platform_data[] = {
52 [0] = { 92 [0] = {
53 .mapbase = 0x4500, 93 .mapbase = 0x4500,
@@ -281,7 +321,6 @@ struct platform_device ppc_sys_platform_devices[] = {
281 }, 321 },
282 }, 322 },
283 }, 323 },
284#ifdef CONFIG_CPM2
285 [MPC85xx_CPM_FCC1] = { 324 [MPC85xx_CPM_FCC1] = {
286 .name = "fsl-cpm-fcc", 325 .name = "fsl-cpm-fcc",
287 .id = 1, 326 .id = 1,
@@ -535,7 +574,151 @@ struct platform_device ppc_sys_platform_devices[] = {
535 }, 574 },
536 }, 575 },
537 }, 576 },
538#endif /* CONFIG_CPM2 */ 577 [MPC85xx_eTSEC1] = {
578 .name = "fsl-gianfar",
579 .id = 1,
580 .dev.platform_data = &mpc85xx_etsec1_pdata,
581 .num_resources = 4,
582 .resource = (struct resource[]) {
583 {
584 .start = MPC85xx_ENET1_OFFSET,
585 .end = MPC85xx_ENET1_OFFSET +
586 MPC85xx_ENET1_SIZE - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .name = "tx",
591 .start = MPC85xx_IRQ_TSEC1_TX,
592 .end = MPC85xx_IRQ_TSEC1_TX,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .name = "rx",
597 .start = MPC85xx_IRQ_TSEC1_RX,
598 .end = MPC85xx_IRQ_TSEC1_RX,
599 .flags = IORESOURCE_IRQ,
600 },
601 {
602 .name = "error",
603 .start = MPC85xx_IRQ_TSEC1_ERROR,
604 .end = MPC85xx_IRQ_TSEC1_ERROR,
605 .flags = IORESOURCE_IRQ,
606 },
607 },
608 },
609 [MPC85xx_eTSEC2] = {
610 .name = "fsl-gianfar",
611 .id = 2,
612 .dev.platform_data = &mpc85xx_etsec2_pdata,
613 .num_resources = 4,
614 .resource = (struct resource[]) {
615 {
616 .start = MPC85xx_ENET2_OFFSET,
617 .end = MPC85xx_ENET2_OFFSET +
618 MPC85xx_ENET2_SIZE - 1,
619 .flags = IORESOURCE_MEM,
620 },
621 {
622 .name = "tx",
623 .start = MPC85xx_IRQ_TSEC2_TX,
624 .end = MPC85xx_IRQ_TSEC2_TX,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
628 .name = "rx",
629 .start = MPC85xx_IRQ_TSEC2_RX,
630 .end = MPC85xx_IRQ_TSEC2_RX,
631 .flags = IORESOURCE_IRQ,
632 },
633 {
634 .name = "error",
635 .start = MPC85xx_IRQ_TSEC2_ERROR,
636 .end = MPC85xx_IRQ_TSEC2_ERROR,
637 .flags = IORESOURCE_IRQ,
638 },
639 },
640 },
641 [MPC85xx_eTSEC3] = {
642 .name = "fsl-gianfar",
643 .id = 3,
644 .dev.platform_data = &mpc85xx_etsec3_pdata,
645 .num_resources = 4,
646 .resource = (struct resource[]) {
647 {
648 .start = MPC85xx_ENET3_OFFSET,
649 .end = MPC85xx_ENET3_OFFSET +
650 MPC85xx_ENET3_SIZE - 1,
651 .flags = IORESOURCE_MEM,
652 },
653 {
654 .name = "tx",
655 .start = MPC85xx_IRQ_TSEC3_TX,
656 .end = MPC85xx_IRQ_TSEC3_TX,
657 .flags = IORESOURCE_IRQ,
658 },
659 {
660 .name = "rx",
661 .start = MPC85xx_IRQ_TSEC3_RX,
662 .end = MPC85xx_IRQ_TSEC3_RX,
663 .flags = IORESOURCE_IRQ,
664 },
665 {
666 .name = "error",
667 .start = MPC85xx_IRQ_TSEC3_ERROR,
668 .end = MPC85xx_IRQ_TSEC3_ERROR,
669 .flags = IORESOURCE_IRQ,
670 },
671 },
672 },
673 [MPC85xx_eTSEC4] = {
674 .name = "fsl-gianfar",
675 .id = 4,
676 .dev.platform_data = &mpc85xx_etsec4_pdata,
677 .num_resources = 4,
678 .resource = (struct resource[]) {
679 {
680 .start = 0x27000,
681 .end = 0x27fff,
682 .flags = IORESOURCE_MEM,
683 },
684 {
685 .name = "tx",
686 .start = MPC85xx_IRQ_TSEC4_TX,
687 .end = MPC85xx_IRQ_TSEC4_TX,
688 .flags = IORESOURCE_IRQ,
689 },
690 {
691 .name = "rx",
692 .start = MPC85xx_IRQ_TSEC4_RX,
693 .end = MPC85xx_IRQ_TSEC4_RX,
694 .flags = IORESOURCE_IRQ,
695 },
696 {
697 .name = "error",
698 .start = MPC85xx_IRQ_TSEC4_ERROR,
699 .end = MPC85xx_IRQ_TSEC4_ERROR,
700 .flags = IORESOURCE_IRQ,
701 },
702 },
703 },
704 [MPC85xx_IIC2] = {
705 .name = "fsl-i2c",
706 .id = 2,
707 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
708 .num_resources = 2,
709 .resource = (struct resource[]) {
710 {
711 .start = 0x03100,
712 .end = 0x031ff,
713 .flags = IORESOURCE_MEM,
714 },
715 {
716 .start = MPC85xx_IRQ_IIC1,
717 .end = MPC85xx_IRQ_IIC1,
718 .flags = IORESOURCE_IRQ,
719 },
720 },
721 },
539}; 722};
540 723
541static int __init mach_mpc85xx_fixup(struct platform_device *pdev) 724static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index d806a92a9401..6e3184ab354f 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -110,6 +110,111 @@ struct ppc_sys_spec ppc_sys_specs[] = {
110 MPC85xx_CPM_USB, 110 MPC85xx_CPM_USB,
111 }, 111 },
112 }, 112 },
113 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
114 {
115 .ppc_sys_name = "8548E",
116 .mask = 0xFFFF00F0,
117 .value = 0x80390010,
118 .num_devices = 13,
119 .device_list = (enum ppc_sys_devices[])
120 {
121 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
122 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
123 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
124 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
125 },
126 },
127 {
128 .ppc_sys_name = "8548",
129 .mask = 0xFFFF00F0,
130 .value = 0x80310010,
131 .num_devices = 12,
132 .device_list = (enum ppc_sys_devices[])
133 {
134 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
135 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
136 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
137 MPC85xx_PERFMON, MPC85xx_DUART,
138 },
139 },
140 {
141 .ppc_sys_name = "8547E",
142 .mask = 0xFFFF00F0,
143 .value = 0x80390010,
144 .num_devices = 13,
145 .device_list = (enum ppc_sys_devices[])
146 {
147 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
148 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
149 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
150 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
151 },
152 },
153 {
154 .ppc_sys_name = "8547",
155 .mask = 0xFFFF00F0,
156 .value = 0x80310010,
157 .num_devices = 12,
158 .device_list = (enum ppc_sys_devices[])
159 {
160 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
161 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
162 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
163 MPC85xx_PERFMON, MPC85xx_DUART,
164 },
165 },
166 {
167 .ppc_sys_name = "8545E",
168 .mask = 0xFFFF00F0,
169 .value = 0x80390010,
170 .num_devices = 11,
171 .device_list = (enum ppc_sys_devices[])
172 {
173 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
174 MPC85xx_IIC1, MPC85xx_IIC2,
175 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
176 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
177 },
178 },
179 {
180 .ppc_sys_name = "8545",
181 .mask = 0xFFFF00F0,
182 .value = 0x80310010,
183 .num_devices = 10,
184 .device_list = (enum ppc_sys_devices[])
185 {
186 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
187 MPC85xx_IIC1, MPC85xx_IIC2,
188 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
189 MPC85xx_PERFMON, MPC85xx_DUART,
190 },
191 },
192 {
193 .ppc_sys_name = "8543E",
194 .mask = 0xFFFF00F0,
195 .value = 0x803A0010,
196 .num_devices = 11,
197 .device_list = (enum ppc_sys_devices[])
198 {
199 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
200 MPC85xx_IIC1, MPC85xx_IIC2,
201 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
202 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
203 },
204 },
205 {
206 .ppc_sys_name = "8543",
207 .mask = 0xFFFF00F0,
208 .value = 0x80320010,
209 .num_devices = 10,
210 .device_list = (enum ppc_sys_devices[])
211 {
212 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
213 MPC85xx_IIC1, MPC85xx_IIC2,
214 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
215 MPC85xx_PERFMON, MPC85xx_DUART,
216 },
217 },
113 { /* default match */ 218 { /* default match */
114 .ppc_sys_name = "", 219 .ppc_sys_name = "",
115 .mask = 0x00000000, 220 .mask = 0x00000000,
diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
index 7b241e7876bd..cc77177fa1c6 100644
--- a/arch/ppc/syslib/mv64x60.c
+++ b/arch/ppc/syslib/mv64x60.c
@@ -17,7 +17,6 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/string.h> 19#include <linux/string.h>
20#include <linux/bootmem.h>
21#include <linux/spinlock.h> 20#include <linux/spinlock.h>
22#include <linux/mv643xx.h> 21#include <linux/mv643xx.h>
23 22
diff --git a/arch/ppc/syslib/mv64x60_win.c b/arch/ppc/syslib/mv64x60_win.c
index b6f0f5dcf6ee..5b827e2bbe22 100644
--- a/arch/ppc/syslib/mv64x60_win.c
+++ b/arch/ppc/syslib/mv64x60_win.c
@@ -17,7 +17,6 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/string.h> 19#include <linux/string.h>
20#include <linux/bootmem.h>
21#include <linux/mv643xx.h> 20#include <linux/mv643xx.h>
22 21
23#include <asm/byteorder.h> 22#include <asm/byteorder.h>
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index a5156c5179a6..e5fd2ae503ea 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -68,7 +68,7 @@ static int ocp_inited;
68/* Sysfs support */ 68/* Sysfs support */
69#define OCP_DEF_ATTR(field, format_string) \ 69#define OCP_DEF_ATTR(field, format_string) \
70static ssize_t \ 70static ssize_t \
71show_##field(struct device *dev, char *buf) \ 71show_##field(struct device *dev, struct device_attribute *attr, char *buf) \
72{ \ 72{ \
73 struct ocp_device *odev = to_ocp_dev(dev); \ 73 struct ocp_device *odev = to_ocp_dev(dev); \
74 \ 74 \
diff --git a/arch/ppc/syslib/of_device.c b/arch/ppc/syslib/of_device.c
index 46269ed21aee..49c0e34e2d6b 100644
--- a/arch/ppc/syslib/of_device.c
+++ b/arch/ppc/syslib/of_device.c
@@ -161,7 +161,7 @@ void of_unregister_driver(struct of_platform_driver *drv)
161} 161}
162 162
163 163
164static ssize_t dev_show_devspec(struct device *dev, char *buf) 164static ssize_t dev_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
165{ 165{
166 struct of_device *ofdev; 166 struct of_device *ofdev;
167 167
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 000ba47c67cb..ad39b86ca92c 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -21,7 +21,6 @@
21#include <asm/signal.h> 21#include <asm/signal.h>
22#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/prom.h>
25#include <asm/sections.h> 24#include <asm/sections.h>
26#include <asm/open_pic.h> 25#include <asm/open_pic.h>
27#include <asm/i8259.h> 26#include <asm/i8259.h>
@@ -371,8 +370,9 @@ void __init openpic_init(int offset)
371 /* Initialize IPI interrupts */ 370 /* Initialize IPI interrupts */
372 if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb); 371 if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
373 for (i = 0; i < OPENPIC_NUM_IPI; i++) { 372 for (i = 0; i < OPENPIC_NUM_IPI; i++) {
374 /* Disabled, Priority 10..13 */ 373 /* Disabled, increased priorities 10..13 */
375 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset); 374 openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
375 OPENPIC_VEC_IPI+i+offset);
376 /* IPIs are per-CPU */ 376 /* IPIs are per-CPU */
377 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU; 377 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
378 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi; 378 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
@@ -400,8 +400,9 @@ void __init openpic_init(int offset)
400 if (sense & IRQ_SENSE_MASK) 400 if (sense & IRQ_SENSE_MASK)
401 irq_desc[i+offset].status = IRQ_LEVEL; 401 irq_desc[i+offset].status = IRQ_LEVEL;
402 402
403 /* Enabled, Priority 8 */ 403 /* Enabled, Default priority */
404 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK), 404 openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
405 (sense & IRQ_POLARITY_MASK),
405 (sense & IRQ_SENSE_MASK)); 406 (sense & IRQ_SENSE_MASK));
406 /* Processor 0 */ 407 /* Processor 0 */
407 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE); 408 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
@@ -657,6 +658,18 @@ static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
657} 658}
658 659
659/* 660/*
661 * Change the priority of an interrupt
662 */
663void __init
664openpic_set_irq_priority(u_int irq, u_int pri)
665{
666 check_arg_irq(irq);
667 openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
668 OPENPIC_PRIORITY_MASK,
669 pri << OPENPIC_PRIORITY_SHIFT);
670}
671
672/*
660 * Initalize the interrupt source which will generate an NMI. 673 * Initalize the interrupt source which will generate an NMI.
661 * This raises the interrupt's priority from 8 to 9. 674 * This raises the interrupt's priority from 8 to 9.
662 * 675 *
@@ -666,9 +679,7 @@ void __init
666openpic_init_nmi_irq(u_int irq) 679openpic_init_nmi_irq(u_int irq)
667{ 680{
668 check_arg_irq(irq); 681 check_arg_irq(irq);
669 openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority, 682 openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
670 OPENPIC_PRIORITY_MASK,
671 9 << OPENPIC_PRIORITY_SHIFT);
672} 683}
673 684
674/* 685/*
diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c
index ea26da0d8b6b..7e272c51a497 100644
--- a/arch/ppc/syslib/open_pic2.c
+++ b/arch/ppc/syslib/open_pic2.c
@@ -25,7 +25,6 @@
25#include <asm/signal.h> 25#include <asm/signal.h>
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/prom.h>
29#include <asm/sections.h> 28#include <asm/sections.h>
30#include <asm/open_pic.h> 29#include <asm/open_pic.h>
31#include <asm/i8259.h> 30#include <asm/i8259.h>
diff --git a/arch/ppc/syslib/ppc4xx_kgdb.c b/arch/ppc/syslib/ppc4xx_kgdb.c
deleted file mode 100644
index fe8668bf8137..000000000000
--- a/arch/ppc/syslib/ppc4xx_kgdb.c
+++ /dev/null
@@ -1,124 +0,0 @@
1#include <linux/config.h>
2#include <linux/types.h>
3#include <asm/ibm4xx.h>
4#include <linux/kernel.h>
5
6
7
8#define LSR_DR 0x01 /* Data ready */
9#define LSR_OE 0x02 /* Overrun */
10#define LSR_PE 0x04 /* Parity error */
11#define LSR_FE 0x08 /* Framing error */
12#define LSR_BI 0x10 /* Break */
13#define LSR_THRE 0x20 /* Xmit holding register empty */
14#define LSR_TEMT 0x40 /* Xmitter empty */
15#define LSR_ERR 0x80 /* Error */
16
17#include <platforms/4xx/ibm_ocp.h>
18
19extern struct NS16550* COM_PORTS[];
20#ifndef NULL
21#define NULL 0x00
22#endif
23
24static volatile struct NS16550 *kgdb_debugport = NULL;
25
26volatile struct NS16550 *
27NS16550_init(int chan)
28{
29 volatile struct NS16550 *com_port;
30 int quot;
31#ifdef BASE_BAUD
32 quot = BASE_BAUD / 9600;
33#else
34 quot = 0x000c; /* 0xc = 9600 baud (on a pc) */
35#endif
36
37 com_port = (struct NS16550 *) COM_PORTS[chan];
38
39 com_port->lcr = 0x00;
40 com_port->ier = 0xFF;
41 com_port->ier = 0x00;
42 com_port->lcr = com_port->lcr | 0x80; /* Access baud rate */
43 com_port->dll = ( quot & 0x00ff ); /* 0xc = 9600 baud */
44 com_port->dlm = ( quot & 0xff00 ) >> 8;
45 com_port->lcr = 0x03; /* 8 data, 1 stop, no parity */
46 com_port->mcr = 0x00; /* RTS/DTR */
47 com_port->fcr = 0x07; /* Clear & enable FIFOs */
48
49 return( com_port );
50}
51
52
53void
54NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
55{
56 while ((com_port->lsr & LSR_THRE) == 0)
57 ;
58 com_port->thr = c;
59 return;
60}
61
62unsigned char
63NS16550_getc(volatile struct NS16550 *com_port)
64{
65 while ((com_port->lsr & LSR_DR) == 0)
66 ;
67 return (com_port->rbr);
68}
69
70unsigned char
71NS16550_tstc(volatile struct NS16550 *com_port)
72{
73 return ((com_port->lsr & LSR_DR) != 0);
74}
75
76
77#if defined(CONFIG_KGDB_TTYS0)
78#define KGDB_PORT 0
79#elif defined(CONFIG_KGDB_TTYS1)
80#define KGDB_PORT 1
81#elif defined(CONFIG_KGDB_TTYS2)
82#define KGDB_PORT 2
83#elif defined(CONFIG_KGDB_TTYS3)
84#define KGDB_PORT 3
85#else
86#error "invalid kgdb_tty port"
87#endif
88
89void putDebugChar( unsigned char c )
90{
91 if ( kgdb_debugport == NULL )
92 kgdb_debugport = NS16550_init(KGDB_PORT);
93 NS16550_putc( kgdb_debugport, c );
94}
95
96int getDebugChar( void )
97{
98 if (kgdb_debugport == NULL)
99 kgdb_debugport = NS16550_init(KGDB_PORT);
100
101 return(NS16550_getc(kgdb_debugport));
102}
103
104void kgdb_interruptible(int enable)
105{
106 return;
107}
108
109void putDebugString(char* str)
110{
111 while (*str != '\0') {
112 putDebugChar(*str);
113 str++;
114 }
115 putDebugChar('\r');
116 return;
117}
118
119void
120kgdb_map_scc(void)
121{
122 printk("kgdb init \n");
123 kgdb_debugport = NS16550_init(KGDB_PORT);
124}
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index 843cf8873e60..602a86891f7f 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -23,7 +23,6 @@
23#include <linux/serial_core.h> 23#include <linux/serial_core.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <asm/prom.h>
27#include <asm/time.h> 26#include <asm/time.h>
28#include <asm/mpc83xx.h> 27#include <asm/mpc83xx.h>
29#include <asm/mmu.h> 28#include <asm/mmu.h>
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index f3277f469e78..ca95d79a704e 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -23,7 +23,6 @@
23#include <linux/serial_core.h> 23#include <linux/serial_core.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <asm/prom.h>
27#include <asm/time.h> 26#include <asm/time.h>
28#include <asm/mpc85xx.h> 27#include <asm/mpc85xx.h>
29#include <asm/immap_85xx.h> 28#include <asm/immap_85xx.h>
@@ -33,6 +32,8 @@
33 32
34#include <syslib/ppc85xx_setup.h> 33#include <syslib/ppc85xx_setup.h>
35 34
35extern void abort(void);
36
36/* Return the amount of memory */ 37/* Return the amount of memory */
37unsigned long __init 38unsigned long __init
38mpc85xx_find_end_of_memory(void) 39mpc85xx_find_end_of_memory(void)
@@ -133,7 +134,7 @@ mpc85xx_halt(void)
133 134
134#ifdef CONFIG_PCI 135#ifdef CONFIG_PCI
135 136
136#if defined(CONFIG_MPC8555_CDS) 137#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
137extern void mpc85xx_cds_enable_via(struct pci_controller *hose); 138extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
138extern void mpc85xx_cds_fixup_via(struct pci_controller *hose); 139extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
139#endif 140#endif
@@ -308,14 +309,14 @@ mpc85xx_setup_hose(void)
308 309
309 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 310 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
310 311
311#if defined(CONFIG_MPC8555_CDS) 312#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
312 /* Pre pciauto_bus_scan VIA init */ 313 /* Pre pciauto_bus_scan VIA init */
313 mpc85xx_cds_enable_via(hose_a); 314 mpc85xx_cds_enable_via(hose_a);
314#endif 315#endif
315 316
316 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); 317 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
317 318
318#if defined(CONFIG_MPC8555_CDS) 319#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
319 /* Post pciauto_bus_scan VIA fixup */ 320 /* Post pciauto_bus_scan VIA fixup */
320 mpc85xx_cds_fixup_via(hose_a); 321 mpc85xx_cds_fixup_via(hose_a);
321#endif 322#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 14:23:56 -0500