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-rw-r--r--arch/ppc/syslib/Makefile14
-rw-r--r--arch/ppc/syslib/gt64260_pic.c1
-rw-r--r--arch/ppc/syslib/ipic.c646
-rw-r--r--arch/ppc/syslib/ipic.h47
-rw-r--r--arch/ppc/syslib/mpc52xx_pic.c1
-rw-r--r--arch/ppc/syslib/mpc52xx_setup.c36
-rw-r--r--arch/ppc/syslib/mpc83xx_devices.c251
-rw-r--r--arch/ppc/syslib/mpc83xx_sys.c122
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c826
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c233
-rw-r--r--arch/ppc/syslib/mpc8xx_devices.c2
-rw-r--r--arch/ppc/syslib/mv64360_pic.c1
-rw-r--r--arch/ppc/syslib/ocp.c4
-rw-r--r--arch/ppc/syslib/open_pic.c2
-rw-r--r--arch/ppc/syslib/ppc83xx_pci.h151
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c411
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.h55
-rw-r--r--arch/ppc/syslib/ppc85xx_common.c38
-rw-r--r--arch/ppc/syslib/ppc85xx_common.h22
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.c932
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.h20
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c367
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.h56
-rw-r--r--arch/ppc/syslib/ppc8xx_pic.c2
-rw-r--r--arch/ppc/syslib/ppc8xx_pic.h1
-rw-r--r--arch/ppc/syslib/ppc_sys.c2
26 files changed, 42 insertions, 4201 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 543795be58c8..52ddebe6c6d1 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -87,20 +87,6 @@ endif
87obj-$(CONFIG_BOOTX_TEXT) += btext.o 87obj-$(CONFIG_BOOTX_TEXT) += btext.o
88obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o 88obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o
89obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o 89obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o
90obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
91 ppc_sys.o mpc85xx_sys.o \
92 mpc85xx_devices.o
93ifeq ($(CONFIG_85xx),y)
94obj-$(CONFIG_PCI) += pci_auto.o
95endif
96obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
97obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
98 mpc83xx_sys.o mpc83xx_devices.o ipic.o
99ifeq ($(CONFIG_83xx),y)
100obj-$(CONFIG_PCI) += pci_auto.o
101endif
102obj-$(CONFIG_MPC8548_CDS) += todc_time.o
103obj-$(CONFIG_MPC8555_CDS) += todc_time.o
104obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ 90obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
105 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o 91 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o
106ifeq ($(CONFIG_PPC_MPC52xx),y) 92ifeq ($(CONFIG_PPC_MPC52xx),y)
diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c
index e84d432c0657..3b4fcca5d1e1 100644
--- a/arch/ppc/syslib/gt64260_pic.c
+++ b/arch/ppc/syslib/gt64260_pic.c
@@ -35,7 +35,6 @@
35#include <linux/interrupt.h> 35#include <linux/interrupt.h>
36#include <linux/sched.h> 36#include <linux/sched.h>
37#include <linux/signal.h> 37#include <linux/signal.h>
38#include <linux/stddef.h>
39#include <linux/delay.h> 38#include <linux/delay.h>
40#include <linux/irq.h> 39#include <linux/irq.h>
41 40
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
deleted file mode 100644
index 4f163e20939e..000000000000
--- a/arch/ppc/syslib/ipic.c
+++ /dev/null
@@ -1,646 +0,0 @@
1/*
2 * arch/ppc/syslib/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26
27#include "ipic.h"
28
29static struct ipic p_ipic;
30static struct ipic * primary_ipic;
31
32static struct ipic_info ipic_info[] = {
33 [9] = {
34 .pend = IPIC_SIPNR_H,
35 .mask = IPIC_SIMSR_H,
36 .prio = IPIC_SIPRR_D,
37 .force = IPIC_SIFCR_H,
38 .bit = 24,
39 .prio_mask = 0,
40 },
41 [10] = {
42 .pend = IPIC_SIPNR_H,
43 .mask = IPIC_SIMSR_H,
44 .prio = IPIC_SIPRR_D,
45 .force = IPIC_SIFCR_H,
46 .bit = 25,
47 .prio_mask = 1,
48 },
49 [11] = {
50 .pend = IPIC_SIPNR_H,
51 .mask = IPIC_SIMSR_H,
52 .prio = IPIC_SIPRR_D,
53 .force = IPIC_SIFCR_H,
54 .bit = 26,
55 .prio_mask = 2,
56 },
57 [14] = {
58 .pend = IPIC_SIPNR_H,
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 29,
63 .prio_mask = 5,
64 },
65 [15] = {
66 .pend = IPIC_SIPNR_H,
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_D,
69 .force = IPIC_SIFCR_H,
70 .bit = 30,
71 .prio_mask = 6,
72 },
73 [16] = {
74 .pend = IPIC_SIPNR_H,
75 .mask = IPIC_SIMSR_H,
76 .prio = IPIC_SIPRR_D,
77 .force = IPIC_SIFCR_H,
78 .bit = 31,
79 .prio_mask = 7,
80 },
81 [17] = {
82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR,
86 .bit = 1,
87 .prio_mask = 5,
88 },
89 [18] = {
90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR,
94 .bit = 2,
95 .prio_mask = 6,
96 },
97 [19] = {
98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR,
102 .bit = 3,
103 .prio_mask = 7,
104 },
105 [20] = {
106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR,
110 .bit = 4,
111 .prio_mask = 4,
112 },
113 [21] = {
114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR,
118 .bit = 5,
119 .prio_mask = 5,
120 },
121 [22] = {
122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR,
126 .bit = 6,
127 .prio_mask = 6,
128 },
129 [23] = {
130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR,
134 .bit = 7,
135 .prio_mask = 7,
136 },
137 [32] = {
138 .pend = IPIC_SIPNR_H,
139 .mask = IPIC_SIMSR_H,
140 .prio = IPIC_SIPRR_A,
141 .force = IPIC_SIFCR_H,
142 .bit = 0,
143 .prio_mask = 0,
144 },
145 [33] = {
146 .pend = IPIC_SIPNR_H,
147 .mask = IPIC_SIMSR_H,
148 .prio = IPIC_SIPRR_A,
149 .force = IPIC_SIFCR_H,
150 .bit = 1,
151 .prio_mask = 1,
152 },
153 [34] = {
154 .pend = IPIC_SIPNR_H,
155 .mask = IPIC_SIMSR_H,
156 .prio = IPIC_SIPRR_A,
157 .force = IPIC_SIFCR_H,
158 .bit = 2,
159 .prio_mask = 2,
160 },
161 [35] = {
162 .pend = IPIC_SIPNR_H,
163 .mask = IPIC_SIMSR_H,
164 .prio = IPIC_SIPRR_A,
165 .force = IPIC_SIFCR_H,
166 .bit = 3,
167 .prio_mask = 3,
168 },
169 [36] = {
170 .pend = IPIC_SIPNR_H,
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 4,
175 .prio_mask = 4,
176 },
177 [37] = {
178 .pend = IPIC_SIPNR_H,
179 .mask = IPIC_SIMSR_H,
180 .prio = IPIC_SIPRR_A,
181 .force = IPIC_SIFCR_H,
182 .bit = 5,
183 .prio_mask = 5,
184 },
185 [38] = {
186 .pend = IPIC_SIPNR_H,
187 .mask = IPIC_SIMSR_H,
188 .prio = IPIC_SIPRR_A,
189 .force = IPIC_SIFCR_H,
190 .bit = 6,
191 .prio_mask = 6,
192 },
193 [39] = {
194 .pend = IPIC_SIPNR_H,
195 .mask = IPIC_SIMSR_H,
196 .prio = IPIC_SIPRR_A,
197 .force = IPIC_SIFCR_H,
198 .bit = 7,
199 .prio_mask = 7,
200 },
201 [48] = {
202 .pend = IPIC_SEPNR,
203 .mask = IPIC_SEMSR,
204 .prio = IPIC_SMPRR_A,
205 .force = IPIC_SEFCR,
206 .bit = 0,
207 .prio_mask = 4,
208 },
209 [64] = {
210 .pend = IPIC_SIPNR_H,
211 .mask = IPIC_SIMSR_L,
212 .prio = IPIC_SMPRR_A,
213 .force = IPIC_SIFCR_L,
214 .bit = 0,
215 .prio_mask = 0,
216 },
217 [65] = {
218 .pend = IPIC_SIPNR_H,
219 .mask = IPIC_SIMSR_L,
220 .prio = IPIC_SMPRR_A,
221 .force = IPIC_SIFCR_L,
222 .bit = 1,
223 .prio_mask = 1,
224 },
225 [66] = {
226 .pend = IPIC_SIPNR_H,
227 .mask = IPIC_SIMSR_L,
228 .prio = IPIC_SMPRR_A,
229 .force = IPIC_SIFCR_L,
230 .bit = 2,
231 .prio_mask = 2,
232 },
233 [67] = {
234 .pend = IPIC_SIPNR_H,
235 .mask = IPIC_SIMSR_L,
236 .prio = IPIC_SMPRR_A,
237 .force = IPIC_SIFCR_L,
238 .bit = 3,
239 .prio_mask = 3,
240 },
241 [68] = {
242 .pend = IPIC_SIPNR_H,
243 .mask = IPIC_SIMSR_L,
244 .prio = IPIC_SMPRR_B,
245 .force = IPIC_SIFCR_L,
246 .bit = 4,
247 .prio_mask = 0,
248 },
249 [69] = {
250 .pend = IPIC_SIPNR_H,
251 .mask = IPIC_SIMSR_L,
252 .prio = IPIC_SMPRR_B,
253 .force = IPIC_SIFCR_L,
254 .bit = 5,
255 .prio_mask = 1,
256 },
257 [70] = {
258 .pend = IPIC_SIPNR_H,
259 .mask = IPIC_SIMSR_L,
260 .prio = IPIC_SMPRR_B,
261 .force = IPIC_SIFCR_L,
262 .bit = 6,
263 .prio_mask = 2,
264 },
265 [71] = {
266 .pend = IPIC_SIPNR_H,
267 .mask = IPIC_SIMSR_L,
268 .prio = IPIC_SMPRR_B,
269 .force = IPIC_SIFCR_L,
270 .bit = 7,
271 .prio_mask = 3,
272 },
273 [72] = {
274 .pend = IPIC_SIPNR_H,
275 .mask = IPIC_SIMSR_L,
276 .prio = 0,
277 .force = IPIC_SIFCR_L,
278 .bit = 8,
279 },
280 [73] = {
281 .pend = IPIC_SIPNR_H,
282 .mask = IPIC_SIMSR_L,
283 .prio = 0,
284 .force = IPIC_SIFCR_L,
285 .bit = 9,
286 },
287 [74] = {
288 .pend = IPIC_SIPNR_H,
289 .mask = IPIC_SIMSR_L,
290 .prio = 0,
291 .force = IPIC_SIFCR_L,
292 .bit = 10,
293 },
294 [75] = {
295 .pend = IPIC_SIPNR_H,
296 .mask = IPIC_SIMSR_L,
297 .prio = 0,
298 .force = IPIC_SIFCR_L,
299 .bit = 11,
300 },
301 [76] = {
302 .pend = IPIC_SIPNR_H,
303 .mask = IPIC_SIMSR_L,
304 .prio = 0,
305 .force = IPIC_SIFCR_L,
306 .bit = 12,
307 },
308 [77] = {
309 .pend = IPIC_SIPNR_H,
310 .mask = IPIC_SIMSR_L,
311 .prio = 0,
312 .force = IPIC_SIFCR_L,
313 .bit = 13,
314 },
315 [78] = {
316 .pend = IPIC_SIPNR_H,
317 .mask = IPIC_SIMSR_L,
318 .prio = 0,
319 .force = IPIC_SIFCR_L,
320 .bit = 14,
321 },
322 [79] = {
323 .pend = IPIC_SIPNR_H,
324 .mask = IPIC_SIMSR_L,
325 .prio = 0,
326 .force = IPIC_SIFCR_L,
327 .bit = 15,
328 },
329 [80] = {
330 .pend = IPIC_SIPNR_H,
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 16,
335 },
336 [84] = {
337 .pend = IPIC_SIPNR_H,
338 .mask = IPIC_SIMSR_L,
339 .prio = 0,
340 .force = IPIC_SIFCR_L,
341 .bit = 20,
342 },
343 [85] = {
344 .pend = IPIC_SIPNR_H,
345 .mask = IPIC_SIMSR_L,
346 .prio = 0,
347 .force = IPIC_SIFCR_L,
348 .bit = 21,
349 },
350 [90] = {
351 .pend = IPIC_SIPNR_H,
352 .mask = IPIC_SIMSR_L,
353 .prio = 0,
354 .force = IPIC_SIFCR_L,
355 .bit = 26,
356 },
357 [91] = {
358 .pend = IPIC_SIPNR_H,
359 .mask = IPIC_SIMSR_L,
360 .prio = 0,
361 .force = IPIC_SIFCR_L,
362 .bit = 27,
363 },
364};
365
366static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
367{
368 return in_be32(base + (reg >> 2));
369}
370
371static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
372{
373 out_be32(base + (reg >> 2), value);
374}
375
376static inline struct ipic * ipic_from_irq(unsigned int irq)
377{
378 return primary_ipic;
379}
380
381static void ipic_enable_irq(unsigned int irq)
382{
383 struct ipic *ipic = ipic_from_irq(irq);
384 unsigned int src = irq - ipic->irq_offset;
385 u32 temp;
386
387 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp);
390}
391
392static void ipic_disable_irq(unsigned int irq)
393{
394 struct ipic *ipic = ipic_from_irq(irq);
395 unsigned int src = irq - ipic->irq_offset;
396 u32 temp;
397
398 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp);
401}
402
403static void ipic_disable_irq_and_ack(unsigned int irq)
404{
405 struct ipic *ipic = ipic_from_irq(irq);
406 unsigned int src = irq - ipic->irq_offset;
407 u32 temp;
408
409 ipic_disable_irq(irq);
410
411 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp);
414}
415
416static void ipic_end_irq(unsigned int irq)
417{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
419 ipic_enable_irq(irq);
420}
421
422struct hw_interrupt_type ipic = {
423 .typename = " IPIC ",
424 .enable = ipic_enable_irq,
425 .disable = ipic_disable_irq,
426 .ack = ipic_disable_irq_and_ack,
427 .end = ipic_end_irq,
428};
429
430void __init ipic_init(phys_addr_t phys_addr,
431 unsigned int flags,
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{
436 u32 i, temp = 0;
437
438 primary_ipic = &p_ipic;
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440
441 primary_ipic->irq_offset = irq_offset;
442
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
444
445 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */
447 if (flags & IPIC_SPREADMODE_GRP_A)
448 temp |= SICFR_IPSA;
449 if (flags & IPIC_SPREADMODE_GRP_D)
450 temp |= SICFR_IPSD;
451 if (flags & IPIC_SPREADMODE_MIX_A)
452 temp |= SICFR_MPSA;
453 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB;
455
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
457
458 /* handle MCP route */
459 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
463
464 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
466
467 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0;
469 else
470 temp &= ~SEMSR_SIRQ0;
471
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].chip = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478
479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493}
494
495int ipic_set_priority(unsigned int irq, unsigned int priority)
496{
497 struct ipic *ipic = ipic_from_irq(irq);
498 unsigned int src = irq - ipic->irq_offset;
499 u32 temp;
500
501 if (priority > 7)
502 return -EINVAL;
503 if (src > 127)
504 return -EINVAL;
505 if (ipic_info[src].prio == 0)
506 return -EINVAL;
507
508 temp = ipic_read(ipic->regs, ipic_info[src].prio);
509
510 if (priority < 4) {
511 temp &= ~(0x7 << (20 + (3 - priority) * 3));
512 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
513 } else {
514 temp &= ~(0x7 << (4 + (7 - priority) * 3));
515 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
516 }
517
518 ipic_write(ipic->regs, ipic_info[src].prio, temp);
519
520 return 0;
521}
522
523void ipic_set_highest_priority(unsigned int irq)
524{
525 struct ipic *ipic = ipic_from_irq(irq);
526 unsigned int src = irq - ipic->irq_offset;
527 u32 temp;
528
529 temp = ipic_read(ipic->regs, IPIC_SICFR);
530
531 /* clear and set HPI */
532 temp &= 0x7f000000;
533 temp |= (src & 0x7f) << 24;
534
535 ipic_write(ipic->regs, IPIC_SICFR, temp);
536}
537
538void ipic_set_default_priority(void)
539{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571}
572
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
574{
575 struct ipic *ipic = primary_ipic;
576 u32 temp;
577
578 temp = ipic_read(ipic->regs, IPIC_SERMR);
579 temp |= (1 << (31 - mcp_irq));
580 ipic_write(ipic->regs, IPIC_SERMR, temp);
581}
582
583void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
584{
585 struct ipic *ipic = primary_ipic;
586 u32 temp;
587
588 temp = ipic_read(ipic->regs, IPIC_SERMR);
589 temp &= (1 << (31 - mcp_irq));
590 ipic_write(ipic->regs, IPIC_SERMR, temp);
591}
592
593u32 ipic_get_mcp_status(void)
594{
595 return ipic_read(primary_ipic->regs, IPIC_SERMR);
596}
597
598void ipic_clear_mcp_status(u32 mask)
599{
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601}
602
603/* Return an interrupt vector or -1 if no interrupt is pending. */
604int ipic_get_irq(void)
605{
606 int irq;
607
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
609
610 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1;
612
613 return irq;
614}
615
616static struct sysdev_class ipic_sysclass = {
617 .name = "ipic",
618};
619
620static struct sys_device device_ipic = {
621 .id = 0,
622 .cls = &ipic_sysclass,
623};
624
625static int __init init_ipic_sysfs(void)
626{
627 int rc;
628
629 if (!primary_ipic->regs)
630 return -ENODEV;
631 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
632
633 rc = sysdev_class_register(&ipic_sysclass);
634 if (rc) {
635 printk(KERN_ERR "Failed registering ipic sys class\n");
636 return -ENODEV;
637 }
638 rc = sysdev_register(&device_ipic);
639 if (rc) {
640 printk(KERN_ERR "Failed registering ipic sys device\n");
641 return -ENODEV;
642 }
643 return 0;
644}
645
646subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
deleted file mode 100644
index a60c9d18bb7f..000000000000
--- a/arch/ppc/syslib/ipic.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * IPIC private definitions and structure.
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __IPIC_H__
14#define __IPIC_H__
15
16#include <asm/ipic.h>
17
18#define MPC83xx_IPIC_SIZE (0x00100)
19
20/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000
22#define SICFR_IPSD 0x00080000
23#define SICFR_MPSA 0x00200000
24#define SICFR_MPSB 0x00400000
25
26/* System External Interrupt Mask Register */
27#define SEMSR_SIRQ0 0x00008000
28
29/* System Error Control Register */
30#define SERCR_MCPR 0x00000001
31
32struct ipic {
33 volatile u32 __iomem *regs;
34 unsigned int irq_offset;
35};
36
37struct ipic_info {
38 u8 pend; /* pending register offset from base */
39 u8 mask; /* mask register offset from base */
40 u8 prio; /* priority register offset from base */
41 u8 force; /* force register offset from base */
42 u8 bit; /* register bit position (as per doc)
43 bit mask = 1 << (31 - bit) */
44 u8 prio_mask; /* priority mask value */
45};
46
47#endif /* __IPIC_H__ */
diff --git a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c
index af35a316544a..f58149c03b0f 100644
--- a/arch/ppc/syslib/mpc52xx_pic.c
+++ b/arch/ppc/syslib/mpc52xx_pic.c
@@ -20,7 +20,6 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/sched.h> 21#include <linux/sched.h>
22#include <linux/signal.h> 22#include <linux/signal.h>
23#include <linux/stddef.h>
24#include <linux/delay.h> 23#include <linux/delay.h>
25#include <linux/irq.h> 24#include <linux/irq.h>
26 25
diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
index ecfa2c0f8ba3..9f504fc7693e 100644
--- a/arch/ppc/syslib/mpc52xx_setup.c
+++ b/arch/ppc/syslib/mpc52xx_setup.c
@@ -16,6 +16,7 @@
16 */ 16 */
17 17
18 18
19#include <linux/spinlock.h>
19#include <asm/io.h> 20#include <asm/io.h>
20#include <asm/time.h> 21#include <asm/time.h>
21#include <asm/mpc52xx.h> 22#include <asm/mpc52xx.h>
@@ -275,3 +276,38 @@ int mpc52xx_match_psc_function(int psc_idx, const char *func)
275 276
276 return 0; 277 return 0;
277} 278}
279
280int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
281{
282 static spinlock_t lock = SPIN_LOCK_UNLOCKED;
283 struct mpc52xx_cdm __iomem *cdm;
284 unsigned long flags;
285 u16 mclken_div;
286 u16 __iomem *reg;
287 u32 mask;
288
289 cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
290 if (!cdm) {
291 printk(KERN_ERR __FILE__ ": Error mapping CDM\n");
292 return -ENODEV;
293 }
294
295 mclken_div = 0x8000 | (clkdiv & 0x1FF);
296 switch (psc_id) {
297 case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break;
298 case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break;
299 case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break;
300 case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break;
301 default:
302 return -ENODEV;
303 }
304
305 /* Set the rate and enable the clock */
306 spin_lock_irqsave(&lock, flags);
307 out_be16(reg, mclken_div);
308 out_be32(&cdm->clk_enables, in_be32(&cdm->clk_enables) | mask);
309 spin_unlock_irqrestore(&lock, flags);
310
311 iounmap(cdm);
312 return 0;
313}
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
deleted file mode 100644
index 5c4932ca8e9b..000000000000
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * MPC83xx Device descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h>
19#include <asm/mpc83xx.h>
20#include <asm/irq.h>
21#include <asm/ppc_sys.h>
22#include <asm/machdep.h>
23
24/* We use offsets for IORESOURCE_MEM since we do not know at compile time
25 * what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup
26 */
27
28struct gianfar_mdio_data mpc83xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc83xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc83xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = {
44 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
45};
46
47static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = {
48 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49};
50
51static struct plat_serial8250_port serial_platform_data[] = {
52 [0] = {
53 .mapbase = 0x4500,
54 .irq = MPC83xx_IRQ_UART1,
55 .iotype = UPIO_MEM,
56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
57 },
58 [1] = {
59 .mapbase = 0x4600,
60 .irq = MPC83xx_IRQ_UART2,
61 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
63 },
64 { },
65};
66
67struct platform_device ppc_sys_platform_devices[] = {
68 [MPC83xx_TSEC1] = {
69 .name = "fsl-gianfar",
70 .id = 1,
71 .dev.platform_data = &mpc83xx_tsec1_pdata,
72 .num_resources = 4,
73 .resource = (struct resource[]) {
74 {
75 .start = 0x24000,
76 .end = 0x24fff,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .name = "tx",
81 .start = MPC83xx_IRQ_TSEC1_TX,
82 .end = MPC83xx_IRQ_TSEC1_TX,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .name = "rx",
87 .start = MPC83xx_IRQ_TSEC1_RX,
88 .end = MPC83xx_IRQ_TSEC1_RX,
89 .flags = IORESOURCE_IRQ,
90 },
91 {
92 .name = "error",
93 .start = MPC83xx_IRQ_TSEC1_ERROR,
94 .end = MPC83xx_IRQ_TSEC1_ERROR,
95 .flags = IORESOURCE_IRQ,
96 },
97 },
98 },
99 [MPC83xx_TSEC2] = {
100 .name = "fsl-gianfar",
101 .id = 2,
102 .dev.platform_data = &mpc83xx_tsec2_pdata,
103 .num_resources = 4,
104 .resource = (struct resource[]) {
105 {
106 .start = 0x25000,
107 .end = 0x25fff,
108 .flags = IORESOURCE_MEM,
109 },
110 {
111 .name = "tx",
112 .start = MPC83xx_IRQ_TSEC2_TX,
113 .end = MPC83xx_IRQ_TSEC2_TX,
114 .flags = IORESOURCE_IRQ,
115 },
116 {
117 .name = "rx",
118 .start = MPC83xx_IRQ_TSEC2_RX,
119 .end = MPC83xx_IRQ_TSEC2_RX,
120 .flags = IORESOURCE_IRQ,
121 },
122 {
123 .name = "error",
124 .start = MPC83xx_IRQ_TSEC2_ERROR,
125 .end = MPC83xx_IRQ_TSEC2_ERROR,
126 .flags = IORESOURCE_IRQ,
127 },
128 },
129 },
130 [MPC83xx_IIC1] = {
131 .name = "fsl-i2c",
132 .id = 1,
133 .dev.platform_data = &mpc83xx_fsl_i2c1_pdata,
134 .num_resources = 2,
135 .resource = (struct resource[]) {
136 {
137 .start = 0x3000,
138 .end = 0x30ff,
139 .flags = IORESOURCE_MEM,
140 },
141 {
142 .start = MPC83xx_IRQ_IIC1,
143 .end = MPC83xx_IRQ_IIC1,
144 .flags = IORESOURCE_IRQ,
145 },
146 },
147 },
148 [MPC83xx_IIC2] = {
149 .name = "fsl-i2c",
150 .id = 2,
151 .dev.platform_data = &mpc83xx_fsl_i2c2_pdata,
152 .num_resources = 2,
153 .resource = (struct resource[]) {
154 {
155 .start = 0x3100,
156 .end = 0x31ff,
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .start = MPC83xx_IRQ_IIC2,
161 .end = MPC83xx_IRQ_IIC2,
162 .flags = IORESOURCE_IRQ,
163 },
164 },
165 },
166 [MPC83xx_DUART] = {
167 .name = "serial8250",
168 .id = PLAT8250_DEV_PLATFORM,
169 .dev.platform_data = serial_platform_data,
170 },
171 [MPC83xx_SEC2] = {
172 .name = "fsl-sec2",
173 .id = 1,
174 .num_resources = 2,
175 .resource = (struct resource[]) {
176 {
177 .start = 0x30000,
178 .end = 0x3ffff,
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .start = MPC83xx_IRQ_SEC2,
183 .end = MPC83xx_IRQ_SEC2,
184 .flags = IORESOURCE_IRQ,
185 },
186 },
187 },
188 [MPC83xx_USB2_DR] = {
189 .name = "fsl-ehci",
190 .id = 1,
191 .num_resources = 2,
192 .resource = (struct resource[]) {
193 {
194 .start = 0x23000,
195 .end = 0x23fff,
196 .flags = IORESOURCE_MEM,
197 },
198 {
199 .start = MPC83xx_IRQ_USB2_DR,
200 .end = MPC83xx_IRQ_USB2_DR,
201 .flags = IORESOURCE_IRQ,
202 },
203 },
204 },
205 [MPC83xx_USB2_MPH] = {
206 .name = "fsl-ehci",
207 .id = 2,
208 .num_resources = 2,
209 .resource = (struct resource[]) {
210 {
211 .start = 0x22000,
212 .end = 0x22fff,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .start = MPC83xx_IRQ_USB2_MPH,
217 .end = MPC83xx_IRQ_USB2_MPH,
218 .flags = IORESOURCE_IRQ,
219 },
220 },
221 },
222 [MPC83xx_MDIO] = {
223 .name = "fsl-gianfar_mdio",
224 .id = 0,
225 .dev.platform_data = &mpc83xx_mdio_pdata,
226 .num_resources = 1,
227 .resource = (struct resource[]) {
228 {
229 .start = 0x24520,
230 .end = 0x2453f,
231 .flags = IORESOURCE_MEM,
232 },
233 },
234 },
235};
236
237static int __init mach_mpc83xx_fixup(struct platform_device *pdev)
238{
239 ppc_sys_fixup_mem_resource(pdev, immrbar);
240 return 0;
241}
242
243static int __init mach_mpc83xx_init(void)
244{
245 if (ppc_md.progress)
246 ppc_md.progress("mach_mpc83xx_init:enter", 0);
247 ppc_sys_device_fixup = mach_mpc83xx_fixup;
248 return 0;
249}
250
251postcore_initcall(mach_mpc83xx_init);
diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c
deleted file mode 100644
index 0498ae7e01e3..000000000000
--- a/arch/ppc/syslib/mpc83xx_sys.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * MPC83xx System descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <asm/ppc_sys.h>
18
19struct ppc_sys_spec *cur_ppc_sys_spec;
20struct ppc_sys_spec ppc_sys_specs[] = {
21 {
22 .ppc_sys_name = "8349E",
23 .mask = 0xFFFF0000,
24 .value = 0x80500000,
25 .num_devices = 9,
26 .device_list = (enum ppc_sys_devices[])
27 {
28 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
29 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
30 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
31 },
32 },
33 {
34 .ppc_sys_name = "8349",
35 .mask = 0xFFFF0000,
36 .value = 0x80510000,
37 .num_devices = 8,
38 .device_list = (enum ppc_sys_devices[])
39 {
40 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
41 MPC83xx_IIC2, MPC83xx_DUART,
42 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
43 },
44 },
45 {
46 .ppc_sys_name = "8347E",
47 .mask = 0xFFFF0000,
48 .value = 0x80520000,
49 .num_devices = 9,
50 .device_list = (enum ppc_sys_devices[])
51 {
52 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
53 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
54 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
55 },
56 },
57 {
58 .ppc_sys_name = "8347",
59 .mask = 0xFFFF0000,
60 .value = 0x80530000,
61 .num_devices = 8,
62 .device_list = (enum ppc_sys_devices[])
63 {
64 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
65 MPC83xx_IIC2, MPC83xx_DUART,
66 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
67 },
68 },
69 {
70 .ppc_sys_name = "8347E",
71 .mask = 0xFFFF0000,
72 .value = 0x80540000,
73 .num_devices = 9,
74 .device_list = (enum ppc_sys_devices[])
75 {
76 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
77 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
78 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
79 },
80 },
81 {
82 .ppc_sys_name = "8347",
83 .mask = 0xFFFF0000,
84 .value = 0x80550000,
85 .num_devices = 8,
86 .device_list = (enum ppc_sys_devices[])
87 {
88 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
89 MPC83xx_IIC2, MPC83xx_DUART,
90 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
91 },
92 },
93 {
94 .ppc_sys_name = "8343E",
95 .mask = 0xFFFF0000,
96 .value = 0x80560000,
97 .num_devices = 8,
98 .device_list = (enum ppc_sys_devices[])
99 {
100 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
101 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
102 MPC83xx_USB2_DR, MPC83xx_MDIO
103 },
104 },
105 {
106 .ppc_sys_name = "8343",
107 .mask = 0xFFFF0000,
108 .value = 0x80570000,
109 .num_devices = 7,
110 .device_list = (enum ppc_sys_devices[])
111 {
112 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
113 MPC83xx_IIC2, MPC83xx_DUART,
114 MPC83xx_USB2_DR, MPC83xx_MDIO
115 },
116 },
117 { /* default match */
118 .ppc_sys_name = "",
119 .mask = 0x00000000,
120 .value = 0x00000000,
121 },
122};
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
deleted file mode 100644
index 325136e5aee0..000000000000
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ /dev/null
@@ -1,826 +0,0 @@
1/*
2 * MPC85xx Device descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h>
19#include <linux/fs_enet_pd.h>
20#include <asm/mpc85xx.h>
21#include <asm/irq.h>
22#include <asm/ppc_sys.h>
23#include <asm/cpm2.h>
24
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49};
50
51static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
57};
58
59static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
65};
66
67static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
73};
74
75static struct gianfar_platform_data mpc85xx_fec_pdata = {
76 .device_flags = 0,
77};
78
79static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
81};
82
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85};
86
87static struct fs_platform_info mpc85xx_fcc1_pdata = {
88 .fs_no = fsid_fcc1,
89 .cp_page = CPM_CR_FCC1_PAGE,
90 .cp_block = CPM_CR_FCC1_SBLOCK,
91
92 .rx_ring = 32,
93 .tx_ring = 32,
94 .rx_copybreak = 240,
95 .use_napi = 0,
96 .napi_weight = 17,
97
98 .clk_mask = CMX1_CLK_MASK,
99 .clk_route = CMX1_CLK_ROUTE,
100 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
101
102 .mem_offset = FCC1_MEM_OFFSET,
103};
104
105static struct fs_platform_info mpc85xx_fcc2_pdata = {
106 .fs_no = fsid_fcc2,
107 .cp_page = CPM_CR_FCC2_PAGE,
108 .cp_block = CPM_CR_FCC2_SBLOCK,
109
110 .rx_ring = 32,
111 .tx_ring = 32,
112 .rx_copybreak = 240,
113 .use_napi = 0,
114 .napi_weight = 17,
115
116 .clk_mask = CMX2_CLK_MASK,
117 .clk_route = CMX2_CLK_ROUTE,
118 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
119
120 .mem_offset = FCC2_MEM_OFFSET,
121};
122
123static struct fs_platform_info mpc85xx_fcc3_pdata = {
124 .fs_no = fsid_fcc3,
125 .cp_page = CPM_CR_FCC3_PAGE,
126 .cp_block = CPM_CR_FCC3_SBLOCK,
127
128 .rx_ring = 32,
129 .tx_ring = 32,
130 .rx_copybreak = 240,
131 .use_napi = 0,
132 .napi_weight = 17,
133
134 .clk_mask = CMX3_CLK_MASK,
135 .clk_route = CMX3_CLK_ROUTE,
136 .clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
137
138 .mem_offset = FCC3_MEM_OFFSET,
139};
140
141static struct plat_serial8250_port serial_platform_data[] = {
142 [0] = {
143 .mapbase = 0x4500,
144 .irq = MPC85xx_IRQ_DUART,
145 .iotype = UPIO_MEM,
146 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
147 },
148 [1] = {
149 .mapbase = 0x4600,
150 .irq = MPC85xx_IRQ_DUART,
151 .iotype = UPIO_MEM,
152 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
153 },
154 { },
155};
156
157struct platform_device ppc_sys_platform_devices[] = {
158 [MPC85xx_TSEC1] = {
159 .name = "fsl-gianfar",
160 .id = 1,
161 .dev.platform_data = &mpc85xx_tsec1_pdata,
162 .num_resources = 4,
163 .resource = (struct resource[]) {
164 {
165 .start = MPC85xx_ENET1_OFFSET,
166 .end = MPC85xx_ENET1_OFFSET +
167 MPC85xx_ENET1_SIZE - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .name = "tx",
172 .start = MPC85xx_IRQ_TSEC1_TX,
173 .end = MPC85xx_IRQ_TSEC1_TX,
174 .flags = IORESOURCE_IRQ,
175 },
176 {
177 .name = "rx",
178 .start = MPC85xx_IRQ_TSEC1_RX,
179 .end = MPC85xx_IRQ_TSEC1_RX,
180 .flags = IORESOURCE_IRQ,
181 },
182 {
183 .name = "error",
184 .start = MPC85xx_IRQ_TSEC1_ERROR,
185 .end = MPC85xx_IRQ_TSEC1_ERROR,
186 .flags = IORESOURCE_IRQ,
187 },
188 },
189 },
190 [MPC85xx_TSEC2] = {
191 .name = "fsl-gianfar",
192 .id = 2,
193 .dev.platform_data = &mpc85xx_tsec2_pdata,
194 .num_resources = 4,
195 .resource = (struct resource[]) {
196 {
197 .start = MPC85xx_ENET2_OFFSET,
198 .end = MPC85xx_ENET2_OFFSET +
199 MPC85xx_ENET2_SIZE - 1,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .name = "tx",
204 .start = MPC85xx_IRQ_TSEC2_TX,
205 .end = MPC85xx_IRQ_TSEC2_TX,
206 .flags = IORESOURCE_IRQ,
207 },
208 {
209 .name = "rx",
210 .start = MPC85xx_IRQ_TSEC2_RX,
211 .end = MPC85xx_IRQ_TSEC2_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "error",
216 .start = MPC85xx_IRQ_TSEC2_ERROR,
217 .end = MPC85xx_IRQ_TSEC2_ERROR,
218 .flags = IORESOURCE_IRQ,
219 },
220 },
221 },
222 [MPC85xx_FEC] = {
223 .name = "fsl-gianfar",
224 .id = 3,
225 .dev.platform_data = &mpc85xx_fec_pdata,
226 .num_resources = 2,
227 .resource = (struct resource[]) {
228 {
229 .start = MPC85xx_ENET3_OFFSET,
230 .end = MPC85xx_ENET3_OFFSET +
231 MPC85xx_ENET3_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233
234 },
235 {
236 .start = MPC85xx_IRQ_FEC,
237 .end = MPC85xx_IRQ_FEC,
238 .flags = IORESOURCE_IRQ,
239 },
240 },
241 },
242 [MPC85xx_IIC1] = {
243 .name = "fsl-i2c",
244 .id = 1,
245 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
246 .num_resources = 2,
247 .resource = (struct resource[]) {
248 {
249 .start = MPC85xx_IIC1_OFFSET,
250 .end = MPC85xx_IIC1_OFFSET +
251 MPC85xx_IIC1_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 {
255 .start = MPC85xx_IRQ_IIC1,
256 .end = MPC85xx_IRQ_IIC1,
257 .flags = IORESOURCE_IRQ,
258 },
259 },
260 },
261 [MPC85xx_DMA0] = {
262 .name = "fsl-dma",
263 .id = 0,
264 .num_resources = 2,
265 .resource = (struct resource[]) {
266 {
267 .start = MPC85xx_DMA0_OFFSET,
268 .end = MPC85xx_DMA0_OFFSET +
269 MPC85xx_DMA0_SIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = MPC85xx_IRQ_DMA0,
274 .end = MPC85xx_IRQ_DMA0,
275 .flags = IORESOURCE_IRQ,
276 },
277 },
278 },
279 [MPC85xx_DMA1] = {
280 .name = "fsl-dma",
281 .id = 1,
282 .num_resources = 2,
283 .resource = (struct resource[]) {
284 {
285 .start = MPC85xx_DMA1_OFFSET,
286 .end = MPC85xx_DMA1_OFFSET +
287 MPC85xx_DMA1_SIZE - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = MPC85xx_IRQ_DMA1,
292 .end = MPC85xx_IRQ_DMA1,
293 .flags = IORESOURCE_IRQ,
294 },
295 },
296 },
297 [MPC85xx_DMA2] = {
298 .name = "fsl-dma",
299 .id = 2,
300 .num_resources = 2,
301 .resource = (struct resource[]) {
302 {
303 .start = MPC85xx_DMA2_OFFSET,
304 .end = MPC85xx_DMA2_OFFSET +
305 MPC85xx_DMA2_SIZE - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = MPC85xx_IRQ_DMA2,
310 .end = MPC85xx_IRQ_DMA2,
311 .flags = IORESOURCE_IRQ,
312 },
313 },
314 },
315 [MPC85xx_DMA3] = {
316 .name = "fsl-dma",
317 .id = 3,
318 .num_resources = 2,
319 .resource = (struct resource[]) {
320 {
321 .start = MPC85xx_DMA3_OFFSET,
322 .end = MPC85xx_DMA3_OFFSET +
323 MPC85xx_DMA3_SIZE - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 {
327 .start = MPC85xx_IRQ_DMA3,
328 .end = MPC85xx_IRQ_DMA3,
329 .flags = IORESOURCE_IRQ,
330 },
331 },
332 },
333 [MPC85xx_DUART] = {
334 .name = "serial8250",
335 .id = PLAT8250_DEV_PLATFORM,
336 .dev.platform_data = serial_platform_data,
337 },
338 [MPC85xx_PERFMON] = {
339 .name = "fsl-perfmon",
340 .id = 1,
341 .num_resources = 2,
342 .resource = (struct resource[]) {
343 {
344 .start = MPC85xx_PERFMON_OFFSET,
345 .end = MPC85xx_PERFMON_OFFSET +
346 MPC85xx_PERFMON_SIZE - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 {
350 .start = MPC85xx_IRQ_PERFMON,
351 .end = MPC85xx_IRQ_PERFMON,
352 .flags = IORESOURCE_IRQ,
353 },
354 },
355 },
356 [MPC85xx_SEC2] = {
357 .name = "fsl-sec2",
358 .id = 1,
359 .num_resources = 2,
360 .resource = (struct resource[]) {
361 {
362 .start = MPC85xx_SEC2_OFFSET,
363 .end = MPC85xx_SEC2_OFFSET +
364 MPC85xx_SEC2_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = MPC85xx_IRQ_SEC2,
369 .end = MPC85xx_IRQ_SEC2,
370 .flags = IORESOURCE_IRQ,
371 },
372 },
373 },
374 [MPC85xx_CPM_FCC1] = {
375 .name = "fsl-cpm-fcc",
376 .id = 1,
377 .num_resources = 4,
378 .dev.platform_data = &mpc85xx_fcc1_pdata,
379 .resource = (struct resource[]) {
380 {
381 .name = "fcc_regs",
382 .start = 0x91300,
383 .end = 0x9131F,
384 .flags = IORESOURCE_MEM,
385 },
386 {
387 .name = "fcc_regs_c",
388 .start = 0x91380,
389 .end = 0x9139F,
390 .flags = IORESOURCE_MEM,
391 },
392 {
393 .name = "fcc_pram",
394 .start = 0x88400,
395 .end = 0x884ff,
396 .flags = IORESOURCE_MEM,
397 },
398 {
399 .start = SIU_INT_FCC1,
400 .end = SIU_INT_FCC1,
401 .flags = IORESOURCE_IRQ,
402 },
403 },
404 },
405 [MPC85xx_CPM_FCC2] = {
406 .name = "fsl-cpm-fcc",
407 .id = 2,
408 .num_resources = 4,
409 .dev.platform_data = &mpc85xx_fcc2_pdata,
410 .resource = (struct resource[]) {
411 {
412 .name = "fcc_regs",
413 .start = 0x91320,
414 .end = 0x9133F,
415 .flags = IORESOURCE_MEM,
416 },
417 {
418 .name = "fcc_regs_c",
419 .start = 0x913A0,
420 .end = 0x913CF,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "fcc_pram",
425 .start = 0x88500,
426 .end = 0x885ff,
427 .flags = IORESOURCE_MEM,
428 },
429 {
430 .start = SIU_INT_FCC2,
431 .end = SIU_INT_FCC2,
432 .flags = IORESOURCE_IRQ,
433 },
434 },
435 },
436 [MPC85xx_CPM_FCC3] = {
437 .name = "fsl-cpm-fcc",
438 .id = 3,
439 .num_resources = 4,
440 .dev.platform_data = &mpc85xx_fcc3_pdata,
441 .resource = (struct resource[]) {
442 {
443 .name = "fcc_regs",
444 .start = 0x91340,
445 .end = 0x9135F,
446 .flags = IORESOURCE_MEM,
447 },
448 {
449 .name = "fcc_regs_c",
450 .start = 0x913D0,
451 .end = 0x913FF,
452 .flags = IORESOURCE_MEM,
453 },
454 {
455 .name = "fcc_pram",
456 .start = 0x88600,
457 .end = 0x886ff,
458 .flags = IORESOURCE_MEM,
459 },
460 {
461 .start = SIU_INT_FCC3,
462 .end = SIU_INT_FCC3,
463 .flags = IORESOURCE_IRQ,
464 },
465 },
466 },
467 [MPC85xx_CPM_I2C] = {
468 .name = "fsl-cpm-i2c",
469 .id = 1,
470 .num_resources = 2,
471 .resource = (struct resource[]) {
472 {
473 .start = 0x91860,
474 .end = 0x918BF,
475 .flags = IORESOURCE_MEM,
476 },
477 {
478 .start = SIU_INT_I2C,
479 .end = SIU_INT_I2C,
480 .flags = IORESOURCE_IRQ,
481 },
482 },
483 },
484 [MPC85xx_CPM_SCC1] = {
485 .name = "fsl-cpm-scc",
486 .id = 1,
487 .num_resources = 2,
488 .resource = (struct resource[]) {
489 {
490 .start = 0x91A00,
491 .end = 0x91A1F,
492 .flags = IORESOURCE_MEM,
493 },
494 {
495 .start = SIU_INT_SCC1,
496 .end = SIU_INT_SCC1,
497 .flags = IORESOURCE_IRQ,
498 },
499 },
500 },
501 [MPC85xx_CPM_SCC2] = {
502 .name = "fsl-cpm-scc",
503 .id = 2,
504 .num_resources = 2,
505 .resource = (struct resource[]) {
506 {
507 .start = 0x91A20,
508 .end = 0x91A3F,
509 .flags = IORESOURCE_MEM,
510 },
511 {
512 .start = SIU_INT_SCC2,
513 .end = SIU_INT_SCC2,
514 .flags = IORESOURCE_IRQ,
515 },
516 },
517 },
518 [MPC85xx_CPM_SCC3] = {
519 .name = "fsl-cpm-scc",
520 .id = 3,
521 .num_resources = 2,
522 .resource = (struct resource[]) {
523 {
524 .start = 0x91A40,
525 .end = 0x91A5F,
526 .flags = IORESOURCE_MEM,
527 },
528 {
529 .start = SIU_INT_SCC3,
530 .end = SIU_INT_SCC3,
531 .flags = IORESOURCE_IRQ,
532 },
533 },
534 },
535 [MPC85xx_CPM_SCC4] = {
536 .name = "fsl-cpm-scc",
537 .id = 4,
538 .num_resources = 2,
539 .resource = (struct resource[]) {
540 {
541 .start = 0x91A60,
542 .end = 0x91A7F,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 .start = SIU_INT_SCC4,
547 .end = SIU_INT_SCC4,
548 .flags = IORESOURCE_IRQ,
549 },
550 },
551 },
552 [MPC85xx_CPM_SPI] = {
553 .name = "fsl-cpm-spi",
554 .id = 1,
555 .num_resources = 2,
556 .resource = (struct resource[]) {
557 {
558 .start = 0x91AA0,
559 .end = 0x91AFF,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 .start = SIU_INT_SPI,
564 .end = SIU_INT_SPI,
565 .flags = IORESOURCE_IRQ,
566 },
567 },
568 },
569 [MPC85xx_CPM_MCC1] = {
570 .name = "fsl-cpm-mcc",
571 .id = 1,
572 .num_resources = 2,
573 .resource = (struct resource[]) {
574 {
575 .start = 0x91B30,
576 .end = 0x91B3F,
577 .flags = IORESOURCE_MEM,
578 },
579 {
580 .start = SIU_INT_MCC1,
581 .end = SIU_INT_MCC1,
582 .flags = IORESOURCE_IRQ,
583 },
584 },
585 },
586 [MPC85xx_CPM_MCC2] = {
587 .name = "fsl-cpm-mcc",
588 .id = 2,
589 .num_resources = 2,
590 .resource = (struct resource[]) {
591 {
592 .start = 0x91B50,
593 .end = 0x91B5F,
594 .flags = IORESOURCE_MEM,
595 },
596 {
597 .start = SIU_INT_MCC2,
598 .end = SIU_INT_MCC2,
599 .flags = IORESOURCE_IRQ,
600 },
601 },
602 },
603 [MPC85xx_CPM_SMC1] = {
604 .name = "fsl-cpm-smc",
605 .id = 1,
606 .num_resources = 2,
607 .resource = (struct resource[]) {
608 {
609 .start = 0x91A80,
610 .end = 0x91A8F,
611 .flags = IORESOURCE_MEM,
612 },
613 {
614 .start = SIU_INT_SMC1,
615 .end = SIU_INT_SMC1,
616 .flags = IORESOURCE_IRQ,
617 },
618 },
619 },
620 [MPC85xx_CPM_SMC2] = {
621 .name = "fsl-cpm-smc",
622 .id = 2,
623 .num_resources = 2,
624 .resource = (struct resource[]) {
625 {
626 .start = 0x91A90,
627 .end = 0x91A9F,
628 .flags = IORESOURCE_MEM,
629 },
630 {
631 .start = SIU_INT_SMC2,
632 .end = SIU_INT_SMC2,
633 .flags = IORESOURCE_IRQ,
634 },
635 },
636 },
637 [MPC85xx_CPM_USB] = {
638 .name = "fsl-cpm-usb",
639 .id = 2,
640 .num_resources = 2,
641 .resource = (struct resource[]) {
642 {
643 .start = 0x91B60,
644 .end = 0x91B7F,
645 .flags = IORESOURCE_MEM,
646 },
647 {
648 .start = SIU_INT_USB,
649 .end = SIU_INT_USB,
650 .flags = IORESOURCE_IRQ,
651 },
652 },
653 },
654 [MPC85xx_eTSEC1] = {
655 .name = "fsl-gianfar",
656 .id = 1,
657 .dev.platform_data = &mpc85xx_etsec1_pdata,
658 .num_resources = 4,
659 .resource = (struct resource[]) {
660 {
661 .start = MPC85xx_ENET1_OFFSET,
662 .end = MPC85xx_ENET1_OFFSET +
663 MPC85xx_ENET1_SIZE - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 {
667 .name = "tx",
668 .start = MPC85xx_IRQ_TSEC1_TX,
669 .end = MPC85xx_IRQ_TSEC1_TX,
670 .flags = IORESOURCE_IRQ,
671 },
672 {
673 .name = "rx",
674 .start = MPC85xx_IRQ_TSEC1_RX,
675 .end = MPC85xx_IRQ_TSEC1_RX,
676 .flags = IORESOURCE_IRQ,
677 },
678 {
679 .name = "error",
680 .start = MPC85xx_IRQ_TSEC1_ERROR,
681 .end = MPC85xx_IRQ_TSEC1_ERROR,
682 .flags = IORESOURCE_IRQ,
683 },
684 },
685 },
686 [MPC85xx_eTSEC2] = {
687 .name = "fsl-gianfar",
688 .id = 2,
689 .dev.platform_data = &mpc85xx_etsec2_pdata,
690 .num_resources = 4,
691 .resource = (struct resource[]) {
692 {
693 .start = MPC85xx_ENET2_OFFSET,
694 .end = MPC85xx_ENET2_OFFSET +
695 MPC85xx_ENET2_SIZE - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 {
699 .name = "tx",
700 .start = MPC85xx_IRQ_TSEC2_TX,
701 .end = MPC85xx_IRQ_TSEC2_TX,
702 .flags = IORESOURCE_IRQ,
703 },
704 {
705 .name = "rx",
706 .start = MPC85xx_IRQ_TSEC2_RX,
707 .end = MPC85xx_IRQ_TSEC2_RX,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .name = "error",
712 .start = MPC85xx_IRQ_TSEC2_ERROR,
713 .end = MPC85xx_IRQ_TSEC2_ERROR,
714 .flags = IORESOURCE_IRQ,
715 },
716 },
717 },
718 [MPC85xx_eTSEC3] = {
719 .name = "fsl-gianfar",
720 .id = 3,
721 .dev.platform_data = &mpc85xx_etsec3_pdata,
722 .num_resources = 4,
723 .resource = (struct resource[]) {
724 {
725 .start = MPC85xx_ENET3_OFFSET,
726 .end = MPC85xx_ENET3_OFFSET +
727 MPC85xx_ENET3_SIZE - 1,
728 .flags = IORESOURCE_MEM,
729 },
730 {
731 .name = "tx",
732 .start = MPC85xx_IRQ_TSEC3_TX,
733 .end = MPC85xx_IRQ_TSEC3_TX,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .name = "rx",
738 .start = MPC85xx_IRQ_TSEC3_RX,
739 .end = MPC85xx_IRQ_TSEC3_RX,
740 .flags = IORESOURCE_IRQ,
741 },
742 {
743 .name = "error",
744 .start = MPC85xx_IRQ_TSEC3_ERROR,
745 .end = MPC85xx_IRQ_TSEC3_ERROR,
746 .flags = IORESOURCE_IRQ,
747 },
748 },
749 },
750 [MPC85xx_eTSEC4] = {
751 .name = "fsl-gianfar",
752 .id = 4,
753 .dev.platform_data = &mpc85xx_etsec4_pdata,
754 .num_resources = 4,
755 .resource = (struct resource[]) {
756 {
757 .start = 0x27000,
758 .end = 0x27fff,
759 .flags = IORESOURCE_MEM,
760 },
761 {
762 .name = "tx",
763 .start = MPC85xx_IRQ_TSEC4_TX,
764 .end = MPC85xx_IRQ_TSEC4_TX,
765 .flags = IORESOURCE_IRQ,
766 },
767 {
768 .name = "rx",
769 .start = MPC85xx_IRQ_TSEC4_RX,
770 .end = MPC85xx_IRQ_TSEC4_RX,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .name = "error",
775 .start = MPC85xx_IRQ_TSEC4_ERROR,
776 .end = MPC85xx_IRQ_TSEC4_ERROR,
777 .flags = IORESOURCE_IRQ,
778 },
779 },
780 },
781 [MPC85xx_IIC2] = {
782 .name = "fsl-i2c",
783 .id = 2,
784 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
785 .num_resources = 2,
786 .resource = (struct resource[]) {
787 {
788 .start = 0x03100,
789 .end = 0x031ff,
790 .flags = IORESOURCE_MEM,
791 },
792 {
793 .start = MPC85xx_IRQ_IIC1,
794 .end = MPC85xx_IRQ_IIC1,
795 .flags = IORESOURCE_IRQ,
796 },
797 },
798 },
799 [MPC85xx_MDIO] = {
800 .name = "fsl-gianfar_mdio",
801 .id = 0,
802 .dev.platform_data = &mpc85xx_mdio_pdata,
803 .num_resources = 1,
804 .resource = (struct resource[]) {
805 {
806 .start = 0x24520,
807 .end = 0x2453f,
808 .flags = IORESOURCE_MEM,
809 },
810 },
811 },
812};
813
814static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
815{
816 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
817 return 0;
818}
819
820static int __init mach_mpc85xx_init(void)
821{
822 ppc_sys_device_fixup = mach_mpc85xx_fixup;
823 return 0;
824}
825
826postcore_initcall(mach_mpc85xx_init);
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
deleted file mode 100644
index d96a93dbcb5a..000000000000
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ /dev/null
@@ -1,233 +0,0 @@
1/*
2 * MPC85xx System descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <asm/ppc_sys.h>
18
19struct ppc_sys_spec *cur_ppc_sys_spec;
20struct ppc_sys_spec ppc_sys_specs[] = {
21 {
22 .ppc_sys_name = "8540",
23 .mask = 0xFFFF0000,
24 .value = 0x80300000,
25 .num_devices = 11,
26 .device_list = (enum ppc_sys_devices[])
27 {
28 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1,
29 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
30 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_MDIO,
31 },
32 },
33 {
34 .ppc_sys_name = "8560",
35 .mask = 0xFFFF0000,
36 .value = 0x80700000,
37 .num_devices = 20,
38 .device_list = (enum ppc_sys_devices[])
39 {
40 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
41 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
42 MPC85xx_PERFMON,
43 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
44 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4,
45 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
46 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, MPC85xx_MDIO,
47 },
48 },
49 {
50 .ppc_sys_name = "8541",
51 .mask = 0xFFFF0000,
52 .value = 0x80720000,
53 .num_devices = 14,
54 .device_list = (enum ppc_sys_devices[])
55 {
56 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
57 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
58 MPC85xx_PERFMON, MPC85xx_DUART,
59 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
60 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
61 MPC85xx_MDIO,
62 },
63 },
64 {
65 .ppc_sys_name = "8541E",
66 .mask = 0xFFFF0000,
67 .value = 0x807A0000,
68 .num_devices = 15,
69 .device_list = (enum ppc_sys_devices[])
70 {
71 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
72 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
73 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
74 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
75 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
76 MPC85xx_MDIO,
77 },
78 },
79 {
80 .ppc_sys_name = "8555",
81 .mask = 0xFFFF0000,
82 .value = 0x80710000,
83 .num_devices = 20,
84 .device_list = (enum ppc_sys_devices[])
85 {
86 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
87 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
88 MPC85xx_PERFMON, MPC85xx_DUART,
89 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
90 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
91 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
92 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
93 MPC85xx_CPM_USB,
94 MPC85xx_MDIO,
95 },
96 },
97 {
98 .ppc_sys_name = "8555E",
99 .mask = 0xFFFF0000,
100 .value = 0x80790000,
101 .num_devices = 21,
102 .device_list = (enum ppc_sys_devices[])
103 {
104 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
105 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
106 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
107 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
108 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
109 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
110 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
111 MPC85xx_CPM_USB,
112 MPC85xx_MDIO,
113 },
114 },
115 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
116 {
117 .ppc_sys_name = "8548E",
118 .mask = 0xFFFF00F0,
119 .value = 0x80390010,
120 .num_devices = 14,
121 .device_list = (enum ppc_sys_devices[])
122 {
123 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
124 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
125 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
126 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
127 MPC85xx_MDIO,
128 },
129 },
130 {
131 .ppc_sys_name = "8548",
132 .mask = 0xFFFF00F0,
133 .value = 0x80310010,
134 .num_devices = 13,
135 .device_list = (enum ppc_sys_devices[])
136 {
137 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
138 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
139 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
140 MPC85xx_PERFMON, MPC85xx_DUART,
141 MPC85xx_MDIO,
142 },
143 },
144 {
145 .ppc_sys_name = "8547E",
146 .mask = 0xFFFF00F0,
147 .value = 0x80390010,
148 .num_devices = 14,
149 .device_list = (enum ppc_sys_devices[])
150 {
151 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
152 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
153 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
154 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
155 MPC85xx_MDIO,
156 },
157 },
158 {
159 .ppc_sys_name = "8547",
160 .mask = 0xFFFF00F0,
161 .value = 0x80310010,
162 .num_devices = 13,
163 .device_list = (enum ppc_sys_devices[])
164 {
165 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
166 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
167 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
168 MPC85xx_PERFMON, MPC85xx_DUART,
169 MPC85xx_MDIO,
170 },
171 },
172 {
173 .ppc_sys_name = "8545E",
174 .mask = 0xFFFF00F0,
175 .value = 0x80390010,
176 .num_devices = 12,
177 .device_list = (enum ppc_sys_devices[])
178 {
179 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
180 MPC85xx_IIC1, MPC85xx_IIC2,
181 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
182 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
183 MPC85xx_MDIO,
184 },
185 },
186 {
187 .ppc_sys_name = "8545",
188 .mask = 0xFFFF00F0,
189 .value = 0x80310010,
190 .num_devices = 11,
191 .device_list = (enum ppc_sys_devices[])
192 {
193 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
194 MPC85xx_IIC1, MPC85xx_IIC2,
195 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
196 MPC85xx_PERFMON, MPC85xx_DUART,
197 MPC85xx_MDIO,
198 },
199 },
200 {
201 .ppc_sys_name = "8543E",
202 .mask = 0xFFFF00F0,
203 .value = 0x803A0010,
204 .num_devices = 12,
205 .device_list = (enum ppc_sys_devices[])
206 {
207 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
208 MPC85xx_IIC1, MPC85xx_IIC2,
209 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
210 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
211 MPC85xx_MDIO,
212 },
213 },
214 {
215 .ppc_sys_name = "8543",
216 .mask = 0xFFFF00F0,
217 .value = 0x80320010,
218 .num_devices = 11,
219 .device_list = (enum ppc_sys_devices[])
220 {
221 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
222 MPC85xx_IIC1, MPC85xx_IIC2,
223 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
224 MPC85xx_PERFMON, MPC85xx_DUART,
225 MPC85xx_MDIO,
226 },
227 },
228 { /* default match */
229 .ppc_sys_name = "",
230 .mask = 0x00000000,
231 .value = 0x00000000,
232 },
233};
diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c
index c05ac87ece4c..80804eee5795 100644
--- a/arch/ppc/syslib/mpc8xx_devices.c
+++ b/arch/ppc/syslib/mpc8xx_devices.c
@@ -16,7 +16,7 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
18#include <linux/mii.h> 18#include <linux/mii.h>
19#include <asm/commproc.h> 19#include <asm/cpm1.h>
20#include <asm/mpc8xx.h> 20#include <asm/mpc8xx.h>
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/ppc_sys.h> 22#include <asm/ppc_sys.h>
diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c
index 4b7a3338e122..2dd2dc5cd404 100644
--- a/arch/ppc/syslib/mv64360_pic.c
+++ b/arch/ppc/syslib/mv64360_pic.c
@@ -36,7 +36,6 @@
36#include <linux/init.h> 36#include <linux/init.h>
37#include <linux/sched.h> 37#include <linux/sched.h>
38#include <linux/signal.h> 38#include <linux/signal.h>
39#include <linux/stddef.h>
40#include <linux/delay.h> 39#include <linux/delay.h>
41#include <linux/irq.h> 40#include <linux/irq.h>
42#include <linux/interrupt.h> 41#include <linux/interrupt.h>
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index 3f5be2c5ce99..ac80370ed2f7 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -20,7 +20,7 @@
20 * of peripherals are found on embedded SoC (System On a Chip) 20 * of peripherals are found on embedded SoC (System On a Chip)
21 * processors or highly integrated system controllers that have 21 * processors or highly integrated system controllers that have
22 * a host bridge and many peripherals. Common examples where 22 * a host bridge and many peripherals. Common examples where
23 * this is already used include the PPC4xx, PPC85xx, MPC52xx, 23 * this is already used include the PPC4xx, MPC52xx,
24 * and MV64xxx parts. 24 * and MV64xxx parts.
25 * 25 *
26 * This subsystem creates a standard OCP bus type within the 26 * This subsystem creates a standard OCP bus type within the
@@ -376,7 +376,7 @@ ocp_remove_one_device(unsigned int vendor, unsigned int function, int index)
376 376
377 down_write(&ocp_devices_sem); 377 down_write(&ocp_devices_sem);
378 dev = __ocp_find_device(vendor, function, index); 378 dev = __ocp_find_device(vendor, function, index);
379 list_del((struct list_head *)dev); 379 list_del(&dev->link);
380 up_write(&ocp_devices_sem); 380 up_write(&ocp_devices_sem);
381 381
382 DBG(("ocp: ocp_remove_one_device(vendor: %x, function: %x, index: %d)... done.\n", vendor, function, index)); 382 DBG(("ocp: ocp_remove_one_device(vendor: %x, function: %x, index: %d)... done.\n", vendor, function, index));
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index da36522d327a..67dffe27b5c3 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -24,7 +24,7 @@
24 24
25#include "open_pic_defs.h" 25#include "open_pic_defs.h"
26 26
27#if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx) 27#if defined(CONFIG_PRPMC800)
28#define OPENPIC_BIG_ENDIAN 28#define OPENPIC_BIG_ENDIAN
29#endif 29#endif
30 30
diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h
deleted file mode 100644
index ec691640f6be..000000000000
--- a/arch/ppc/syslib/ppc83xx_pci.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* Created by Tony Li <tony.li@freescale.com>
2 * Copyright (c) 2005 freescale semiconductor
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
20#define __PPC_SYSLIB_PPC83XX_PCI_H
21
22typedef struct immr_clk {
23 u32 spmr; /* system PLL mode Register */
24 u32 occr; /* output clock control Register */
25 u32 sccr; /* system clock control Register */
26 u8 res0[0xF4];
27} immr_clk_t;
28
29/*
30 * Sequencer
31 */
32typedef struct immr_ios {
33 u32 potar0;
34 u8 res0[4];
35 u32 pobar0;
36 u8 res1[4];
37 u32 pocmr0;
38 u8 res2[4];
39 u32 potar1;
40 u8 res3[4];
41 u32 pobar1;
42 u8 res4[4];
43 u32 pocmr1;
44 u8 res5[4];
45 u32 potar2;
46 u8 res6[4];
47 u32 pobar2;
48 u8 res7[4];
49 u32 pocmr2;
50 u8 res8[4];
51 u32 potar3;
52 u8 res9[4];
53 u32 pobar3;
54 u8 res10[4];
55 u32 pocmr3;
56 u8 res11[4];
57 u32 potar4;
58 u8 res12[4];
59 u32 pobar4;
60 u8 res13[4];
61 u32 pocmr4;
62 u8 res14[4];
63 u32 potar5;
64 u8 res15[4];
65 u32 pobar5;
66 u8 res16[4];
67 u32 pocmr5;
68 u8 res17[4];
69 u8 res18[0x60];
70 u32 pmcr;
71 u8 res19[4];
72 u32 dtcr;
73 u8 res20[4];
74} immr_ios_t;
75#define POTAR_TA_MASK 0x000fffff
76#define POBAR_BA_MASK 0x000fffff
77#define POCMR_EN 0x80000000
78#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
79#define POCMR_SE 0x20000000 /* streaming enable */
80#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
81#define POCMR_CM_MASK 0x000fffff
82
83/*
84 * PCI Controller Control and Status Registers
85 */
86typedef struct immr_pcictrl {
87 u32 esr;
88 u32 ecdr;
89 u32 eer;
90 u32 eatcr;
91 u32 eacr;
92 u32 eeacr;
93 u32 edlcr;
94 u32 edhcr;
95 u32 gcr;
96 u32 ecr;
97 u32 gsr;
98 u8 res0[12];
99 u32 pitar2;
100 u8 res1[4];
101 u32 pibar2;
102 u32 piebar2;
103 u32 piwar2;
104 u8 res2[4];
105 u32 pitar1;
106 u8 res3[4];
107 u32 pibar1;
108 u32 piebar1;
109 u32 piwar1;
110 u8 res4[4];
111 u32 pitar0;
112 u8 res5[4];
113 u32 pibar0;
114 u8 res6[4];
115 u32 piwar0;
116 u8 res7[132];
117} immr_pcictrl_t;
118#define PITAR_TA_MASK 0x000fffff
119#define PIBAR_MASK 0xffffffff
120#define PIEBAR_EBA_MASK 0x000fffff
121#define PIWAR_EN 0x80000000
122#define PIWAR_PF 0x20000000
123#define PIWAR_RTT_MASK 0x000f0000
124#define PIWAR_RTT_NO_SNOOP 0x00040000
125#define PIWAR_RTT_SNOOP 0x00050000
126#define PIWAR_WTT_MASK 0x0000f000
127#define PIWAR_WTT_NO_SNOOP 0x00004000
128#define PIWAR_WTT_SNOOP 0x00005000
129#define PIWAR_IWS_MASK 0x0000003F
130#define PIWAR_IWS_4K 0x0000000B
131#define PIWAR_IWS_8K 0x0000000C
132#define PIWAR_IWS_16K 0x0000000D
133#define PIWAR_IWS_32K 0x0000000E
134#define PIWAR_IWS_64K 0x0000000F
135#define PIWAR_IWS_128K 0x00000010
136#define PIWAR_IWS_256K 0x00000011
137#define PIWAR_IWS_512K 0x00000012
138#define PIWAR_IWS_1M 0x00000013
139#define PIWAR_IWS_2M 0x00000014
140#define PIWAR_IWS_4M 0x00000015
141#define PIWAR_IWS_8M 0x00000016
142#define PIWAR_IWS_16M 0x00000017
143#define PIWAR_IWS_32M 0x00000018
144#define PIWAR_IWS_64M 0x00000019
145#define PIWAR_IWS_128M 0x0000001A
146#define PIWAR_IWS_256M 0x0000001B
147#define PIWAR_IWS_512M 0x0000001C
148#define PIWAR_IWS_1G 0x0000001D
149#define PIWAR_IWS_2G 0x0000001E
150
151#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
deleted file mode 100644
index ec466db52114..000000000000
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ /dev/null
@@ -1,411 +0,0 @@
1/*
2 * MPC83XX common board code
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Added PCI support -- Tony Li <tony.li@freescale.com>
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/serial.h>
30#include <linux/tty.h> /* for linux/serial_core.h */
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/time.h>
35#include <asm/mpc83xx.h>
36#include <asm/mmu.h>
37#include <asm/ppc_sys.h>
38#include <asm/kgdb.h>
39#include <asm/delay.h>
40#include <asm/machdep.h>
41
42#include <syslib/ppc83xx_setup.h>
43#if defined(CONFIG_PCI)
44#include <asm/delay.h>
45#include <syslib/ppc83xx_pci.h>
46#endif
47
48phys_addr_t immrbar;
49
50/* Return the amount of memory */
51unsigned long __init
52mpc83xx_find_end_of_memory(void)
53{
54 bd_t *binfo;
55
56 binfo = (bd_t *) __res;
57
58 return binfo->bi_memsize;
59}
60
61long __init
62mpc83xx_time_init(void)
63{
64#define SPCR_OFFS 0x00000110
65#define SPCR_TBEN 0x00400000
66
67 bd_t *binfo = (bd_t *)__res;
68 u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
69
70 *spcr |= SPCR_TBEN;
71
72 iounmap(spcr);
73
74 return 0;
75}
76
77/* The decrementer counts at the system (internal) clock freq divided by 4 */
78void __init
79mpc83xx_calibrate_decr(void)
80{
81 bd_t *binfo = (bd_t *) __res;
82 unsigned int freq, divisor;
83
84 freq = binfo->bi_busfreq;
85 divisor = 4;
86 tb_ticks_per_jiffy = freq / HZ / divisor;
87 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
88}
89
90#ifdef CONFIG_SERIAL_8250
91void __init
92mpc83xx_early_serial_map(void)
93{
94#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
95 struct uart_port serial_req;
96#endif
97 struct plat_serial8250_port *pdata;
98 bd_t *binfo = (bd_t *) __res;
99 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
100
101 /* Setup serial port access */
102 pdata[0].uartclk = binfo->bi_busfreq;
103 pdata[0].mapbase += binfo->bi_immr_base;
104 pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
105
106#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
107 memset(&serial_req, 0, sizeof (serial_req));
108 serial_req.iotype = UPIO_MEM;
109 serial_req.mapbase = pdata[0].mapbase;
110 serial_req.membase = pdata[0].membase;
111 serial_req.regshift = 0;
112
113 gen550_init(0, &serial_req);
114#endif
115
116 pdata[1].uartclk = binfo->bi_busfreq;
117 pdata[1].mapbase += binfo->bi_immr_base;
118 pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
119
120#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
121 /* Assume gen550_init() doesn't modify serial_req */
122 serial_req.mapbase = pdata[1].mapbase;
123 serial_req.membase = pdata[1].membase;
124
125 gen550_init(1, &serial_req);
126#endif
127}
128#endif
129
130void
131mpc83xx_restart(char *cmd)
132{
133 volatile unsigned char __iomem *reg;
134 unsigned char tmp;
135
136 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
137
138 local_irq_disable();
139
140 /*
141 * Unlock the BCSR bits so a PRST will update the contents.
142 * Otherwise the reset asserts but doesn't clear.
143 */
144 tmp = in_8(reg + BCSR_MISC_REG3_OFF);
145 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
146 out_8(reg + BCSR_MISC_REG3_OFF, tmp);
147
148 /*
149 * Trigger a reset via a low->high transition of the
150 * PORESET bit.
151 */
152 tmp = in_8(reg + BCSR_MISC_REG2_OFF);
153 tmp &= ~BCSR_MISC_REG2_PORESET;
154 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
155
156 udelay(1);
157
158 tmp |= BCSR_MISC_REG2_PORESET;
159 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
160
161 for(;;);
162}
163
164void
165mpc83xx_power_off(void)
166{
167 local_irq_disable();
168 for(;;);
169}
170
171void
172mpc83xx_halt(void)
173{
174 local_irq_disable();
175 for(;;);
176}
177
178#if defined(CONFIG_PCI)
179void __init
180mpc83xx_setup_pci1(struct pci_controller *hose)
181{
182 u16 reg16;
183 volatile immr_pcictrl_t * pci_ctrl;
184 volatile immr_ios_t * ios;
185 bd_t *binfo = (bd_t *) __res;
186
187 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
188 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
189
190 /*
191 * Configure PCI Outbound Translation Windows
192 */
193 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
194 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
195 ios->pocmr0 = POCMR_EN |
196 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
197 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
198
199 /* mapped to PCI1 IO space */
200 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
201 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
202 ios->pocmr1 = POCMR_EN | POCMR_IO |
203 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
204 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
205
206 /*
207 * Configure PCI Inbound Translation Windows
208 */
209 pci_ctrl->pitar1 = 0x0;
210 pci_ctrl->pibar1 = 0x0;
211 pci_ctrl->piebar1 = 0x0;
212 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
213
214 /*
215 * Release PCI RST signal
216 */
217 pci_ctrl->gcr = 0;
218 udelay(2000);
219 pci_ctrl->gcr = 1;
220 udelay(2000);
221
222 reg16 = 0xff;
223 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
224 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
225 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
226
227 /*
228 * Clear non-reserved bits in status register.
229 */
230 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
231 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
232
233 iounmap(pci_ctrl);
234 iounmap(ios);
235}
236
237void __init
238mpc83xx_setup_pci2(struct pci_controller *hose)
239{
240 u16 reg16;
241 volatile immr_pcictrl_t * pci_ctrl;
242 volatile immr_ios_t * ios;
243 bd_t *binfo = (bd_t *) __res;
244
245 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
246 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
247
248 /*
249 * Configure PCI Outbound Translation Windows
250 */
251 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
252 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
253 ios->pocmr3 = POCMR_EN | POCMR_DST |
254 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
255 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
256
257 /* mapped to PCI2 IO space */
258 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
259 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
260 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
261 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
262 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
263
264 /*
265 * Configure PCI Inbound Translation Windows
266 */
267 pci_ctrl->pitar1 = 0x0;
268 pci_ctrl->pibar1 = 0x0;
269 pci_ctrl->piebar1 = 0x0;
270 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
271
272 /*
273 * Release PCI RST signal
274 */
275 pci_ctrl->gcr = 0;
276 udelay(2000);
277 pci_ctrl->gcr = 1;
278 udelay(2000);
279
280 reg16 = 0xff;
281 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
282 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
283 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
284
285 /*
286 * Clear non-reserved bits in status register.
287 */
288 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
289 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
290
291 iounmap(pci_ctrl);
292 iounmap(ios);
293}
294
295/*
296 * PCI buses can be enabled only if SYS board combinates with PIB
297 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
298 * and 3 PCI slots, so people must configure the routes between them before
299 * enable PCI bus. This routes are under the control of PCA9555PW device which
300 * can be accessed via I2C bus 2 and are configured by firmware. Refer to
301 * Freescale to get more information about firmware configuration.
302 */
303
304extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
305extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
306 unsigned char pin);
307void __init
308mpc83xx_setup_hose(void)
309{
310 u32 val32;
311 volatile immr_clk_t * clk;
312 struct pci_controller * hose1;
313#ifdef CONFIG_MPC83xx_PCI2
314 struct pci_controller * hose2;
315#endif
316 bd_t * binfo = (bd_t *)__res;
317
318 clk = ioremap(binfo->bi_immr_base + 0xA00,
319 sizeof(immr_clk_t));
320
321 /*
322 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
323 */
324 val32 = clk->occr;
325 udelay(2000);
326 clk->occr = 0xff000000;
327 udelay(2000);
328
329 iounmap(clk);
330
331 hose1 = pcibios_alloc_controller();
332 if(!hose1)
333 return;
334
335 ppc_md.pci_swizzle = common_swizzle;
336 ppc_md.pci_map_irq = mpc83xx_map_irq;
337
338 hose1->bus_offset = 0;
339 hose1->first_busno = 0;
340 hose1->last_busno = 0xff;
341
342 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
343 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
344 hose1->set_cfg_type = 1;
345
346 mpc83xx_setup_pci1(hose1);
347
348 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
349 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
350 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
351
352 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
353 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
354 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
355#ifdef CONFIG_MPC83xx_PCI2
356 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
357 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
358#else
359 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
360 MPC83xx_PCI1_IO_SIZE);
361#endif /* CONFIG_MPC83xx_PCI2 */
362 hose1->io_base_virt = (void *)isa_io_base;
363 /* setup resources */
364 pci_init_resource(&hose1->io_resource,
365 MPC83xx_PCI1_LOWER_IO,
366 MPC83xx_PCI1_UPPER_IO,
367 IORESOURCE_IO, "PCI host bridge 1");
368 pci_init_resource(&hose1->mem_resources[0],
369 MPC83xx_PCI1_LOWER_MEM,
370 MPC83xx_PCI1_UPPER_MEM,
371 IORESOURCE_MEM, "PCI host bridge 1");
372
373 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
374 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
375
376#ifdef CONFIG_MPC83xx_PCI2
377 hose2 = pcibios_alloc_controller();
378 if(!hose2)
379 return;
380
381 hose2->bus_offset = hose1->last_busno + 1;
382 hose2->first_busno = hose1->last_busno + 1;
383 hose2->last_busno = 0xff;
384 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
385 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
386 hose2->set_cfg_type = 1;
387
388 mpc83xx_setup_pci2(hose2);
389
390 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
391 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
392 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
393
394 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
395 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
396 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
397 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
398 /* setup resources */
399 pci_init_resource(&hose2->io_resource,
400 MPC83xx_PCI2_LOWER_IO,
401 MPC83xx_PCI2_UPPER_IO,
402 IORESOURCE_IO, "PCI host bridge 2");
403 pci_init_resource(&hose2->mem_resources[0],
404 MPC83xx_PCI2_LOWER_MEM,
405 MPC83xx_PCI2_UPPER_MEM,
406 IORESOURCE_MEM, "PCI host bridge 2");
407
408 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
409#endif /* CONFIG_MPC83xx_PCI2 */
410}
411#endif /*CONFIG_PCI*/
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h
deleted file mode 100644
index b918a2d245ea..000000000000
--- a/arch/ppc/syslib/ppc83xx_setup.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * MPC83XX common board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H
24#define __PPC_SYSLIB_PPC83XX_SETUP_H
25
26#include <linux/init.h>
27
28extern unsigned long mpc83xx_find_end_of_memory(void) __init;
29extern long mpc83xx_time_init(void) __init;
30extern void mpc83xx_calibrate_decr(void) __init;
31extern void mpc83xx_early_serial_map(void) __init;
32extern void mpc83xx_restart(char *cmd);
33extern void mpc83xx_power_off(void);
34extern void mpc83xx_halt(void);
35extern void mpc83xx_setup_hose(void) __init;
36
37/* PCI config */
38#define PCI1_CFG_ADDR_OFFSET (0x8300)
39#define PCI1_CFG_DATA_OFFSET (0x8304)
40
41#define PCI2_CFG_ADDR_OFFSET (0x8380)
42#define PCI2_CFG_DATA_OFFSET (0x8384)
43
44/* Serial Config */
45#ifdef CONFIG_SERIAL_MANY_PORTS
46#define RS_TABLE_SIZE 64
47#else
48#define RS_TABLE_SIZE 2
49#endif
50
51#ifndef BASE_BAUD
52#define BASE_BAUD 115200
53#endif
54
55#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */
diff --git a/arch/ppc/syslib/ppc85xx_common.c b/arch/ppc/syslib/ppc85xx_common.c
deleted file mode 100644
index e5ac699e7316..000000000000
--- a/arch/ppc/syslib/ppc85xx_common.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * MPC85xx support routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/types.h>
15#include <linux/module.h>
16#include <linux/init.h>
17
18#include <asm/mpc85xx.h>
19#include <asm/mmu.h>
20
21/* ************************************************************************ */
22/* Return the value of CCSRBAR for the current board */
23
24phys_addr_t
25get_ccsrbar(void)
26{
27 return BOARD_CCSRBAR;
28}
29
30EXPORT_SYMBOL(get_ccsrbar);
31
32/* For now this is a pass through */
33phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
34{
35 return addr;
36};
37EXPORT_SYMBOL(fixup_bigphys_addr);
38
diff --git a/arch/ppc/syslib/ppc85xx_common.h b/arch/ppc/syslib/ppc85xx_common.h
deleted file mode 100644
index 4fc405425113..000000000000
--- a/arch/ppc/syslib/ppc85xx_common.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * MPC85xx support routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __PPC_SYSLIB_PPC85XX_COMMON_H
15#define __PPC_SYSLIB_PPC85XX_COMMON_H
16
17#include <linux/init.h>
18
19/* Provide access to ccsrbar for any modules, etc */
20phys_addr_t get_ccsrbar(void);
21
22#endif /* __PPC_SYSLIB_PPC85XX_COMMON_H */
diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c
deleted file mode 100644
index af2425e4655f..000000000000
--- a/arch/ppc/syslib/ppc85xx_rio.c
+++ /dev/null
@@ -1,932 +0,0 @@
1/*
2 * MPC85xx RapidIO support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
18#include <linux/rio.h>
19#include <linux/rio_drv.h>
20
21#include <asm/io.h>
22
23#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
24#define RIO_ATMU_REGS_OFFSET 0x10c00
25#define RIO_MSG_REGS_OFFSET 0x11000
26#define RIO_MAINT_WIN_SIZE 0x400000
27#define RIO_DBELL_WIN_SIZE 0x1000
28
29#define RIO_MSG_OMR_MUI 0x00000002
30#define RIO_MSG_OSR_TE 0x00000080
31#define RIO_MSG_OSR_QOI 0x00000020
32#define RIO_MSG_OSR_QFI 0x00000010
33#define RIO_MSG_OSR_MUB 0x00000004
34#define RIO_MSG_OSR_EOMI 0x00000002
35#define RIO_MSG_OSR_QEI 0x00000001
36
37#define RIO_MSG_IMR_MI 0x00000002
38#define RIO_MSG_ISR_TE 0x00000080
39#define RIO_MSG_ISR_QFI 0x00000010
40#define RIO_MSG_ISR_DIQI 0x00000001
41
42#define RIO_MSG_DESC_SIZE 32
43#define RIO_MSG_BUFFER_SIZE 4096
44#define RIO_MIN_TX_RING_SIZE 2
45#define RIO_MAX_TX_RING_SIZE 2048
46#define RIO_MIN_RX_RING_SIZE 2
47#define RIO_MAX_RX_RING_SIZE 2048
48
49#define DOORBELL_DMR_DI 0x00000002
50#define DOORBELL_DSR_TE 0x00000080
51#define DOORBELL_DSR_QFI 0x00000010
52#define DOORBELL_DSR_DIQI 0x00000001
53#define DOORBELL_TID_OFFSET 0x03
54#define DOORBELL_SID_OFFSET 0x05
55#define DOORBELL_INFO_OFFSET 0x06
56
57#define DOORBELL_MESSAGE_SIZE 0x08
58#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
59#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
60#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
61
62struct rio_atmu_regs {
63 u32 rowtar;
64 u32 pad1;
65 u32 rowbar;
66 u32 pad2;
67 u32 rowar;
68 u32 pad3[3];
69};
70
71struct rio_msg_regs {
72 u32 omr;
73 u32 osr;
74 u32 pad1;
75 u32 odqdpar;
76 u32 pad2;
77 u32 osar;
78 u32 odpr;
79 u32 odatr;
80 u32 odcr;
81 u32 pad3;
82 u32 odqepar;
83 u32 pad4[13];
84 u32 imr;
85 u32 isr;
86 u32 pad5;
87 u32 ifqdpar;
88 u32 pad6;
89 u32 ifqepar;
90 u32 pad7[250];
91 u32 dmr;
92 u32 dsr;
93 u32 pad8;
94 u32 dqdpar;
95 u32 pad9;
96 u32 dqepar;
97 u32 pad10[26];
98 u32 pwmr;
99 u32 pwsr;
100 u32 pad11;
101 u32 pwqbar;
102};
103
104struct rio_tx_desc {
105 u32 res1;
106 u32 saddr;
107 u32 dport;
108 u32 dattr;
109 u32 res2;
110 u32 res3;
111 u32 dwcnt;
112 u32 res4;
113};
114
115static u32 regs_win;
116static struct rio_atmu_regs *atmu_regs;
117static struct rio_atmu_regs *maint_atmu_regs;
118static struct rio_atmu_regs *dbell_atmu_regs;
119static u32 dbell_win;
120static u32 maint_win;
121static struct rio_msg_regs *msg_regs;
122
123static struct rio_dbell_ring {
124 void *virt;
125 dma_addr_t phys;
126} dbell_ring;
127
128static struct rio_msg_tx_ring {
129 void *virt;
130 dma_addr_t phys;
131 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
132 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
133 int tx_slot;
134 int size;
135 void *dev_id;
136} msg_tx_ring;
137
138static struct rio_msg_rx_ring {
139 void *virt;
140 dma_addr_t phys;
141 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
142 int rx_slot;
143 int size;
144 void *dev_id;
145} msg_rx_ring;
146
147/**
148 * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
149 * @index: ID of RapidIO interface
150 * @destid: Destination ID of target device
151 * @data: 16-bit info field of RapidIO doorbell message
152 *
153 * Sends a MPC85xx doorbell message. Returns %0 on success or
154 * %-EINVAL on failure.
155 */
156static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
157{
158 pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
159 index, destid, data);
160 out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
161 out_be16((void *)(dbell_win), data);
162
163 return 0;
164}
165
166/**
167 * mpc85xx_local_config_read - Generate a MPC85xx local config space read
168 * @index: ID of RapdiIO interface
169 * @offset: Offset into configuration space
170 * @len: Length (in bytes) of the maintenance transaction
171 * @data: Value to be read into
172 *
173 * Generates a MPC85xx local configuration space read. Returns %0 on
174 * success or %-EINVAL on failure.
175 */
176static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
177{
178 pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
179 offset);
180 *data = in_be32((void *)(regs_win + offset));
181
182 return 0;
183}
184
185/**
186 * mpc85xx_local_config_write - Generate a MPC85xx local config space write
187 * @index: ID of RapdiIO interface
188 * @offset: Offset into configuration space
189 * @len: Length (in bytes) of the maintenance transaction
190 * @data: Value to be written
191 *
192 * Generates a MPC85xx local configuration space write. Returns %0 on
193 * success or %-EINVAL on failure.
194 */
195static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
196{
197 pr_debug
198 ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
199 index, offset, data);
200 out_be32((void *)(regs_win + offset), data);
201
202 return 0;
203}
204
205/**
206 * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
207 * @index: ID of RapdiIO interface
208 * @destid: Destination ID of transaction
209 * @hopcount: Number of hops to target device
210 * @offset: Offset into configuration space
211 * @len: Length (in bytes) of the maintenance transaction
212 * @val: Location to be read into
213 *
214 * Generates a MPC85xx read maintenance transaction. Returns %0 on
215 * success or %-EINVAL on failure.
216 */
217static int
218mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
219 u32 * val)
220{
221 u8 *data;
222
223 pr_debug
224 ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
225 index, destid, hopcount, offset, len);
226 out_be32((void *)&maint_atmu_regs->rowtar,
227 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
228
229 data = (u8 *) maint_win + offset;
230 switch (len) {
231 case 1:
232 *val = in_8((u8 *) data);
233 break;
234 case 2:
235 *val = in_be16((u16 *) data);
236 break;
237 default:
238 *val = in_be32((u32 *) data);
239 break;
240 }
241
242 return 0;
243}
244
245/**
246 * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
247 * @index: ID of RapdiIO interface
248 * @destid: Destination ID of transaction
249 * @hopcount: Number of hops to target device
250 * @offset: Offset into configuration space
251 * @len: Length (in bytes) of the maintenance transaction
252 * @val: Value to be written
253 *
254 * Generates an MPC85xx write maintenance transaction. Returns %0 on
255 * success or %-EINVAL on failure.
256 */
257static int
258mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
259 int len, u32 val)
260{
261 u8 *data;
262 pr_debug
263 ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
264 index, destid, hopcount, offset, len, val);
265 out_be32((void *)&maint_atmu_regs->rowtar,
266 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
267
268 data = (u8 *) maint_win + offset;
269 switch (len) {
270 case 1:
271 out_8((u8 *) data, val);
272 break;
273 case 2:
274 out_be16((u16 *) data, val);
275 break;
276 default:
277 out_be32((u32 *) data, val);
278 break;
279 }
280
281 return 0;
282}
283
284/**
285 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
286 * @mport: Master port with outbound message queue
287 * @rdev: Target of outbound message
288 * @mbox: Outbound mailbox
289 * @buffer: Message to add to outbound queue
290 * @len: Length of message
291 *
292 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
293 * %0 on success or %-EINVAL on failure.
294 */
295int
296rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
297 void *buffer, size_t len)
298{
299 u32 omr;
300 struct rio_tx_desc *desc =
301 (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
302 int ret = 0;
303
304 pr_debug
305 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
306 rdev->destid, mbox, (int)buffer, len);
307
308 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
309 ret = -EINVAL;
310 goto out;
311 }
312
313 /* Copy and clear rest of buffer */
314 memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
315 if (len < (RIO_MAX_MSG_SIZE - 4))
316 memset((void *)((u32) msg_tx_ring.
317 virt_buffer[msg_tx_ring.tx_slot] + len), 0,
318 RIO_MAX_MSG_SIZE - len);
319
320 /* Set mbox field for message */
321 desc->dport = mbox & 0x3;
322
323 /* Enable EOMI interrupt, set priority, and set destid */
324 desc->dattr = 0x28000000 | (rdev->destid << 2);
325
326 /* Set transfer size aligned to next power of 2 (in double words) */
327 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
328
329 /* Set snooping and source buffer address */
330 desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
331
332 /* Increment enqueue pointer */
333 omr = in_be32((void *)&msg_regs->omr);
334 out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
335
336 /* Go to next descriptor */
337 if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
338 msg_tx_ring.tx_slot = 0;
339
340 out:
341 return ret;
342}
343
344EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
345
346/**
347 * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
348 * @irq: Linux interrupt number
349 * @dev_instance: Pointer to interrupt-specific data
350 *
351 * Handles outbound message interrupts. Executes a register outbound
352 * mailbox event handler and acks the interrupt occurrence.
353 */
354static irqreturn_t
355mpc85xx_rio_tx_handler(int irq, void *dev_instance)
356{
357 int osr;
358 struct rio_mport *port = (struct rio_mport *)dev_instance;
359
360 osr = in_be32((void *)&msg_regs->osr);
361
362 if (osr & RIO_MSG_OSR_TE) {
363 pr_info("RIO: outbound message transmission error\n");
364 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
365 goto out;
366 }
367
368 if (osr & RIO_MSG_OSR_QOI) {
369 pr_info("RIO: outbound message queue overflow\n");
370 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
371 goto out;
372 }
373
374 if (osr & RIO_MSG_OSR_EOMI) {
375 u32 dqp = in_be32((void *)&msg_regs->odqdpar);
376 int slot = (dqp - msg_tx_ring.phys) >> 5;
377 port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
378
379 /* Ack the end-of-message interrupt */
380 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
381 }
382
383 out:
384 return IRQ_HANDLED;
385}
386
387/**
388 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
389 * @mport: Master port implementing the outbound message unit
390 * @dev_id: Device specific pointer to pass on event
391 * @mbox: Mailbox to open
392 * @entries: Number of entries in the outbound mailbox ring
393 *
394 * Initializes buffer ring, request the outbound message interrupt,
395 * and enables the outbound message unit. Returns %0 on success and
396 * %-EINVAL or %-ENOMEM on failure.
397 */
398int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
399{
400 int i, j, rc = 0;
401
402 if ((entries < RIO_MIN_TX_RING_SIZE) ||
403 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
404 rc = -EINVAL;
405 goto out;
406 }
407
408 /* Initialize shadow copy ring */
409 msg_tx_ring.dev_id = dev_id;
410 msg_tx_ring.size = entries;
411
412 for (i = 0; i < msg_tx_ring.size; i++) {
413 if (!
414 (msg_tx_ring.virt_buffer[i] =
415 dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
416 &msg_tx_ring.phys_buffer[i],
417 GFP_KERNEL))) {
418 rc = -ENOMEM;
419 for (j = 0; j < msg_tx_ring.size; j++)
420 if (msg_tx_ring.virt_buffer[j])
421 dma_free_coherent(NULL,
422 RIO_MSG_BUFFER_SIZE,
423 msg_tx_ring.
424 virt_buffer[j],
425 msg_tx_ring.
426 phys_buffer[j]);
427 goto out;
428 }
429 }
430
431 /* Initialize outbound message descriptor ring */
432 if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
433 msg_tx_ring.size *
434 RIO_MSG_DESC_SIZE,
435 &msg_tx_ring.phys,
436 GFP_KERNEL))) {
437 rc = -ENOMEM;
438 goto out_dma;
439 }
440 memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
441 msg_tx_ring.tx_slot = 0;
442
443 /* Point dequeue/enqueue pointers at first entry in ring */
444 out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
445 out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
446
447 /* Configure for snooping */
448 out_be32((void *)&msg_regs->osar, 0x00000004);
449
450 /* Clear interrupt status */
451 out_be32((void *)&msg_regs->osr, 0x000000b3);
452
453 /* Hook up outbound message handler */
454 if ((rc =
455 request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
456 "msg_tx", (void *)mport)) < 0)
457 goto out_irq;
458
459 /*
460 * Configure outbound message unit
461 * Snooping
462 * Interrupts (all enabled, except QEIE)
463 * Chaining mode
464 * Disable
465 */
466 out_be32((void *)&msg_regs->omr, 0x00100220);
467
468 /* Set number of entries */
469 out_be32((void *)&msg_regs->omr,
470 in_be32((void *)&msg_regs->omr) |
471 ((get_bitmask_order(entries) - 2) << 12));
472
473 /* Now enable the unit */
474 out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
475
476 out:
477 return rc;
478
479 out_irq:
480 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
481 msg_tx_ring.virt, msg_tx_ring.phys);
482
483 out_dma:
484 for (i = 0; i < msg_tx_ring.size; i++)
485 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
486 msg_tx_ring.virt_buffer[i],
487 msg_tx_ring.phys_buffer[i]);
488
489 return rc;
490}
491
492/**
493 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
494 * @mport: Master port implementing the outbound message unit
495 * @mbox: Mailbox to close
496 *
497 * Disables the outbound message unit, free all buffers, and
498 * frees the outbound message interrupt.
499 */
500void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
501{
502 /* Disable inbound message unit */
503 out_be32((void *)&msg_regs->omr, 0);
504
505 /* Free ring */
506 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
507 msg_tx_ring.virt, msg_tx_ring.phys);
508
509 /* Free interrupt */
510 free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
511}
512
513/**
514 * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
515 * @irq: Linux interrupt number
516 * @dev_instance: Pointer to interrupt-specific data
517 *
518 * Handles inbound message interrupts. Executes a registered inbound
519 * mailbox event handler and acks the interrupt occurrence.
520 */
521static irqreturn_t
522mpc85xx_rio_rx_handler(int irq, void *dev_instance)
523{
524 int isr;
525 struct rio_mport *port = (struct rio_mport *)dev_instance;
526
527 isr = in_be32((void *)&msg_regs->isr);
528
529 if (isr & RIO_MSG_ISR_TE) {
530 pr_info("RIO: inbound message reception error\n");
531 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
532 goto out;
533 }
534
535 /* XXX Need to check/dispatch until queue empty */
536 if (isr & RIO_MSG_ISR_DIQI) {
537 /*
538 * We implement *only* mailbox 0, but can receive messages
539 * for any mailbox/letter to that mailbox destination. So,
540 * make the callback with an unknown/invalid mailbox number
541 * argument.
542 */
543 port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
544
545 /* Ack the queueing interrupt */
546 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
547 }
548
549 out:
550 return IRQ_HANDLED;
551}
552
553/**
554 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
555 * @mport: Master port implementing the inbound message unit
556 * @dev_id: Device specific pointer to pass on event
557 * @mbox: Mailbox to open
558 * @entries: Number of entries in the inbound mailbox ring
559 *
560 * Initializes buffer ring, request the inbound message interrupt,
561 * and enables the inbound message unit. Returns %0 on success
562 * and %-EINVAL or %-ENOMEM on failure.
563 */
564int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
565{
566 int i, rc = 0;
567
568 if ((entries < RIO_MIN_RX_RING_SIZE) ||
569 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
570 rc = -EINVAL;
571 goto out;
572 }
573
574 /* Initialize client buffer ring */
575 msg_rx_ring.dev_id = dev_id;
576 msg_rx_ring.size = entries;
577 msg_rx_ring.rx_slot = 0;
578 for (i = 0; i < msg_rx_ring.size; i++)
579 msg_rx_ring.virt_buffer[i] = NULL;
580
581 /* Initialize inbound message ring */
582 if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
583 msg_rx_ring.size *
584 RIO_MAX_MSG_SIZE,
585 &msg_rx_ring.phys,
586 GFP_KERNEL))) {
587 rc = -ENOMEM;
588 goto out;
589 }
590
591 /* Point dequeue/enqueue pointers at first entry in ring */
592 out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
593 out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
594
595 /* Clear interrupt status */
596 out_be32((void *)&msg_regs->isr, 0x00000091);
597
598 /* Hook up inbound message handler */
599 if ((rc =
600 request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
601 "msg_rx", (void *)mport)) < 0) {
602 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
603 msg_tx_ring.virt_buffer[i],
604 msg_tx_ring.phys_buffer[i]);
605 goto out;
606 }
607
608 /*
609 * Configure inbound message unit:
610 * Snooping
611 * 4KB max message size
612 * Unmask all interrupt sources
613 * Disable
614 */
615 out_be32((void *)&msg_regs->imr, 0x001b0060);
616
617 /* Set number of queue entries */
618 out_be32((void *)&msg_regs->imr,
619 in_be32((void *)&msg_regs->imr) |
620 ((get_bitmask_order(entries) - 2) << 12));
621
622 /* Now enable the unit */
623 out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
624
625 out:
626 return rc;
627}
628
629/**
630 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
631 * @mport: Master port implementing the inbound message unit
632 * @mbox: Mailbox to close
633 *
634 * Disables the inbound message unit, free all buffers, and
635 * frees the inbound message interrupt.
636 */
637void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
638{
639 /* Disable inbound message unit */
640 out_be32((void *)&msg_regs->imr, 0);
641
642 /* Free ring */
643 dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
644 msg_rx_ring.virt, msg_rx_ring.phys);
645
646 /* Free interrupt */
647 free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
648}
649
650/**
651 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
652 * @mport: Master port implementing the inbound message unit
653 * @mbox: Inbound mailbox number
654 * @buf: Buffer to add to inbound queue
655 *
656 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
657 * %0 on success or %-EINVAL on failure.
658 */
659int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
660{
661 int rc = 0;
662
663 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
664 msg_rx_ring.rx_slot);
665
666 if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
667 printk(KERN_ERR
668 "RIO: error adding inbound buffer %d, buffer exists\n",
669 msg_rx_ring.rx_slot);
670 rc = -EINVAL;
671 goto out;
672 }
673
674 msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
675 if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
676 msg_rx_ring.rx_slot = 0;
677
678 out:
679 return rc;
680}
681
682EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
683
684/**
685 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
686 * @mport: Master port implementing the inbound message unit
687 * @mbox: Inbound mailbox number
688 *
689 * Gets the next available inbound message from the inbound message queue.
690 * A pointer to the message is returned on success or NULL on failure.
691 */
692void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
693{
694 u32 imr;
695 u32 phys_buf, virt_buf;
696 void *buf = NULL;
697 int buf_idx;
698
699 phys_buf = in_be32((void *)&msg_regs->ifqdpar);
700
701 /* If no more messages, then bail out */
702 if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
703 goto out2;
704
705 virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
706 buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
707 buf = msg_rx_ring.virt_buffer[buf_idx];
708
709 if (!buf) {
710 printk(KERN_ERR
711 "RIO: inbound message copy failed, no buffers\n");
712 goto out1;
713 }
714
715 /* Copy max message size, caller is expected to allocate that big */
716 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
717
718 /* Clear the available buffer */
719 msg_rx_ring.virt_buffer[buf_idx] = NULL;
720
721 out1:
722 imr = in_be32((void *)&msg_regs->imr);
723 out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
724
725 out2:
726 return buf;
727}
728
729EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
730
731/**
732 * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
733 * @irq: Linux interrupt number
734 * @dev_instance: Pointer to interrupt-specific data
735 *
736 * Handles doorbell interrupts. Parses a list of registered
737 * doorbell event handlers and executes a matching event handler.
738 */
739static irqreturn_t
740mpc85xx_rio_dbell_handler(int irq, void *dev_instance)
741{
742 int dsr;
743 struct rio_mport *port = (struct rio_mport *)dev_instance;
744
745 dsr = in_be32((void *)&msg_regs->dsr);
746
747 if (dsr & DOORBELL_DSR_TE) {
748 pr_info("RIO: doorbell reception error\n");
749 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
750 goto out;
751 }
752
753 if (dsr & DOORBELL_DSR_QFI) {
754 pr_info("RIO: doorbell queue full\n");
755 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
756 goto out;
757 }
758
759 /* XXX Need to check/dispatch until queue empty */
760 if (dsr & DOORBELL_DSR_DIQI) {
761 u32 dmsg =
762 (u32) dbell_ring.virt +
763 (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
764 u32 dmr;
765 struct rio_dbell *dbell;
766 int found = 0;
767
768 pr_debug
769 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
770 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
771
772 list_for_each_entry(dbell, &port->dbells, node) {
773 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
774 (dbell->res->end >= DBELL_INF(dmsg))) {
775 found = 1;
776 break;
777 }
778 }
779 if (found) {
780 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
781 DBELL_INF(dmsg));
782 } else {
783 pr_debug
784 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
785 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
786 }
787 dmr = in_be32((void *)&msg_regs->dmr);
788 out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
789 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
790 }
791
792 out:
793 return IRQ_HANDLED;
794}
795
796/**
797 * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
798 * @mport: Master port implementing the inbound doorbell unit
799 *
800 * Initializes doorbell unit hardware and inbound DMA buffer
801 * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
802 * or %-ENOMEM on failure.
803 */
804static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
805{
806 int rc = 0;
807
808 /* Map outbound doorbell window immediately after maintenance window */
809 if (!(dbell_win =
810 (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
811 RIO_DBELL_WIN_SIZE))) {
812 printk(KERN_ERR
813 "RIO: unable to map outbound doorbell window\n");
814 rc = -ENOMEM;
815 goto out;
816 }
817
818 /* Initialize inbound doorbells */
819 if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
820 512 * DOORBELL_MESSAGE_SIZE,
821 &dbell_ring.phys,
822 GFP_KERNEL))) {
823 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
824 rc = -ENOMEM;
825 iounmap((void *)dbell_win);
826 goto out;
827 }
828
829 /* Point dequeue/enqueue pointers at first entry in ring */
830 out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
831 out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
832
833 /* Clear interrupt status */
834 out_be32((void *)&msg_regs->dsr, 0x00000091);
835
836 /* Hook up doorbell handler */
837 if ((rc =
838 request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
839 "dbell_rx", (void *)mport) < 0)) {
840 iounmap((void *)dbell_win);
841 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
842 dbell_ring.virt, dbell_ring.phys);
843 printk(KERN_ERR
844 "MPC85xx RIO: unable to request inbound doorbell irq");
845 goto out;
846 }
847
848 /* Configure doorbells for snooping, 512 entries, and enable */
849 out_be32((void *)&msg_regs->dmr, 0x00108161);
850
851 out:
852 return rc;
853}
854
855static char *cmdline = NULL;
856
857static int mpc85xx_rio_get_hdid(int index)
858{
859 /* XXX Need to parse multiple entries in some format */
860 if (!cmdline)
861 return -1;
862
863 return simple_strtol(cmdline, NULL, 0);
864}
865
866static int mpc85xx_rio_get_cmdline(char *s)
867{
868 if (!s)
869 return 0;
870
871 cmdline = s;
872 return 1;
873}
874
875__setup("riohdid=", mpc85xx_rio_get_cmdline);
876
877/**
878 * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
879 * @law_start: Starting physical address of RapidIO LAW
880 * @law_size: Size of RapidIO LAW
881 *
882 * Initializes MPC85xx RapidIO hardware interface, configures
883 * master port with system-specific info, and registers the
884 * master port with the RapidIO subsystem.
885 */
886void mpc85xx_rio_setup(int law_start, int law_size)
887{
888 struct rio_ops *ops;
889 struct rio_mport *port;
890
891 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
892 ops->lcread = mpc85xx_local_config_read;
893 ops->lcwrite = mpc85xx_local_config_write;
894 ops->cread = mpc85xx_rio_config_read;
895 ops->cwrite = mpc85xx_rio_config_write;
896 ops->dsend = mpc85xx_rio_doorbell_send;
897
898 port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
899 port->id = 0;
900 port->index = 0;
901 INIT_LIST_HEAD(&port->dbells);
902 port->iores.start = law_start;
903 port->iores.end = law_start + law_size;
904 port->iores.flags = IORESOURCE_MEM;
905
906 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
907 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
908 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
909 strcpy(port->name, "RIO0 mport");
910
911 port->ops = ops;
912 port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
913
914 rio_register_mport(port);
915
916 regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
917 atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
918 maint_atmu_regs = atmu_regs + 1;
919 dbell_atmu_regs = atmu_regs + 2;
920 msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
921
922 /* Configure maintenance transaction window */
923 out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
924 out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
925
926 maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
927
928 /* Configure outbound doorbell window */
929 out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
930 out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
931 mpc85xx_rio_doorbell_init(port);
932}
diff --git a/arch/ppc/syslib/ppc85xx_rio.h b/arch/ppc/syslib/ppc85xx_rio.h
deleted file mode 100644
index 6d3ff30b1579..000000000000
--- a/arch/ppc/syslib/ppc85xx_rio.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * MPC85xx RapidIO definitions
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __PPC_SYSLIB_PPC85XX_RIO_H
14#define __PPC_SYSLIB_PPC85XX_RIO_H
15
16#include <linux/init.h>
17
18extern void mpc85xx_rio_setup(int law_start, int law_size);
19
20#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
deleted file mode 100644
index 2475ec6600fe..000000000000
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ /dev/null
@@ -1,367 +0,0 @@
1/*
2 * MPC85XX common board code
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/types.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/pci.h>
18#include <linux/serial.h>
19#include <linux/tty.h> /* for linux/serial_core.h */
20#include <linux/serial_core.h>
21#include <linux/serial_8250.h>
22
23#include <asm/time.h>
24#include <asm/mpc85xx.h>
25#include <asm/immap_85xx.h>
26#include <asm/mmu.h>
27#include <asm/ppc_sys.h>
28#include <asm/kgdb.h>
29#include <asm/machdep.h>
30
31#include <syslib/ppc85xx_setup.h>
32
33extern void abort(void);
34
35/* Return the amount of memory */
36unsigned long __init
37mpc85xx_find_end_of_memory(void)
38{
39 bd_t *binfo;
40
41 binfo = (bd_t *) __res;
42
43 return binfo->bi_memsize;
44}
45
46/* The decrementer counts at the system (internal) clock freq divided by 8 */
47void __init
48mpc85xx_calibrate_decr(void)
49{
50 bd_t *binfo = (bd_t *) __res;
51 unsigned int freq, divisor;
52
53 /* get the core frequency */
54 freq = binfo->bi_busfreq;
55
56 /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
57 divisor = 8;
58 tb_ticks_per_jiffy = freq / divisor / HZ;
59 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
60
61 /* Set the time base to zero */
62 mtspr(SPRN_TBWL, 0);
63 mtspr(SPRN_TBWU, 0);
64
65 /* Clear any pending timer interrupts */
66 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
67
68 /* Enable decrementer interrupt */
69 mtspr(SPRN_TCR, TCR_DIE);
70}
71
72#ifdef CONFIG_SERIAL_8250
73void __init
74mpc85xx_early_serial_map(void)
75{
76#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
77 struct uart_port serial_req;
78#endif
79 struct plat_serial8250_port *pdata;
80 bd_t *binfo = (bd_t *) __res;
81 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
82
83 /* Setup serial port access */
84 pdata[0].uartclk = binfo->bi_busfreq;
85 pdata[0].mapbase += binfo->bi_immr_base;
86 pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
87
88#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
89 memset(&serial_req, 0, sizeof (serial_req));
90 serial_req.iotype = UPIO_MEM;
91 serial_req.mapbase = pdata[0].mapbase;
92 serial_req.membase = pdata[0].membase;
93 serial_req.regshift = 0;
94
95 gen550_init(0, &serial_req);
96#endif
97
98 pdata[1].uartclk = binfo->bi_busfreq;
99 pdata[1].mapbase += binfo->bi_immr_base;
100 pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
101
102#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
103 /* Assume gen550_init() doesn't modify serial_req */
104 serial_req.mapbase = pdata[1].mapbase;
105 serial_req.membase = pdata[1].membase;
106
107 gen550_init(1, &serial_req);
108#endif
109}
110#endif
111
112void
113mpc85xx_restart(char *cmd)
114{
115 local_irq_disable();
116 abort();
117}
118
119void
120mpc85xx_power_off(void)
121{
122 local_irq_disable();
123 for(;;);
124}
125
126void
127mpc85xx_halt(void)
128{
129 local_irq_disable();
130 for(;;);
131}
132
133#ifdef CONFIG_PCI
134
135#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
136extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
137extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
138#endif
139
140static void __init
141mpc85xx_setup_pci1(struct pci_controller *hose)
142{
143 volatile struct ccsr_pci *pci;
144 volatile struct ccsr_guts *guts;
145 unsigned short temps;
146 bd_t *binfo = (bd_t *) __res;
147
148 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
149 MPC85xx_PCI1_SIZE);
150
151 guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
152 MPC85xx_GUTS_SIZE);
153
154 early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
155 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
156 early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
157
158#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
159 if (guts->pordevsr & PORDEVSR_PCI) {
160 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
161 } else {
162 /* PCI-X init */
163 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
164 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
165 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
166 }
167
168 /* Disable all windows (except powar0 since its ignored) */
169 pci->powar1 = 0;
170 pci->powar2 = 0;
171 pci->powar3 = 0;
172 pci->powar4 = 0;
173 pci->piwar1 = 0;
174 pci->piwar2 = 0;
175 pci->piwar3 = 0;
176
177 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
178 pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
179 pci->potear1 = 0x00000000;
180 pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
181 /* Enable, Mem R/W */
182 pci->powar1 = 0x80044000 |
183 (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
184
185 /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
186 pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
187 pci->potear2 = 0x00000000;
188 pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
189 /* Enable, IO R/W */
190 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
191
192 /* Setup 2G inbound Memory Window @ 0 */
193 pci->pitar1 = 0x00000000;
194 pci->piwbar1 = 0x00000000;
195 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
196 Mem, Snoop R/W, 2G */
197}
198
199
200extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
201extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
202
203#ifdef CONFIG_85xx_PCI2
204static void __init
205mpc85xx_setup_pci2(struct pci_controller *hose)
206{
207 volatile struct ccsr_pci *pci;
208 unsigned short temps;
209 bd_t *binfo = (bd_t *) __res;
210
211 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
212 MPC85xx_PCI2_SIZE);
213
214 early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
215 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
216 early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
217 early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
218
219 /* Disable all windows (except powar0 since its ignored) */
220 pci->powar1 = 0;
221 pci->powar2 = 0;
222 pci->powar3 = 0;
223 pci->powar4 = 0;
224 pci->piwar1 = 0;
225 pci->piwar2 = 0;
226 pci->piwar3 = 0;
227
228 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
229 pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
230 pci->potear1 = 0x00000000;
231 pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
232 /* Enable, Mem R/W */
233 pci->powar1 = 0x80044000 |
234 (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
235
236 /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
237 pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;
238 pci->potear2 = 0x00000000;
239 pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
240 /* Enable, IO R/W */
241 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
242
243 /* Setup 2G inbound Memory Window @ 0 */
244 pci->pitar1 = 0x00000000;
245 pci->piwbar1 = 0x00000000;
246 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
247 Mem, Snoop R/W, 2G */
248}
249#endif /* CONFIG_85xx_PCI2 */
250
251int mpc85xx_pci1_last_busno = 0;
252
253void __init
254mpc85xx_setup_hose(void)
255{
256 struct pci_controller *hose_a;
257#ifdef CONFIG_85xx_PCI2
258 struct pci_controller *hose_b;
259#endif
260 bd_t *binfo = (bd_t *) __res;
261
262 hose_a = pcibios_alloc_controller();
263
264 if (!hose_a)
265 return;
266
267 ppc_md.pci_swizzle = common_swizzle;
268 ppc_md.pci_map_irq = mpc85xx_map_irq;
269
270 hose_a->first_busno = 0;
271 hose_a->bus_offset = 0;
272 hose_a->last_busno = 0xff;
273
274 setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
275 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
276 hose_a->set_cfg_type = 1;
277
278 mpc85xx_setup_pci1(hose_a);
279
280 hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
281 hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
282 hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
283
284 hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
285 hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
286 hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
287#ifdef CONFIG_85xx_PCI2
288 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
289 MPC85XX_PCI1_IO_SIZE +
290 MPC85XX_PCI2_IO_SIZE);
291#else
292 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
293 MPC85XX_PCI1_IO_SIZE);
294#endif
295 isa_io_base = (unsigned long)hose_a->io_base_virt;
296
297 /* setup resources */
298 pci_init_resource(&hose_a->mem_resources[0],
299 MPC85XX_PCI1_LOWER_MEM,
300 MPC85XX_PCI1_UPPER_MEM,
301 IORESOURCE_MEM, "PCI1 host bridge");
302
303 pci_init_resource(&hose_a->io_resource,
304 MPC85XX_PCI1_LOWER_IO,
305 MPC85XX_PCI1_UPPER_IO,
306 IORESOURCE_IO, "PCI1 host bridge");
307
308 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
309
310#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
311 /* Pre pciauto_bus_scan VIA init */
312 mpc85xx_cds_enable_via(hose_a);
313#endif
314
315 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
316
317#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
318 /* Post pciauto_bus_scan VIA fixup */
319 mpc85xx_cds_fixup_via(hose_a);
320#endif
321
322#ifdef CONFIG_85xx_PCI2
323 hose_b = pcibios_alloc_controller();
324
325 if (!hose_b)
326 return;
327
328 hose_b->bus_offset = hose_a->last_busno + 1;
329 hose_b->first_busno = hose_a->last_busno + 1;
330 hose_b->last_busno = 0xff;
331
332 setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
333 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
334 hose_b->set_cfg_type = 1;
335
336 mpc85xx_setup_pci2(hose_b);
337
338 hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
339 hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
340 hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
341
342 hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
343 hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
344 hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
345 hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
346
347 /* setup resources */
348 pci_init_resource(&hose_b->mem_resources[0],
349 MPC85XX_PCI2_LOWER_MEM,
350 MPC85XX_PCI2_UPPER_MEM,
351 IORESOURCE_MEM, "PCI2 host bridge");
352
353 pci_init_resource(&hose_b->io_resource,
354 MPC85XX_PCI2_LOWER_IO,
355 MPC85XX_PCI2_UPPER_IO,
356 IORESOURCE_IO, "PCI2 host bridge");
357
358 hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
359
360 /* let board code know what the last bus number was on PCI1 */
361 mpc85xx_pci1_last_busno = hose_a->last_busno;
362#endif
363 return;
364}
365#endif /* CONFIG_PCI */
366
367
diff --git a/arch/ppc/syslib/ppc85xx_setup.h b/arch/ppc/syslib/ppc85xx_setup.h
deleted file mode 100644
index 6ff79995210b..000000000000
--- a/arch/ppc/syslib/ppc85xx_setup.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * MPC85XX common board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __PPC_SYSLIB_PPC85XX_SETUP_H
16#define __PPC_SYSLIB_PPC85XX_SETUP_H
17
18#include <linux/init.h>
19#include <asm/ppcboot.h>
20
21extern unsigned long mpc85xx_find_end_of_memory(void) __init;
22extern void mpc85xx_calibrate_decr(void) __init;
23extern void mpc85xx_early_serial_map(void) __init;
24extern void mpc85xx_restart(char *cmd);
25extern void mpc85xx_power_off(void);
26extern void mpc85xx_halt(void);
27extern void mpc85xx_setup_hose(void) __init;
28
29/* PCI config */
30#define PCI1_CFG_ADDR_OFFSET (0x8000)
31#define PCI1_CFG_DATA_OFFSET (0x8004)
32
33#define PCI2_CFG_ADDR_OFFSET (0x9000)
34#define PCI2_CFG_DATA_OFFSET (0x9004)
35
36/* Additional register for PCI-X configuration */
37#define PCIX_NEXT_CAP 0x60
38#define PCIX_CAP_ID 0x61
39#define PCIX_COMMAND 0x62
40#define PCIX_STATUS 0x64
41
42/* Serial Config */
43#ifdef CONFIG_SERIAL_MANY_PORTS
44#define RS_TABLE_SIZE 64
45#else
46#define RS_TABLE_SIZE 2
47#endif
48
49#ifndef BASE_BAUD
50#define BASE_BAUD 115200
51#endif
52
53/* Offset of CPM register space */
54#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
55
56#endif /* __PPC_SYSLIB_PPC85XX_SETUP_H */
diff --git a/arch/ppc/syslib/ppc8xx_pic.c b/arch/ppc/syslib/ppc8xx_pic.c
index e8619c750732..bce9a75c80e3 100644
--- a/arch/ppc/syslib/ppc8xx_pic.c
+++ b/arch/ppc/syslib/ppc8xx_pic.c
@@ -16,7 +16,7 @@ extern int cpm_get_irq(void);
16 * the only interrupt controller. Some boards, like the MBX and 16 * the only interrupt controller. Some boards, like the MBX and
17 * Sandpoint have the 8259 as a secondary controller. Depending 17 * Sandpoint have the 8259 as a secondary controller. Depending
18 * upon the processor type, the internal controller can have as 18 * upon the processor type, the internal controller can have as
19 * few as 16 interrups or as many as 64. We could use the 19 * few as 16 interrupts or as many as 64. We could use the
20 * "clear_bit()" and "set_bit()" functions like other platforms, 20 * "clear_bit()" and "set_bit()" functions like other platforms,
21 * but they are overkill for us. 21 * but they are overkill for us.
22 */ 22 */
diff --git a/arch/ppc/syslib/ppc8xx_pic.h b/arch/ppc/syslib/ppc8xx_pic.h
index d7d9f651a91b..53bcd97ef7f5 100644
--- a/arch/ppc/syslib/ppc8xx_pic.h
+++ b/arch/ppc/syslib/ppc8xx_pic.h
@@ -6,7 +6,6 @@
6 6
7extern struct hw_interrupt_type ppc8xx_pic; 7extern struct hw_interrupt_type ppc8xx_pic;
8 8
9void m8xx_pic_init(void);
10void m8xx_do_IRQ(struct pt_regs *regs, 9void m8xx_do_IRQ(struct pt_regs *regs,
11 int cpu); 10 int cpu);
12int m8xx_get_irq(struct pt_regs *regs); 11int m8xx_get_irq(struct pt_regs *regs);
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index 2d48018b71d9..837183c24dfc 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -185,7 +185,7 @@ void platform_notify_map(const struct platform_notify_dev_map *map,
185 */ 185 */
186 186
187/* 187/*
188 Here we'll replace .name pointers with fixed-lenght strings 188 Here we'll replace .name pointers with fixed-length strings
189 Hereby, this should be called *before* any func stuff triggeded. 189 Hereby, this should be called *before* any func stuff triggeded.
190 */ 190 */
191void ppc_sys_device_initfunc(void) 191void ppc_sys_device_initfunc(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 09:22:47 -0500