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-rw-r--r--arch/ppc/syslib/Makefile4
-rw-r--r--arch/ppc/syslib/ibm440sp_common.c4
-rw-r--r--arch/ppc/syslib/ibm44x_common.c12
-rw-r--r--arch/ppc/syslib/ppc405_pci.c7
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.c442
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.h149
-rw-r--r--arch/ppc/syslib/ppc4xx_pic.c37
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.c938
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.h21
-rw-r--r--arch/ppc/syslib/ppc_sys.c1
-rw-r--r--arch/ppc/syslib/prom.c6
11 files changed, 1607 insertions, 14 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index b4ef15b45c4a..5bd33baac243 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common.o
15obj-$(CONFIG_440GP) += ibm440gp_common.o 15obj-$(CONFIG_440GP) += ibm440gp_common.o
16obj-$(CONFIG_440GX) += ibm440gx_common.o 16obj-$(CONFIG_440GX) += ibm440gx_common.o
17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o 17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
18obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
18ifeq ($(CONFIG_4xx),y) 19ifeq ($(CONFIG_4xx),y)
19ifeq ($(CONFIG_VIRTEX_II_PRO),y) 20ifeq ($(CONFIG_VIRTEX_II_PRO),y)
20obj-$(CONFIG_40x) += xilinx_pic.o 21obj-$(CONFIG_40x) += xilinx_pic.o
@@ -32,6 +33,7 @@ obj-$(CONFIG_PPC4xx_DMA) += ppc4xx_dma.o
32obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o 33obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o
33ifeq ($(CONFIG_40x),y) 34ifeq ($(CONFIG_40x),y)
34obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o 35obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o
36obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
35endif 37endif
36endif 38endif
37obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \ 39obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
@@ -46,12 +48,14 @@ obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o
46obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o 48obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
47obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o 49obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o
48obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o 50obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
51obj-$(CONFIG_EV64360) += todc_time.o
49obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o 52obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o
50obj-$(CONFIG_GEMINI) += open_pic.o 53obj-$(CONFIG_GEMINI) += open_pic.o
51obj-$(CONFIG_GT64260) += gt64260_pic.o 54obj-$(CONFIG_GT64260) += gt64260_pic.o
52obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o 55obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o
53obj-$(CONFIG_HDPU) += pci_auto.o 56obj-$(CONFIG_HDPU) += pci_auto.o
54obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o 57obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o
58obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o
55obj-$(CONFIG_KATANA) += pci_auto.o 59obj-$(CONFIG_KATANA) += pci_auto.o
56obj-$(CONFIG_MV64360) += mv64360_pic.o 60obj-$(CONFIG_MV64360) += mv64360_pic.o
57obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o 61obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o
diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c
index 417d4cff77a0..cdafda127d81 100644
--- a/arch/ppc/syslib/ibm440sp_common.c
+++ b/arch/ppc/syslib/ibm440sp_common.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/ppc/syslib/ibm440sp_common.c 2 * arch/ppc/syslib/ibm440sp_common.c
3 * 3 *
4 * PPC440SP system library 4 * PPC440SP/PPC440SPe system library
5 * 5 *
6 * Matt Porter <mporter@kernel.crashing.org> 6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc. 7 * Copyright 2002-2005 MontaVista Software Inc.
@@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_of_memory(void)
35 u32 mem_size = 0; 35 u32 mem_size = 0;
36 36
37 /* Read two bank sizes and sum */ 37 /* Read two bank sizes and sum */
38 for (i=0; i<2; i++) 38 for (i=0; i< MQ0_NUM_BANKS; i++)
39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { 39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) {
40 case MQ0_CONFIG_SIZE_8M: 40 case MQ0_CONFIG_SIZE_8M:
41 mem_size += PPC44x_MEM_SIZE_8M; 41 mem_size += PPC44x_MEM_SIZE_8M;
diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c
index 5152c8e41340..71db11d22158 100644
--- a/arch/ppc/syslib/ibm44x_common.c
+++ b/arch/ppc/syslib/ibm44x_common.c
@@ -20,6 +20,7 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial.h> 21#include <linux/serial.h>
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/initrd.h>
23 24
24#include <asm/ibm44x.h> 25#include <asm/ibm44x.h>
25#include <asm/mmu.h> 26#include <asm/mmu.h>
@@ -214,9 +215,20 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo
214/* Called from machine_check_exception */ 215/* Called from machine_check_exception */
215void platform_machine_check(struct pt_regs *regs) 216void platform_machine_check(struct pt_regs *regs)
216{ 217{
218#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
219 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
220 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
221 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
222 mfdcr(DCRN_PLB0_BESRL));
223 printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
224 mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
225 mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
226 mfdcr(DCRN_PLB1_BESRL));
227#else
217 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", 228 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
218 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), 229 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
219 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR)); 230 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
231#endif
220 printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n", 232 printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
221 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL), 233 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
222 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1)); 234 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
diff --git a/arch/ppc/syslib/ppc405_pci.c b/arch/ppc/syslib/ppc405_pci.c
index 81c83bf98df4..d6d838b16dac 100644
--- a/arch/ppc/syslib/ppc405_pci.c
+++ b/arch/ppc/syslib/ppc405_pci.c
@@ -89,13 +89,6 @@ ppc4xx_find_bridges(void)
89 isa_mem_base = 0; 89 isa_mem_base = 0;
90 pci_dram_offset = 0; 90 pci_dram_offset = 0;
91 91
92#if (PSR_PCI_ARBIT_EN > 1)
93 /* Check if running in slave mode */
94 if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
95 printk("Running as PCI slave, kernel PCI disabled !\n");
96 return;
97 }
98#endif
99 /* Setup PCI32 hose */ 92 /* Setup PCI32 hose */
100 hose_a = pcibios_alloc_controller(); 93 hose_a = pcibios_alloc_controller();
101 if (!hose_a) 94 if (!hose_a)
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
new file mode 100644
index 000000000000..1509fc1ddfb6
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -0,0 +1,442 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/config.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16
17#include <asm/reg.h>
18#include <asm/io.h>
19#include <asm/ibm44x.h>
20
21#include "ppc440spe_pcie.h"
22
23static int
24pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
25 int len, u32 *val)
26{
27 struct pci_controller *hose = bus->sysdata;
28
29 if (PCI_SLOT(devfn) != 1)
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 offset += devfn << 12;
33
34 /*
35 * Note: the caller has already checked that offset is
36 * suitably aligned and that len is 1, 2 or 4.
37 */
38 switch (len) {
39 case 1:
40 *val = in_8(hose->cfg_data + offset);
41 break;
42 case 2:
43 *val = in_le16(hose->cfg_data + offset);
44 break;
45 default:
46 *val = in_le32(hose->cfg_data + offset);
47 break;
48 }
49
50 if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
51
52 return PCIBIOS_SUCCESSFUL;
53}
54
55static int
56pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
57 int len, u32 val)
58{
59 struct pci_controller *hose = bus->sysdata;
60
61 if (PCI_SLOT(devfn) != 1)
62 return PCIBIOS_DEVICE_NOT_FOUND;
63
64 offset += devfn << 12;
65
66 switch (len) {
67 case 1:
68 out_8(hose->cfg_data + offset, val);
69 break;
70 case 2:
71 out_le16(hose->cfg_data + offset, val);
72 break;
73 default:
74 out_le32(hose->cfg_data + offset, val);
75 break;
76 }
77 return PCIBIOS_SUCCESSFUL;
78}
79
80static struct pci_ops pcie_pci_ops =
81{
82 .read = pcie_read_config,
83 .write = pcie_write_config
84};
85
86enum {
87 PTYPE_ENDPOINT = 0x0,
88 PTYPE_LEGACY_ENDPOINT = 0x1,
89 PTYPE_ROOT_PORT = 0x4,
90
91 LNKW_X1 = 0x1,
92 LNKW_X4 = 0x4,
93 LNKW_X8 = 0x8
94};
95
96static void check_error(void)
97{
98 u32 valPE0, valPE1, valPE2;
99
100 /* SDR0_PEGPLLLCT1 reset */
101 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
102 printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0);
103 }
104
105 valPE0 = SDR_READ(PESDR0_RCSSET);
106 valPE1 = SDR_READ(PESDR1_RCSSET);
107 valPE2 = SDR_READ(PESDR2_RCSSET);
108
109 /* SDR0_PExRCSSET rstgu */
110 if ( !(valPE0 & 0x01000000) ||
111 !(valPE1 & 0x01000000) ||
112 !(valPE2 & 0x01000000)) {
113 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
114 }
115
116 /* SDR0_PExRCSSET rstdl */
117 if ( !(valPE0 & 0x00010000) ||
118 !(valPE1 & 0x00010000) ||
119 !(valPE2 & 0x00010000)) {
120 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
121 }
122
123 /* SDR0_PExRCSSET rstpyn */
124 if ( (valPE0 & 0x00001000) ||
125 (valPE1 & 0x00001000) ||
126 (valPE2 & 0x00001000)) {
127 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
128 }
129
130 /* SDR0_PExRCSSET hldplb */
131 if ( (valPE0 & 0x10000000) ||
132 (valPE1 & 0x10000000) ||
133 (valPE2 & 0x10000000)) {
134 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
135 }
136
137 /* SDR0_PExRCSSET rdy */
138 if ( (valPE0 & 0x00100000) ||
139 (valPE1 & 0x00100000) ||
140 (valPE2 & 0x00100000)) {
141 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
142 }
143
144 /* SDR0_PExRCSSET shutdown */
145 if ( (valPE0 & 0x00000100) ||
146 (valPE1 & 0x00000100) ||
147 (valPE2 & 0x00000100)) {
148 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
149 }
150}
151
152/*
153 * Initialize PCI Express core as described in User Manual section 27.12.1
154 */
155int ppc440spe_init_pcie(void)
156{
157 /* Set PLL clock receiver to LVPECL */
158 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
159
160 check_error();
161
162 printk(KERN_INFO "PCIE initialization OK\n");
163
164 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
165 printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
166 SDR_READ(PESDR0_PLLLCT2));
167
168 /* De-assert reset of PCIe PLL, wait for lock */
169 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
170 udelay(3);
171
172 return 0;
173}
174
175int ppc440spe_init_pcie_rootport(int port)
176{
177 static int core_init;
178 void __iomem *utl_base;
179 u32 val = 0;
180 int i;
181
182 if (!core_init) {
183 ++core_init;
184 i = ppc440spe_init_pcie();
185 if (i)
186 return i;
187 }
188
189 /*
190 * Initialize various parts of the PCI Express core for our port:
191 *
192 * - Set as a root port and enable max width
193 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
194 * - Set up UTL configuration.
195 * - Increase SERDES drive strength to levels suggested by AMCC.
196 * - De-assert RSTPYN, RSTDL and RSTGU.
197 */
198 switch (port) {
199 case 0:
200 SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
201
202 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
203 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
204
205 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
206 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
207 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
208 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
209 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
210 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
211 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
212 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
213
214 SDR_WRITE(PESDR0_RCSSET,
215 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
216 break;
217
218 case 1:
219 SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
220
221 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
222 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
223
224 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
225 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
226 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
227 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
228
229 SDR_WRITE(PESDR1_RCSSET,
230 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
231 break;
232
233 case 2:
234 SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
235
236 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
237 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
238
239 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
240 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
241 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
242 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
243
244 SDR_WRITE(PESDR2_RCSSET,
245 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
246 break;
247 }
248
249 mdelay(1000);
250
251 switch (port) {
252 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
253 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
254 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
255 }
256
257 if (!(val & (1 << 20)))
258 printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
259 else
260 printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
261
262 switch (port) {
263 case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
264 case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
265 case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
266 }
267
268 /*
269 * Map UTL registers at 0xc_1000_0n00
270 */
271 switch (port) {
272 case 0:
273 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
274 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
275 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
276 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
277 break;
278
279 case 1:
280 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
281 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
282 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
283 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
284 break;
285
286 case 2:
287 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
288 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
289 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
290 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
291 }
292
293 utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
294
295 /*
296 * Set buffer allocations and then assert VRB and TXE.
297 */
298 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
299 out_be32(utl_base + PEUTL_INTR, 0x02000000);
300 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
301 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
302 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
303 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
304 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
305 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
306
307 iounmap(utl_base);
308
309 /*
310 * We map PCI Express configuration access into the 512MB regions
311 * PCIE0: 0xc_4000_0000
312 * PCIE1: 0xc_8000_0000
313 * PCIE2: 0xc_c000_0000
314 */
315 switch (port) {
316 case 0:
317 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
318 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
319 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
320 break;
321
322 case 1:
323 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
324 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
325 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
326 break;
327
328 case 2:
329 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
330 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
331 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
332 break;
333 }
334
335 /*
336 * Check for VC0 active and assert RDY.
337 */
338 switch (port) {
339 case 0:
340 if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
341 printk(KERN_WARNING "PCIE0: VC0 not active\n");
342 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
343 break;
344 case 1:
345 if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
346 printk(KERN_WARNING "PCIE0: VC0 not active\n");
347 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
348 break;
349 case 2:
350 if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
351 printk(KERN_WARNING "PCIE0: VC0 not active\n");
352 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
353 break;
354 }
355
356#if 0
357 /* Dump all config regs */
358 for (i = 0x300; i <= 0x320; ++i)
359 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
360 for (i = 0x340; i <= 0x353; ++i)
361 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
362 for (i = 0x370; i <= 0x383; ++i)
363 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
364 for (i = 0x3a0; i <= 0x3a2; ++i)
365 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
366 for (i = 0x3c0; i <= 0x3c3; ++i)
367 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
368#endif
369
370 mdelay(100);
371
372 return 0;
373}
374
375void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
376{
377 void __iomem *mbase;
378
379 /*
380 * Map 16MB, which is enough for 4 bits of bus #
381 */
382 hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000,
383 1 << 24);
384 hose->ops = &pcie_pci_ops;
385
386 /*
387 * Set bus numbers on our root port
388 */
389 mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096);
390 out_8(mbase + PCI_PRIMARY_BUS, 0);
391 out_8(mbase + PCI_SECONDARY_BUS, 0);
392
393 /*
394 * Set up outbound translation to hose->mem_space from PLB
395 * addresses at an offset of 0xd_0000_0000. We set the low
396 * bits of the mask to 11 to turn off splitting into 8
397 * subregions and to enable the outbound translation.
398 */
399 out_le32(mbase + PECFG_POM0LAH, 0);
400 out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start);
401
402 switch (port) {
403 case 0:
404 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
405 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start);
406 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
407 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
408 ~(hose->mem_space.end - hose->mem_space.start) | 3);
409 break;
410 case 1:
411 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
412 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start);
413 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
414 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
415 ~(hose->mem_space.end - hose->mem_space.start) | 3);
416
417 break;
418 case 2:
419 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
420 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start);
421 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
422 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
423 ~(hose->mem_space.end - hose->mem_space.start) | 3);
424 break;
425 }
426
427 /* Set up 16GB inbound memory window at 0 */
428 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
429 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
430 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
431 out_le32(mbase + PECFG_BAR0LMPA, 0);
432 out_le32(mbase + PECFG_PIM0LAL, 0);
433 out_le32(mbase + PECFG_PIM0LAH, 0);
434 out_le32(mbase + PECFG_PIMEN, 0x1);
435
436 /* Enable I/O, Mem, and Busmaster cycles */
437 out_le16(mbase + PCI_COMMAND,
438 in_le16(mbase + PCI_COMMAND) |
439 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
440
441 iounmap(mbase);
442}
diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h
new file mode 100644
index 000000000000..55b765ad3272
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H
12#define __PPC_SYSLIB_PPC440SPE_PCIE_H
13
14#define DCRN_SDR0_CFGADDR 0x00e
15#define DCRN_SDR0_CFGDATA 0x00f
16
17#define DCRN_PCIE0_BASE 0x100
18#define DCRN_PCIE1_BASE 0x120
19#define DCRN_PCIE2_BASE 0x140
20#define PCIE0 DCRN_PCIE0_BASE
21#define PCIE1 DCRN_PCIE1_BASE
22#define PCIE2 DCRN_PCIE2_BASE
23
24#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
25#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
26#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
27#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
28#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
29#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
30#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
31#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
32#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
33#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
34#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
35#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
36#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
37#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
38
39/*
40 * System DCRs (SDRs)
41 */
42#define PESDR0_PLLLCT1 0x03a0
43#define PESDR0_PLLLCT2 0x03a1
44#define PESDR0_PLLLCT3 0x03a2
45
46#define PESDR0_UTLSET1 0x0300
47#define PESDR0_UTLSET2 0x0301
48#define PESDR0_DLPSET 0x0302
49#define PESDR0_LOOP 0x0303
50#define PESDR0_RCSSET 0x0304
51#define PESDR0_RCSSTS 0x0305
52#define PESDR0_HSSL0SET1 0x0306
53#define PESDR0_HSSL0SET2 0x0307
54#define PESDR0_HSSL0STS 0x0308
55#define PESDR0_HSSL1SET1 0x0309
56#define PESDR0_HSSL1SET2 0x030a
57#define PESDR0_HSSL1STS 0x030b
58#define PESDR0_HSSL2SET1 0x030c
59#define PESDR0_HSSL2SET2 0x030d
60#define PESDR0_HSSL2STS 0x030e
61#define PESDR0_HSSL3SET1 0x030f
62#define PESDR0_HSSL3SET2 0x0310
63#define PESDR0_HSSL3STS 0x0311
64#define PESDR0_HSSL4SET1 0x0312
65#define PESDR0_HSSL4SET2 0x0313
66#define PESDR0_HSSL4STS 0x0314
67#define PESDR0_HSSL5SET1 0x0315
68#define PESDR0_HSSL5SET2 0x0316
69#define PESDR0_HSSL5STS 0x0317
70#define PESDR0_HSSL6SET1 0x0318
71#define PESDR0_HSSL6SET2 0x0319
72#define PESDR0_HSSL6STS 0x031a
73#define PESDR0_HSSL7SET1 0x031b
74#define PESDR0_HSSL7SET2 0x031c
75#define PESDR0_HSSL7STS 0x031d
76#define PESDR0_HSSCTLSET 0x031e
77#define PESDR0_LANE_ABCD 0x031f
78#define PESDR0_LANE_EFGH 0x0320
79
80#define PESDR1_UTLSET1 0x0340
81#define PESDR1_UTLSET2 0x0341
82#define PESDR1_DLPSET 0x0342
83#define PESDR1_LOOP 0x0343
84#define PESDR1_RCSSET 0x0344
85#define PESDR1_RCSSTS 0x0345
86#define PESDR1_HSSL0SET1 0x0346
87#define PESDR1_HSSL0SET2 0x0347
88#define PESDR1_HSSL0STS 0x0348
89#define PESDR1_HSSL1SET1 0x0349
90#define PESDR1_HSSL1SET2 0x034a
91#define PESDR1_HSSL1STS 0x034b
92#define PESDR1_HSSL2SET1 0x034c
93#define PESDR1_HSSL2SET2 0x034d
94#define PESDR1_HSSL2STS 0x034e
95#define PESDR1_HSSL3SET1 0x034f
96#define PESDR1_HSSL3SET2 0x0350
97#define PESDR1_HSSL3STS 0x0351
98#define PESDR1_HSSCTLSET 0x0352
99#define PESDR1_LANE_ABCD 0x0353
100
101#define PESDR2_UTLSET1 0x0370
102#define PESDR2_UTLSET2 0x0371
103#define PESDR2_DLPSET 0x0372
104#define PESDR2_LOOP 0x0373
105#define PESDR2_RCSSET 0x0374
106#define PESDR2_RCSSTS 0x0375
107#define PESDR2_HSSL0SET1 0x0376
108#define PESDR2_HSSL0SET2 0x0377
109#define PESDR2_HSSL0STS 0x0378
110#define PESDR2_HSSL1SET1 0x0379
111#define PESDR2_HSSL1SET2 0x037a
112#define PESDR2_HSSL1STS 0x037b
113#define PESDR2_HSSL2SET1 0x037c
114#define PESDR2_HSSL2SET2 0x037d
115#define PESDR2_HSSL2STS 0x037e
116#define PESDR2_HSSL3SET1 0x037f
117#define PESDR2_HSSL3SET2 0x0380
118#define PESDR2_HSSL3STS 0x0381
119#define PESDR2_HSSCTLSET 0x0382
120#define PESDR2_LANE_ABCD 0x0383
121
122/*
123 * UTL register offsets
124 */
125#define PEUTL_PBBSZ 0x20
126#define PEUTL_OPDBSZ 0x68
127#define PEUTL_IPHBSZ 0x70
128#define PEUTL_IPDBSZ 0x78
129#define PEUTL_OUTTR 0x90
130#define PEUTL_INTR 0x98
131#define PEUTL_PCTL 0xa0
132#define PEUTL_RCIRQEN 0xb8
133
134/*
135 * Config space register offsets
136 */
137#define PECFG_BAR0LMPA 0x210
138#define PECFG_BAR0HMPA 0x214
139#define PECFG_PIMEN 0x33c
140#define PECFG_PIM0LAL 0x340
141#define PECFG_PIM0LAH 0x344
142#define PECFG_POM0LAL 0x380
143#define PECFG_POM0LAH 0x384
144
145int ppc440spe_init_pcie(void);
146int ppc440spe_init_pcie_rootport(int port);
147void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
148
149#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */
diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 0b435633a0d1..aa4165144ec2 100644
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -38,6 +38,7 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) 38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) 39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) 40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
41#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq)
41 42
42#define UIC_HANDLERS(n) \ 43#define UIC_HANDLERS(n) \
43static void ppc4xx_uic##n##_enable(unsigned int irq) \ 44static void ppc4xx_uic##n##_enable(unsigned int irq) \
@@ -88,7 +89,38 @@ static void ppc4xx_uic##n##_end(unsigned int irq) \
88 .end = ppc4xx_uic##n##_end, \ 89 .end = ppc4xx_uic##n##_end, \
89} \ 90} \
90 91
91#if NR_UICS == 3 92#if NR_UICS == 4
93#define ACK_UIC0_PARENT
94#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
95#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
96#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
97UIC_HANDLERS(0);
98UIC_HANDLERS(1);
99UIC_HANDLERS(2);
100UIC_HANDLERS(3);
101
102static int ppc4xx_pic_get_irq(struct pt_regs *regs)
103{
104 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
105 if (uic0 & UIC0_UIC1NC)
106 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
107 else if (uic0 & UIC0_UIC2NC)
108 return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
109 else if (uic0 & UIC0_UIC3NC)
110 return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3)));
111 else
112 return uic0 ? 32 - ffs(uic0) : -1;
113}
114
115static void __init ppc4xx_pic_impl_init(void)
116{
117 /* Enable cascade interrupts in UIC0 */
118 ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
119 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
120 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
121}
122
123#elif NR_UICS == 3
92#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); 124#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
93#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); 125#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
94#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); 126#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -170,6 +202,9 @@ static struct ppc4xx_uic_impl {
170 { .decl = DECLARE_UIC(1), .base = UIC1 }, 202 { .decl = DECLARE_UIC(1), .base = UIC1 },
171#if NR_UICS > 2 203#if NR_UICS > 2
172 { .decl = DECLARE_UIC(2), .base = UIC2 }, 204 { .decl = DECLARE_UIC(2), .base = UIC2 },
205#if NR_UICS > 3
206 { .decl = DECLARE_UIC(3), .base = UIC3 },
207#endif
173#endif 208#endif
174#endif 209#endif
175}; 210};
diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c
new file mode 100644
index 000000000000..297f3b549177
--- /dev/null
+++ b/arch/ppc/syslib/ppc85xx_rio.c
@@ -0,0 +1,938 @@
1/*
2 * MPC85xx RapidIO support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/dma-mapping.h>
18#include <linux/interrupt.h>
19#include <linux/rio.h>
20#include <linux/rio_drv.h>
21
22#include <asm/io.h>
23
24#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
25#define RIO_ATMU_REGS_OFFSET 0x10c00
26#define RIO_MSG_REGS_OFFSET 0x11000
27#define RIO_MAINT_WIN_SIZE 0x400000
28#define RIO_DBELL_WIN_SIZE 0x1000
29
30#define RIO_MSG_OMR_MUI 0x00000002
31#define RIO_MSG_OSR_TE 0x00000080
32#define RIO_MSG_OSR_QOI 0x00000020
33#define RIO_MSG_OSR_QFI 0x00000010
34#define RIO_MSG_OSR_MUB 0x00000004
35#define RIO_MSG_OSR_EOMI 0x00000002
36#define RIO_MSG_OSR_QEI 0x00000001
37
38#define RIO_MSG_IMR_MI 0x00000002
39#define RIO_MSG_ISR_TE 0x00000080
40#define RIO_MSG_ISR_QFI 0x00000010
41#define RIO_MSG_ISR_DIQI 0x00000001
42
43#define RIO_MSG_DESC_SIZE 32
44#define RIO_MSG_BUFFER_SIZE 4096
45#define RIO_MIN_TX_RING_SIZE 2
46#define RIO_MAX_TX_RING_SIZE 2048
47#define RIO_MIN_RX_RING_SIZE 2
48#define RIO_MAX_RX_RING_SIZE 2048
49
50#define DOORBELL_DMR_DI 0x00000002
51#define DOORBELL_DSR_TE 0x00000080
52#define DOORBELL_DSR_QFI 0x00000010
53#define DOORBELL_DSR_DIQI 0x00000001
54#define DOORBELL_TID_OFFSET 0x03
55#define DOORBELL_SID_OFFSET 0x05
56#define DOORBELL_INFO_OFFSET 0x06
57
58#define DOORBELL_MESSAGE_SIZE 0x08
59#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
60#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
61#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
62
63#define is_power_of_2(x) (((x) & ((x) - 1)) == 0)
64
65struct rio_atmu_regs {
66 u32 rowtar;
67 u32 pad1;
68 u32 rowbar;
69 u32 pad2;
70 u32 rowar;
71 u32 pad3[3];
72};
73
74struct rio_msg_regs {
75 u32 omr;
76 u32 osr;
77 u32 pad1;
78 u32 odqdpar;
79 u32 pad2;
80 u32 osar;
81 u32 odpr;
82 u32 odatr;
83 u32 odcr;
84 u32 pad3;
85 u32 odqepar;
86 u32 pad4[13];
87 u32 imr;
88 u32 isr;
89 u32 pad5;
90 u32 ifqdpar;
91 u32 pad6;
92 u32 ifqepar;
93 u32 pad7[250];
94 u32 dmr;
95 u32 dsr;
96 u32 pad8;
97 u32 dqdpar;
98 u32 pad9;
99 u32 dqepar;
100 u32 pad10[26];
101 u32 pwmr;
102 u32 pwsr;
103 u32 pad11;
104 u32 pwqbar;
105};
106
107struct rio_tx_desc {
108 u32 res1;
109 u32 saddr;
110 u32 dport;
111 u32 dattr;
112 u32 res2;
113 u32 res3;
114 u32 dwcnt;
115 u32 res4;
116};
117
118static u32 regs_win;
119static struct rio_atmu_regs *atmu_regs;
120static struct rio_atmu_regs *maint_atmu_regs;
121static struct rio_atmu_regs *dbell_atmu_regs;
122static u32 dbell_win;
123static u32 maint_win;
124static struct rio_msg_regs *msg_regs;
125
126static struct rio_dbell_ring {
127 void *virt;
128 dma_addr_t phys;
129} dbell_ring;
130
131static struct rio_msg_tx_ring {
132 void *virt;
133 dma_addr_t phys;
134 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
135 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
136 int tx_slot;
137 int size;
138 void *dev_id;
139} msg_tx_ring;
140
141static struct rio_msg_rx_ring {
142 void *virt;
143 dma_addr_t phys;
144 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
145 int rx_slot;
146 int size;
147 void *dev_id;
148} msg_rx_ring;
149
150/**
151 * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
152 * @index: ID of RapidIO interface
153 * @destid: Destination ID of target device
154 * @data: 16-bit info field of RapidIO doorbell message
155 *
156 * Sends a MPC85xx doorbell message. Returns %0 on success or
157 * %-EINVAL on failure.
158 */
159static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
160{
161 pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
162 index, destid, data);
163 out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
164 out_be16((void *)(dbell_win), data);
165
166 return 0;
167}
168
169/**
170 * mpc85xx_local_config_read - Generate a MPC85xx local config space read
171 * @index: ID of RapdiIO interface
172 * @offset: Offset into configuration space
173 * @len: Length (in bytes) of the maintenance transaction
174 * @data: Value to be read into
175 *
176 * Generates a MPC85xx local configuration space read. Returns %0 on
177 * success or %-EINVAL on failure.
178 */
179static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
180{
181 pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
182 offset);
183 *data = in_be32((void *)(regs_win + offset));
184
185 return 0;
186}
187
188/**
189 * mpc85xx_local_config_write - Generate a MPC85xx local config space write
190 * @index: ID of RapdiIO interface
191 * @offset: Offset into configuration space
192 * @len: Length (in bytes) of the maintenance transaction
193 * @data: Value to be written
194 *
195 * Generates a MPC85xx local configuration space write. Returns %0 on
196 * success or %-EINVAL on failure.
197 */
198static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
199{
200 pr_debug
201 ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
202 index, offset, data);
203 out_be32((void *)(regs_win + offset), data);
204
205 return 0;
206}
207
208/**
209 * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
210 * @index: ID of RapdiIO interface
211 * @destid: Destination ID of transaction
212 * @hopcount: Number of hops to target device
213 * @offset: Offset into configuration space
214 * @len: Length (in bytes) of the maintenance transaction
215 * @val: Location to be read into
216 *
217 * Generates a MPC85xx read maintenance transaction. Returns %0 on
218 * success or %-EINVAL on failure.
219 */
220static int
221mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
222 u32 * val)
223{
224 u8 *data;
225
226 pr_debug
227 ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
228 index, destid, hopcount, offset, len);
229 out_be32((void *)&maint_atmu_regs->rowtar,
230 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
231
232 data = (u8 *) maint_win + offset;
233 switch (len) {
234 case 1:
235 *val = in_8((u8 *) data);
236 break;
237 case 2:
238 *val = in_be16((u16 *) data);
239 break;
240 default:
241 *val = in_be32((u32 *) data);
242 break;
243 }
244
245 return 0;
246}
247
248/**
249 * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
250 * @index: ID of RapdiIO interface
251 * @destid: Destination ID of transaction
252 * @hopcount: Number of hops to target device
253 * @offset: Offset into configuration space
254 * @len: Length (in bytes) of the maintenance transaction
255 * @val: Value to be written
256 *
257 * Generates an MPC85xx write maintenance transaction. Returns %0 on
258 * success or %-EINVAL on failure.
259 */
260static int
261mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
262 int len, u32 val)
263{
264 u8 *data;
265 pr_debug
266 ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
267 index, destid, hopcount, offset, len, val);
268 out_be32((void *)&maint_atmu_regs->rowtar,
269 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
270
271 data = (u8 *) maint_win + offset;
272 switch (len) {
273 case 1:
274 out_8((u8 *) data, val);
275 break;
276 case 2:
277 out_be16((u16 *) data, val);
278 break;
279 default:
280 out_be32((u32 *) data, val);
281 break;
282 }
283
284 return 0;
285}
286
287/**
288 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
289 * @mport: Master port with outbound message queue
290 * @rdev: Target of outbound message
291 * @mbox: Outbound mailbox
292 * @buffer: Message to add to outbound queue
293 * @len: Length of message
294 *
295 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
296 * %0 on success or %-EINVAL on failure.
297 */
298int
299rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
300 void *buffer, size_t len)
301{
302 u32 omr;
303 struct rio_tx_desc *desc =
304 (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
305 int ret = 0;
306
307 pr_debug
308 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
309 rdev->destid, mbox, (int)buffer, len);
310
311 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
312 ret = -EINVAL;
313 goto out;
314 }
315
316 /* Copy and clear rest of buffer */
317 memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
318 if (len < (RIO_MAX_MSG_SIZE - 4))
319 memset((void *)((u32) msg_tx_ring.
320 virt_buffer[msg_tx_ring.tx_slot] + len), 0,
321 RIO_MAX_MSG_SIZE - len);
322
323 /* Set mbox field for message */
324 desc->dport = mbox & 0x3;
325
326 /* Enable EOMI interrupt, set priority, and set destid */
327 desc->dattr = 0x28000000 | (rdev->destid << 2);
328
329 /* Set transfer size aligned to next power of 2 (in double words) */
330 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
331
332 /* Set snooping and source buffer address */
333 desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
334
335 /* Increment enqueue pointer */
336 omr = in_be32((void *)&msg_regs->omr);
337 out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
338
339 /* Go to next descriptor */
340 if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
341 msg_tx_ring.tx_slot = 0;
342
343 out:
344 return ret;
345}
346
347EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
348
349/**
350 * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
351 * @irq: Linux interrupt number
352 * @dev_instance: Pointer to interrupt-specific data
353 * @regs: Register context
354 *
355 * Handles outbound message interrupts. Executes a register outbound
356 * mailbox event handler and acks the interrupt occurence.
357 */
358static irqreturn_t
359mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs)
360{
361 int osr;
362 struct rio_mport *port = (struct rio_mport *)dev_instance;
363
364 osr = in_be32((void *)&msg_regs->osr);
365
366 if (osr & RIO_MSG_OSR_TE) {
367 pr_info("RIO: outbound message transmission error\n");
368 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
369 goto out;
370 }
371
372 if (osr & RIO_MSG_OSR_QOI) {
373 pr_info("RIO: outbound message queue overflow\n");
374 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
375 goto out;
376 }
377
378 if (osr & RIO_MSG_OSR_EOMI) {
379 u32 dqp = in_be32((void *)&msg_regs->odqdpar);
380 int slot = (dqp - msg_tx_ring.phys) >> 5;
381 port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
382
383 /* Ack the end-of-message interrupt */
384 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
385 }
386
387 out:
388 return IRQ_HANDLED;
389}
390
391/**
392 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
393 * @mport: Master port implementing the outbound message unit
394 * @dev_id: Device specific pointer to pass on event
395 * @mbox: Mailbox to open
396 * @entries: Number of entries in the outbound mailbox ring
397 *
398 * Initializes buffer ring, request the outbound message interrupt,
399 * and enables the outbound message unit. Returns %0 on success and
400 * %-EINVAL or %-ENOMEM on failure.
401 */
402int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
403{
404 int i, j, rc = 0;
405
406 if ((entries < RIO_MIN_TX_RING_SIZE) ||
407 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
408 rc = -EINVAL;
409 goto out;
410 }
411
412 /* Initialize shadow copy ring */
413 msg_tx_ring.dev_id = dev_id;
414 msg_tx_ring.size = entries;
415
416 for (i = 0; i < msg_tx_ring.size; i++) {
417 if (!
418 (msg_tx_ring.virt_buffer[i] =
419 dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
420 &msg_tx_ring.phys_buffer[i],
421 GFP_KERNEL))) {
422 rc = -ENOMEM;
423 for (j = 0; j < msg_tx_ring.size; j++)
424 if (msg_tx_ring.virt_buffer[j])
425 dma_free_coherent(NULL,
426 RIO_MSG_BUFFER_SIZE,
427 msg_tx_ring.
428 virt_buffer[j],
429 msg_tx_ring.
430 phys_buffer[j]);
431 goto out;
432 }
433 }
434
435 /* Initialize outbound message descriptor ring */
436 if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
437 msg_tx_ring.size *
438 RIO_MSG_DESC_SIZE,
439 &msg_tx_ring.phys,
440 GFP_KERNEL))) {
441 rc = -ENOMEM;
442 goto out_dma;
443 }
444 memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
445 msg_tx_ring.tx_slot = 0;
446
447 /* Point dequeue/enqueue pointers at first entry in ring */
448 out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
449 out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
450
451 /* Configure for snooping */
452 out_be32((void *)&msg_regs->osar, 0x00000004);
453
454 /* Clear interrupt status */
455 out_be32((void *)&msg_regs->osr, 0x000000b3);
456
457 /* Hook up outbound message handler */
458 if ((rc =
459 request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
460 "msg_tx", (void *)mport)) < 0)
461 goto out_irq;
462
463 /*
464 * Configure outbound message unit
465 * Snooping
466 * Interrupts (all enabled, except QEIE)
467 * Chaining mode
468 * Disable
469 */
470 out_be32((void *)&msg_regs->omr, 0x00100220);
471
472 /* Set number of entries */
473 out_be32((void *)&msg_regs->omr,
474 in_be32((void *)&msg_regs->omr) |
475 ((get_bitmask_order(entries) - 2) << 12));
476
477 /* Now enable the unit */
478 out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
479
480 out:
481 return rc;
482
483 out_irq:
484 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
485 msg_tx_ring.virt, msg_tx_ring.phys);
486
487 out_dma:
488 for (i = 0; i < msg_tx_ring.size; i++)
489 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
490 msg_tx_ring.virt_buffer[i],
491 msg_tx_ring.phys_buffer[i]);
492
493 return rc;
494}
495
496/**
497 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
498 * @mport: Master port implementing the outbound message unit
499 * @mbox: Mailbox to close
500 *
501 * Disables the outbound message unit, free all buffers, and
502 * frees the outbound message interrupt.
503 */
504void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
505{
506 /* Disable inbound message unit */
507 out_be32((void *)&msg_regs->omr, 0);
508
509 /* Free ring */
510 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
511 msg_tx_ring.virt, msg_tx_ring.phys);
512
513 /* Free interrupt */
514 free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
515}
516
517/**
518 * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
519 * @irq: Linux interrupt number
520 * @dev_instance: Pointer to interrupt-specific data
521 * @regs: Register context
522 *
523 * Handles inbound message interrupts. Executes a registered inbound
524 * mailbox event handler and acks the interrupt occurence.
525 */
526static irqreturn_t
527mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs)
528{
529 int isr;
530 struct rio_mport *port = (struct rio_mport *)dev_instance;
531
532 isr = in_be32((void *)&msg_regs->isr);
533
534 if (isr & RIO_MSG_ISR_TE) {
535 pr_info("RIO: inbound message reception error\n");
536 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
537 goto out;
538 }
539
540 /* XXX Need to check/dispatch until queue empty */
541 if (isr & RIO_MSG_ISR_DIQI) {
542 /*
543 * We implement *only* mailbox 0, but can receive messages
544 * for any mailbox/letter to that mailbox destination. So,
545 * make the callback with an unknown/invalid mailbox number
546 * argument.
547 */
548 port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
549
550 /* Ack the queueing interrupt */
551 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
552 }
553
554 out:
555 return IRQ_HANDLED;
556}
557
558/**
559 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
560 * @mport: Master port implementing the inbound message unit
561 * @dev_id: Device specific pointer to pass on event
562 * @mbox: Mailbox to open
563 * @entries: Number of entries in the inbound mailbox ring
564 *
565 * Initializes buffer ring, request the inbound message interrupt,
566 * and enables the inbound message unit. Returns %0 on success
567 * and %-EINVAL or %-ENOMEM on failure.
568 */
569int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
570{
571 int i, rc = 0;
572
573 if ((entries < RIO_MIN_RX_RING_SIZE) ||
574 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
575 rc = -EINVAL;
576 goto out;
577 }
578
579 /* Initialize client buffer ring */
580 msg_rx_ring.dev_id = dev_id;
581 msg_rx_ring.size = entries;
582 msg_rx_ring.rx_slot = 0;
583 for (i = 0; i < msg_rx_ring.size; i++)
584 msg_rx_ring.virt_buffer[i] = NULL;
585
586 /* Initialize inbound message ring */
587 if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
588 msg_rx_ring.size *
589 RIO_MAX_MSG_SIZE,
590 &msg_rx_ring.phys,
591 GFP_KERNEL))) {
592 rc = -ENOMEM;
593 goto out;
594 }
595
596 /* Point dequeue/enqueue pointers at first entry in ring */
597 out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
598 out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
599
600 /* Clear interrupt status */
601 out_be32((void *)&msg_regs->isr, 0x00000091);
602
603 /* Hook up inbound message handler */
604 if ((rc =
605 request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
606 "msg_rx", (void *)mport)) < 0) {
607 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
608 msg_tx_ring.virt_buffer[i],
609 msg_tx_ring.phys_buffer[i]);
610 goto out;
611 }
612
613 /*
614 * Configure inbound message unit:
615 * Snooping
616 * 4KB max message size
617 * Unmask all interrupt sources
618 * Disable
619 */
620 out_be32((void *)&msg_regs->imr, 0x001b0060);
621
622 /* Set number of queue entries */
623 out_be32((void *)&msg_regs->imr,
624 in_be32((void *)&msg_regs->imr) |
625 ((get_bitmask_order(entries) - 2) << 12));
626
627 /* Now enable the unit */
628 out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
629
630 out:
631 return rc;
632}
633
634/**
635 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
636 * @mport: Master port implementing the inbound message unit
637 * @mbox: Mailbox to close
638 *
639 * Disables the inbound message unit, free all buffers, and
640 * frees the inbound message interrupt.
641 */
642void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
643{
644 /* Disable inbound message unit */
645 out_be32((void *)&msg_regs->imr, 0);
646
647 /* Free ring */
648 dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
649 msg_rx_ring.virt, msg_rx_ring.phys);
650
651 /* Free interrupt */
652 free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
653}
654
655/**
656 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
657 * @mport: Master port implementing the inbound message unit
658 * @mbox: Inbound mailbox number
659 * @buf: Buffer to add to inbound queue
660 *
661 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
662 * %0 on success or %-EINVAL on failure.
663 */
664int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
665{
666 int rc = 0;
667
668 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
669 msg_rx_ring.rx_slot);
670
671 if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
672 printk(KERN_ERR
673 "RIO: error adding inbound buffer %d, buffer exists\n",
674 msg_rx_ring.rx_slot);
675 rc = -EINVAL;
676 goto out;
677 }
678
679 msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
680 if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
681 msg_rx_ring.rx_slot = 0;
682
683 out:
684 return rc;
685}
686
687EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
688
689/**
690 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
691 * @mport: Master port implementing the inbound message unit
692 * @mbox: Inbound mailbox number
693 *
694 * Gets the next available inbound message from the inbound message queue.
695 * A pointer to the message is returned on success or NULL on failure.
696 */
697void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
698{
699 u32 imr;
700 u32 phys_buf, virt_buf;
701 void *buf = NULL;
702 int buf_idx;
703
704 phys_buf = in_be32((void *)&msg_regs->ifqdpar);
705
706 /* If no more messages, then bail out */
707 if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
708 goto out2;
709
710 virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
711 buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
712 buf = msg_rx_ring.virt_buffer[buf_idx];
713
714 if (!buf) {
715 printk(KERN_ERR
716 "RIO: inbound message copy failed, no buffers\n");
717 goto out1;
718 }
719
720 /* Copy max message size, caller is expected to allocate that big */
721 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
722
723 /* Clear the available buffer */
724 msg_rx_ring.virt_buffer[buf_idx] = NULL;
725
726 out1:
727 imr = in_be32((void *)&msg_regs->imr);
728 out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
729
730 out2:
731 return buf;
732}
733
734EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
735
736/**
737 * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
738 * @irq: Linux interrupt number
739 * @dev_instance: Pointer to interrupt-specific data
740 * @regs: Register context
741 *
742 * Handles doorbell interrupts. Parses a list of registered
743 * doorbell event handlers and executes a matching event handler.
744 */
745static irqreturn_t
746mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs)
747{
748 int dsr;
749 struct rio_mport *port = (struct rio_mport *)dev_instance;
750
751 dsr = in_be32((void *)&msg_regs->dsr);
752
753 if (dsr & DOORBELL_DSR_TE) {
754 pr_info("RIO: doorbell reception error\n");
755 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
756 goto out;
757 }
758
759 if (dsr & DOORBELL_DSR_QFI) {
760 pr_info("RIO: doorbell queue full\n");
761 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
762 goto out;
763 }
764
765 /* XXX Need to check/dispatch until queue empty */
766 if (dsr & DOORBELL_DSR_DIQI) {
767 u32 dmsg =
768 (u32) dbell_ring.virt +
769 (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
770 u32 dmr;
771 struct rio_dbell *dbell;
772 int found = 0;
773
774 pr_debug
775 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
776 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
777
778 list_for_each_entry(dbell, &port->dbells, node) {
779 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
780 (dbell->res->end >= DBELL_INF(dmsg))) {
781 found = 1;
782 break;
783 }
784 }
785 if (found) {
786 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
787 DBELL_INF(dmsg));
788 } else {
789 pr_debug
790 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
791 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
792 }
793 dmr = in_be32((void *)&msg_regs->dmr);
794 out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
795 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
796 }
797
798 out:
799 return IRQ_HANDLED;
800}
801
802/**
803 * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
804 * @mport: Master port implementing the inbound doorbell unit
805 *
806 * Initializes doorbell unit hardware and inbound DMA buffer
807 * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
808 * or %-ENOMEM on failure.
809 */
810static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
811{
812 int rc = 0;
813
814 /* Map outbound doorbell window immediately after maintenance window */
815 if (!(dbell_win =
816 (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
817 RIO_DBELL_WIN_SIZE))) {
818 printk(KERN_ERR
819 "RIO: unable to map outbound doorbell window\n");
820 rc = -ENOMEM;
821 goto out;
822 }
823
824 /* Initialize inbound doorbells */
825 if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
826 512 * DOORBELL_MESSAGE_SIZE,
827 &dbell_ring.phys,
828 GFP_KERNEL))) {
829 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
830 rc = -ENOMEM;
831 iounmap((void *)dbell_win);
832 goto out;
833 }
834
835 /* Point dequeue/enqueue pointers at first entry in ring */
836 out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
837 out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
838
839 /* Clear interrupt status */
840 out_be32((void *)&msg_regs->dsr, 0x00000091);
841
842 /* Hook up doorbell handler */
843 if ((rc =
844 request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
845 "dbell_rx", (void *)mport) < 0)) {
846 iounmap((void *)dbell_win);
847 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
848 dbell_ring.virt, dbell_ring.phys);
849 printk(KERN_ERR
850 "MPC85xx RIO: unable to request inbound doorbell irq");
851 goto out;
852 }
853
854 /* Configure doorbells for snooping, 512 entries, and enable */
855 out_be32((void *)&msg_regs->dmr, 0x00108161);
856
857 out:
858 return rc;
859}
860
861static char *cmdline = NULL;
862
863static int mpc85xx_rio_get_hdid(int index)
864{
865 /* XXX Need to parse multiple entries in some format */
866 if (!cmdline)
867 return -1;
868
869 return simple_strtol(cmdline, NULL, 0);
870}
871
872static int mpc85xx_rio_get_cmdline(char *s)
873{
874 if (!s)
875 return 0;
876
877 cmdline = s;
878 return 1;
879}
880
881__setup("riohdid=", mpc85xx_rio_get_cmdline);
882
883/**
884 * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
885 * @law_start: Starting physical address of RapidIO LAW
886 * @law_size: Size of RapidIO LAW
887 *
888 * Initializes MPC85xx RapidIO hardware interface, configures
889 * master port with system-specific info, and registers the
890 * master port with the RapidIO subsystem.
891 */
892void mpc85xx_rio_setup(int law_start, int law_size)
893{
894 struct rio_ops *ops;
895 struct rio_mport *port;
896
897 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
898 ops->lcread = mpc85xx_local_config_read;
899 ops->lcwrite = mpc85xx_local_config_write;
900 ops->cread = mpc85xx_rio_config_read;
901 ops->cwrite = mpc85xx_rio_config_write;
902 ops->dsend = mpc85xx_rio_doorbell_send;
903
904 port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
905 port->id = 0;
906 port->index = 0;
907 INIT_LIST_HEAD(&port->dbells);
908 port->iores.start = law_start;
909 port->iores.end = law_start + law_size;
910 port->iores.flags = IORESOURCE_MEM;
911
912 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
913 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
914 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
915 strcpy(port->name, "RIO0 mport");
916
917 port->ops = ops;
918 port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
919
920 rio_register_mport(port);
921
922 regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
923 atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
924 maint_atmu_regs = atmu_regs + 1;
925 dbell_atmu_regs = atmu_regs + 2;
926 msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
927
928 /* Configure maintenance transaction window */
929 out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
930 out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
931
932 maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
933
934 /* Configure outbound doorbell window */
935 out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
936 out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
937 mpc85xx_rio_doorbell_init(port);
938}
diff --git a/arch/ppc/syslib/ppc85xx_rio.h b/arch/ppc/syslib/ppc85xx_rio.h
new file mode 100644
index 000000000000..c0827a2c3eec
--- /dev/null
+++ b/arch/ppc/syslib/ppc85xx_rio.h
@@ -0,0 +1,21 @@
1/*
2 * MPC85xx RapidIO definitions
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __PPC_SYSLIB_PPC85XX_RIO_H
14#define __PPC_SYSLIB_PPC85XX_RIO_H
15
16#include <linux/config.h>
17#include <linux/init.h>
18
19extern void mpc85xx_rio_setup(int law_start, int law_size);
20
21#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index 62ee86e80711..603f01190816 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -14,6 +14,7 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17#include <linux/string.h>
17#include <asm/ppc_sys.h> 18#include <asm/ppc_sys.h>
18 19
19int (*ppc_sys_device_fixup) (struct platform_device * pdev); 20int (*ppc_sys_device_fixup) (struct platform_device * pdev);
diff --git a/arch/ppc/syslib/prom.c b/arch/ppc/syslib/prom.c
index 278da6ee62ea..1b9aa0d6a924 100644
--- a/arch/ppc/syslib/prom.c
+++ b/arch/ppc/syslib/prom.c
@@ -1335,10 +1335,8 @@ release_OF_resource(struct device_node* node, int index)
1335 if (!res) 1335 if (!res)
1336 return -ENODEV; 1336 return -ENODEV;
1337 1337
1338 if (res->name) { 1338 kfree(res->name);
1339 kfree(res->name); 1339 res->name = NULL;
1340 res->name = NULL;
1341 }
1342 release_resource(res); 1340 release_resource(res);
1343 kfree(res); 1341 kfree(res);
1344 1342
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 15:59:32 -0500