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-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c410
1 files changed, 0 insertions, 410 deletions
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
deleted file mode 100644
index ea372914dd6e..000000000000
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * MPC83XX common board code
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Added PCI support -- Tony Li <tony.li@freescale.com>
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/serial.h>
30#include <linux/tty.h> /* for linux/serial_core.h */
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/time.h>
35#include <asm/mpc83xx.h>
36#include <asm/mmu.h>
37#include <asm/ppc_sys.h>
38#include <asm/kgdb.h>
39#include <asm/delay.h>
40#include <asm/machdep.h>
41
42#include <syslib/ppc83xx_setup.h>
43#if defined(CONFIG_PCI)
44#include <syslib/ppc83xx_pci.h>
45#endif
46
47phys_addr_t immrbar;
48
49/* Return the amount of memory */
50unsigned long __init
51mpc83xx_find_end_of_memory(void)
52{
53 bd_t *binfo;
54
55 binfo = (bd_t *) __res;
56
57 return binfo->bi_memsize;
58}
59
60long __init
61mpc83xx_time_init(void)
62{
63#define SPCR_OFFS 0x00000110
64#define SPCR_TBEN 0x00400000
65
66 bd_t *binfo = (bd_t *)__res;
67 u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
68
69 *spcr |= SPCR_TBEN;
70
71 iounmap(spcr);
72
73 return 0;
74}
75
76/* The decrementer counts at the system (internal) clock freq divided by 4 */
77void __init
78mpc83xx_calibrate_decr(void)
79{
80 bd_t *binfo = (bd_t *) __res;
81 unsigned int freq, divisor;
82
83 freq = binfo->bi_busfreq;
84 divisor = 4;
85 tb_ticks_per_jiffy = freq / HZ / divisor;
86 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
87}
88
89#ifdef CONFIG_SERIAL_8250
90void __init
91mpc83xx_early_serial_map(void)
92{
93#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
94 struct uart_port serial_req;
95#endif
96 struct plat_serial8250_port *pdata;
97 bd_t *binfo = (bd_t *) __res;
98 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
99
100 /* Setup serial port access */
101 pdata[0].uartclk = binfo->bi_busfreq;
102 pdata[0].mapbase += binfo->bi_immr_base;
103 pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
104
105#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
106 memset(&serial_req, 0, sizeof (serial_req));
107 serial_req.iotype = UPIO_MEM;
108 serial_req.mapbase = pdata[0].mapbase;
109 serial_req.membase = pdata[0].membase;
110 serial_req.regshift = 0;
111
112 gen550_init(0, &serial_req);
113#endif
114
115 pdata[1].uartclk = binfo->bi_busfreq;
116 pdata[1].mapbase += binfo->bi_immr_base;
117 pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
118
119#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
120 /* Assume gen550_init() doesn't modify serial_req */
121 serial_req.mapbase = pdata[1].mapbase;
122 serial_req.membase = pdata[1].membase;
123
124 gen550_init(1, &serial_req);
125#endif
126}
127#endif
128
129void
130mpc83xx_restart(char *cmd)
131{
132 volatile unsigned char __iomem *reg;
133 unsigned char tmp;
134
135 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
136
137 local_irq_disable();
138
139 /*
140 * Unlock the BCSR bits so a PRST will update the contents.
141 * Otherwise the reset asserts but doesn't clear.
142 */
143 tmp = in_8(reg + BCSR_MISC_REG3_OFF);
144 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
145 out_8(reg + BCSR_MISC_REG3_OFF, tmp);
146
147 /*
148 * Trigger a reset via a low->high transition of the
149 * PORESET bit.
150 */
151 tmp = in_8(reg + BCSR_MISC_REG2_OFF);
152 tmp &= ~BCSR_MISC_REG2_PORESET;
153 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
154
155 udelay(1);
156
157 tmp |= BCSR_MISC_REG2_PORESET;
158 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
159
160 for(;;);
161}
162
163void
164mpc83xx_power_off(void)
165{
166 local_irq_disable();
167 for(;;);
168}
169
170void
171mpc83xx_halt(void)
172{
173 local_irq_disable();
174 for(;;);
175}
176
177#if defined(CONFIG_PCI)
178void __init
179mpc83xx_setup_pci1(struct pci_controller *hose)
180{
181 u16 reg16;
182 volatile immr_pcictrl_t * pci_ctrl;
183 volatile immr_ios_t * ios;
184 bd_t *binfo = (bd_t *) __res;
185
186 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
187 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
188
189 /*
190 * Configure PCI Outbound Translation Windows
191 */
192 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
193 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
194 ios->pocmr0 = POCMR_EN |
195 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
196 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
197
198 /* mapped to PCI1 IO space */
199 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
200 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
201 ios->pocmr1 = POCMR_EN | POCMR_IO |
202 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
203 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
204
205 /*
206 * Configure PCI Inbound Translation Windows
207 */
208 pci_ctrl->pitar1 = 0x0;
209 pci_ctrl->pibar1 = 0x0;
210 pci_ctrl->piebar1 = 0x0;
211 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
212
213 /*
214 * Release PCI RST signal
215 */
216 pci_ctrl->gcr = 0;
217 udelay(2000);
218 pci_ctrl->gcr = 1;
219 udelay(2000);
220
221 reg16 = 0xff;
222 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
223 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
224 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
225
226 /*
227 * Clear non-reserved bits in status register.
228 */
229 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
230 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
231
232 iounmap(pci_ctrl);
233 iounmap(ios);
234}
235
236void __init
237mpc83xx_setup_pci2(struct pci_controller *hose)
238{
239 u16 reg16;
240 volatile immr_pcictrl_t * pci_ctrl;
241 volatile immr_ios_t * ios;
242 bd_t *binfo = (bd_t *) __res;
243
244 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
245 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
246
247 /*
248 * Configure PCI Outbound Translation Windows
249 */
250 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
251 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
252 ios->pocmr3 = POCMR_EN | POCMR_DST |
253 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
254 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
255
256 /* mapped to PCI2 IO space */
257 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
258 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
259 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
260 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
261 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
262
263 /*
264 * Configure PCI Inbound Translation Windows
265 */
266 pci_ctrl->pitar1 = 0x0;
267 pci_ctrl->pibar1 = 0x0;
268 pci_ctrl->piebar1 = 0x0;
269 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
270
271 /*
272 * Release PCI RST signal
273 */
274 pci_ctrl->gcr = 0;
275 udelay(2000);
276 pci_ctrl->gcr = 1;
277 udelay(2000);
278
279 reg16 = 0xff;
280 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
281 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
282 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
283
284 /*
285 * Clear non-reserved bits in status register.
286 */
287 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
288 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
289
290 iounmap(pci_ctrl);
291 iounmap(ios);
292}
293
294/*
295 * PCI buses can be enabled only if SYS board combinates with PIB
296 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
297 * and 3 PCI slots, so people must configure the routes between them before
298 * enable PCI bus. This routes are under the control of PCA9555PW device which
299 * can be accessed via I2C bus 2 and are configured by firmware. Refer to
300 * Freescale to get more information about firmware configuration.
301 */
302
303extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
304extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
305 unsigned char pin);
306void __init
307mpc83xx_setup_hose(void)
308{
309 u32 val32;
310 volatile immr_clk_t * clk;
311 struct pci_controller * hose1;
312#ifdef CONFIG_MPC83xx_PCI2
313 struct pci_controller * hose2;
314#endif
315 bd_t * binfo = (bd_t *)__res;
316
317 clk = ioremap(binfo->bi_immr_base + 0xA00,
318 sizeof(immr_clk_t));
319
320 /*
321 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
322 */
323 val32 = clk->occr;
324 udelay(2000);
325 clk->occr = 0xff000000;
326 udelay(2000);
327
328 iounmap(clk);
329
330 hose1 = pcibios_alloc_controller();
331 if(!hose1)
332 return;
333
334 ppc_md.pci_swizzle = common_swizzle;
335 ppc_md.pci_map_irq = mpc83xx_map_irq;
336
337 hose1->bus_offset = 0;
338 hose1->first_busno = 0;
339 hose1->last_busno = 0xff;
340
341 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
342 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
343 hose1->set_cfg_type = 1;
344
345 mpc83xx_setup_pci1(hose1);
346
347 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
348 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
349 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
350
351 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
352 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
353 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
354#ifdef CONFIG_MPC83xx_PCI2
355 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
356 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
357#else
358 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
359 MPC83xx_PCI1_IO_SIZE);
360#endif /* CONFIG_MPC83xx_PCI2 */
361 hose1->io_base_virt = (void *)isa_io_base;
362 /* setup resources */
363 pci_init_resource(&hose1->io_resource,
364 MPC83xx_PCI1_LOWER_IO,
365 MPC83xx_PCI1_UPPER_IO,
366 IORESOURCE_IO, "PCI host bridge 1");
367 pci_init_resource(&hose1->mem_resources[0],
368 MPC83xx_PCI1_LOWER_MEM,
369 MPC83xx_PCI1_UPPER_MEM,
370 IORESOURCE_MEM, "PCI host bridge 1");
371
372 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
373 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
374
375#ifdef CONFIG_MPC83xx_PCI2
376 hose2 = pcibios_alloc_controller();
377 if(!hose2)
378 return;
379
380 hose2->bus_offset = hose1->last_busno + 1;
381 hose2->first_busno = hose1->last_busno + 1;
382 hose2->last_busno = 0xff;
383 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
384 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
385 hose2->set_cfg_type = 1;
386
387 mpc83xx_setup_pci2(hose2);
388
389 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
390 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
391 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
392
393 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
394 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
395 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
396 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
397 /* setup resources */
398 pci_init_resource(&hose2->io_resource,
399 MPC83xx_PCI2_LOWER_IO,
400 MPC83xx_PCI2_UPPER_IO,
401 IORESOURCE_IO, "PCI host bridge 2");
402 pci_init_resource(&hose2->mem_resources[0],
403 MPC83xx_PCI2_LOWER_MEM,
404 MPC83xx_PCI2_UPPER_MEM,
405 IORESOURCE_MEM, "PCI host bridge 2");
406
407 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
408#endif /* CONFIG_MPC83xx_PCI2 */
409}
410#endif /*CONFIG_PCI*/
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