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-rw-r--r--arch/ppc/syslib/hawk_common.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/ppc/syslib/hawk_common.c b/arch/ppc/syslib/hawk_common.c
index c5bf16b0d6a1..86821d8753ed 100644
--- a/arch/ppc/syslib/hawk_common.c
+++ b/arch/ppc/syslib/hawk_common.c
@@ -165,7 +165,7 @@ hawk_init(struct pci_controller *hose,
165 processor_pci_mem_start + 165 processor_pci_mem_start +
166 hose->mem_space.start) | 0x0); 166 hose->mem_space.start) | 0x0);
167 167
168 /* Map MPIC into vitual memory */ 168 /* Map MPIC into virtual memory */
169 OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE); 169 OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
170 170
171 return 0; 171 return 0;
@@ -176,7 +176,7 @@ hawk_init(struct pci_controller *hose,
176 * This assumes that PPCBug has initialized the memory controller (SMC) 176 * This assumes that PPCBug has initialized the memory controller (SMC)
177 * on the Falcon/HAWK correctly (i.e., it does no sanity checking). 177 * on the Falcon/HAWK correctly (i.e., it does no sanity checking).
178 * It also assumes that the memory base registers are set to configure the 178 * It also assumes that the memory base registers are set to configure the
179 * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc. 179 * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
180 * however, RAM base registers can be skipped (e.g. A, B, C are set, 180 * however, RAM base registers can be skipped (e.g. A, B, C are set,
181 * D is skipped but E is set is okay). 181 * D is skipped but E is set is okay).
182 */ 182 */