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-rw-r--r--arch/ppc/platforms/Makefile12
-rw-r--r--arch/ppc/platforms/chrp_nvram.c83
-rw-r--r--arch/ppc/platforms/chrp_pci.c309
-rw-r--r--arch/ppc/platforms/chrp_pegasos_eth.c211
-rw-r--r--arch/ppc/platforms/chrp_setup.c669
-rw-r--r--arch/ppc/platforms/chrp_smp.c99
-rw-r--r--arch/ppc/platforms/chrp_time.c251
7 files changed, 0 insertions, 1634 deletions
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index e8b91a33ce91..90c622294423 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -2,18 +2,10 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5# Extra CFLAGS so we don't have to do relative includes
6CFLAGS_chrp_setup.o += -Iarch/$(ARCH)/mm
7
8obj-$(CONFIG_APUS) += apus_setup.o 5obj-$(CONFIG_APUS) += apus_setup.o
9ifeq ($(CONFIG_APUS),y) 6ifeq ($(CONFIG_APUS),y)
10obj-$(CONFIG_PCI) += apus_pci.o 7obj-$(CONFIG_PCI) += apus_pci.o
11endif 8endif
12obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \
13 chrp_pegasos_eth.o
14ifeq ($(CONFIG_PPC_CHRP),y)
15obj-$(CONFIG_NVRAM) += chrp_nvram.o
16endif
17obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o 9obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
18obj-$(CONFIG_PREP_RESIDUAL) += residual.o 10obj-$(CONFIG_PREP_RESIDUAL) += residual.o
19obj-$(CONFIG_PQ2ADS) += pq2ads.o 11obj-$(CONFIG_PQ2ADS) += pq2ads.o
@@ -40,7 +32,3 @@ obj-$(CONFIG_EV64360) += ev64360.o
40obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o 32obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
41obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o 33obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
42obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o 34obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
43
44ifeq ($(CONFIG_SMP),y)
45obj-$(CONFIG_PPC_CHRP) += chrp_smp.o
46endif
diff --git a/arch/ppc/platforms/chrp_nvram.c b/arch/ppc/platforms/chrp_nvram.c
deleted file mode 100644
index 465ba9b090ef..000000000000
--- a/arch/ppc/platforms/chrp_nvram.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * /dev/nvram driver for PPC
10 *
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <asm/uaccess.h>
18#include <asm/prom.h>
19#include <asm/machdep.h>
20
21static unsigned int nvram_size;
22static unsigned char nvram_buf[4];
23static DEFINE_SPINLOCK(nvram_lock);
24
25static unsigned char chrp_nvram_read(int addr)
26{
27 unsigned long done, flags;
28 unsigned char ret;
29
30 if (addr >= nvram_size) {
31 printk(KERN_DEBUG "%s: read addr %d > nvram_size %u\n",
32 current->comm, addr, nvram_size);
33 return 0xff;
34 }
35 spin_lock_irqsave(&nvram_lock, flags);
36 if ((call_rtas("nvram-fetch", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done)
37 ret = 0xff;
38 else
39 ret = nvram_buf[0];
40 spin_unlock_irqrestore(&nvram_lock, flags);
41
42 return ret;
43}
44
45static void chrp_nvram_write(int addr, unsigned char val)
46{
47 unsigned long done, flags;
48
49 if (addr >= nvram_size) {
50 printk(KERN_DEBUG "%s: write addr %d > nvram_size %u\n",
51 current->comm, addr, nvram_size);
52 return;
53 }
54 spin_lock_irqsave(&nvram_lock, flags);
55 nvram_buf[0] = val;
56 if ((call_rtas("nvram-store", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done)
57 printk(KERN_DEBUG "rtas IO error storing 0x%02x at %d", val, addr);
58 spin_unlock_irqrestore(&nvram_lock, flags);
59}
60
61void __init chrp_nvram_init(void)
62{
63 struct device_node *nvram;
64 unsigned int *nbytes_p, proplen;
65
66 nvram = of_find_node_by_type(NULL, "nvram");
67 if (nvram == NULL)
68 return;
69
70 nbytes_p = (unsigned int *)get_property(nvram, "#bytes", &proplen);
71 if (nbytes_p == NULL || proplen != sizeof(unsigned int))
72 return;
73
74 nvram_size = *nbytes_p;
75
76 printk(KERN_INFO "CHRP nvram contains %u bytes\n", nvram_size);
77 of_node_put(nvram);
78
79 ppc_md.nvram_read_val = chrp_nvram_read;
80 ppc_md.nvram_write_val = chrp_nvram_write;
81
82 return;
83}
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
deleted file mode 100644
index c7fe6182bb77..000000000000
--- a/arch/ppc/platforms/chrp_pci.c
+++ /dev/null
@@ -1,309 +0,0 @@
1/*
2 * CHRP pci routines.
3 */
4
5#include <linux/config.h>
6#include <linux/kernel.h>
7#include <linux/pci.h>
8#include <linux/delay.h>
9#include <linux/string.h>
10#include <linux/init.h>
11#include <linux/ide.h>
12
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/irq.h>
16#include <asm/hydra.h>
17#include <asm/prom.h>
18#include <asm/gg2.h>
19#include <asm/machdep.h>
20#include <asm/sections.h>
21#include <asm/pci-bridge.h>
22#include <asm/open_pic.h>
23
24/* LongTrail */
25void __iomem *gg2_pci_config_base;
26
27/*
28 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
29 * limit the bus number to 3 bits
30 */
31
32int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
33 int len, u32 *val)
34{
35 volatile void __iomem *cfg_data;
36 struct pci_controller *hose = bus->sysdata;
37
38 if (bus->number > 7)
39 return PCIBIOS_DEVICE_NOT_FOUND;
40 /*
41 * Note: the caller has already checked that off is
42 * suitably aligned and that len is 1, 2 or 4.
43 */
44 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
45 switch (len) {
46 case 1:
47 *val = in_8(cfg_data);
48 break;
49 case 2:
50 *val = in_le16(cfg_data);
51 break;
52 default:
53 *val = in_le32(cfg_data);
54 break;
55 }
56 return PCIBIOS_SUCCESSFUL;
57}
58
59int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
60 int len, u32 val)
61{
62 volatile void __iomem *cfg_data;
63 struct pci_controller *hose = bus->sysdata;
64
65 if (bus->number > 7)
66 return PCIBIOS_DEVICE_NOT_FOUND;
67 /*
68 * Note: the caller has already checked that off is
69 * suitably aligned and that len is 1, 2 or 4.
70 */
71 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
72 switch (len) {
73 case 1:
74 out_8(cfg_data, val);
75 break;
76 case 2:
77 out_le16(cfg_data, val);
78 break;
79 default:
80 out_le32(cfg_data, val);
81 break;
82 }
83 return PCIBIOS_SUCCESSFUL;
84}
85
86static struct pci_ops gg2_pci_ops =
87{
88 gg2_read_config,
89 gg2_write_config
90};
91
92/*
93 * Access functions for PCI config space using RTAS calls.
94 */
95int
96rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
97 int len, u32 *val)
98{
99 struct pci_controller *hose = bus->sysdata;
100 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
101 | (((bus->number - hose->first_busno) & 0xff) << 16)
102 | (hose->index << 24);
103 unsigned long ret = ~0UL;
104 int rval;
105
106 rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len);
107 *val = ret;
108 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
109}
110
111int
112rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
113 int len, u32 val)
114{
115 struct pci_controller *hose = bus->sysdata;
116 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
117 | (((bus->number - hose->first_busno) & 0xff) << 16)
118 | (hose->index << 24);
119 int rval;
120
121 rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
122 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
123}
124
125static struct pci_ops rtas_pci_ops =
126{
127 rtas_read_config,
128 rtas_write_config
129};
130
131volatile struct Hydra __iomem *Hydra = NULL;
132
133int __init
134hydra_init(void)
135{
136 struct device_node *np;
137
138 np = find_devices("mac-io");
139 if (np == NULL || np->n_addrs == 0)
140 return 0;
141 Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
142 printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
143 printk("Hydra Feature_Control was %x",
144 in_le32(&Hydra->Feature_Control));
145 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
146 HYDRA_FC_SCSI_CELL_EN |
147 HYDRA_FC_SCCA_ENABLE |
148 HYDRA_FC_SCCB_ENABLE |
149 HYDRA_FC_ARB_BYPASS |
150 HYDRA_FC_MPIC_ENABLE |
151 HYDRA_FC_SLOW_SCC_PCLK |
152 HYDRA_FC_MPIC_IS_MASTER));
153 printk(", now %x\n", in_le32(&Hydra->Feature_Control));
154 return 1;
155}
156
157void __init
158chrp_pcibios_fixup(void)
159{
160 struct pci_dev *dev = NULL;
161 struct device_node *np;
162
163 /* PCI interrupts are controlled by the OpenPIC */
164 for_each_pci_dev(dev) {
165 np = pci_device_to_OF_node(dev);
166 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
167 dev->irq = np->intrs[0].line;
168 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
169 }
170}
171
172#define PRG_CL_RESET_VALID 0x00010000
173
174static void __init
175setup_python(struct pci_controller *hose, struct device_node *dev)
176{
177 u32 __iomem *reg;
178 u32 val;
179 unsigned long addr = dev->addrs[0].address;
180
181 setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
182
183 /* Clear the magic go-slow bit */
184 reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
185 val = in_be32(&reg[12]);
186 if (val & PRG_CL_RESET_VALID) {
187 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
188 in_be32(&reg[12]);
189 }
190 iounmap(reg);
191}
192
193/* Marvell Discovery II based Pegasos 2 */
194static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
195{
196 struct device_node *root = find_path_device("/");
197 struct device_node *rtas;
198
199 rtas = of_find_node_by_name (root, "rtas");
200 if (rtas) {
201 hose->ops = &rtas_pci_ops;
202 } else {
203 printk ("RTAS supporting Pegasos OF not found, please upgrade"
204 " your firmware\n");
205 }
206 pci_assign_all_buses = 1;
207}
208
209void __init
210chrp_find_bridges(void)
211{
212 struct device_node *dev;
213 int *bus_range;
214 int len, index = -1;
215 struct pci_controller *hose;
216 unsigned int *dma;
217 char *model, *machine;
218 int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
219 struct device_node *root = find_path_device("/");
220
221 /*
222 * The PCI host bridge nodes on some machines don't have
223 * properties to adequately identify them, so we have to
224 * look at what sort of machine this is as well.
225 */
226 machine = get_property(root, "model", NULL);
227 if (machine != NULL) {
228 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
229 is_mot = strncmp(machine, "MOT", 3) == 0;
230 if (strncmp(machine, "Pegasos2", 8) == 0)
231 is_pegasos = 2;
232 else if (strncmp(machine, "Pegasos", 7) == 0)
233 is_pegasos = 1;
234 }
235 for (dev = root->child; dev != NULL; dev = dev->sibling) {
236 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
237 continue;
238 ++index;
239 /* The GG2 bridge on the LongTrail doesn't have an address */
240 if (dev->n_addrs < 1 && !is_longtrail) {
241 printk(KERN_WARNING "Can't use %s: no address\n",
242 dev->full_name);
243 continue;
244 }
245 bus_range = (int *) get_property(dev, "bus-range", &len);
246 if (bus_range == NULL || len < 2 * sizeof(int)) {
247 printk(KERN_WARNING "Can't get bus-range for %s\n",
248 dev->full_name);
249 continue;
250 }
251 if (bus_range[1] == bus_range[0])
252 printk(KERN_INFO "PCI bus %d", bus_range[0]);
253 else
254 printk(KERN_INFO "PCI buses %d..%d",
255 bus_range[0], bus_range[1]);
256 printk(" controlled by %s", dev->type);
257 if (dev->n_addrs > 0)
258 printk(" at %x", dev->addrs[0].address);
259 printk("\n");
260
261 hose = pcibios_alloc_controller();
262 if (!hose) {
263 printk("Can't allocate PCI controller structure for %s\n",
264 dev->full_name);
265 continue;
266 }
267 hose->arch_data = dev;
268 hose->first_busno = bus_range[0];
269 hose->last_busno = bus_range[1];
270
271 model = get_property(dev, "model", NULL);
272 if (model == NULL)
273 model = "<none>";
274 if (device_is_compatible(dev, "IBM,python")) {
275 setup_python(hose, dev);
276 } else if (is_mot
277 || strncmp(model, "Motorola, Grackle", 17) == 0) {
278 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
279 } else if (is_longtrail) {
280 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
281 hose->ops = &gg2_pci_ops;
282 hose->cfg_data = p;
283 gg2_pci_config_base = p;
284 } else if (is_pegasos == 1) {
285 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
286 } else if (is_pegasos == 2) {
287 setup_peg2(hose, dev);
288 } else {
289 printk("No methods for %s (model %s), using RTAS\n",
290 dev->full_name, model);
291 hose->ops = &rtas_pci_ops;
292 }
293
294 pci_process_bridge_OF_ranges(hose, dev, index == 0);
295
296 /* check the first bridge for a property that we can
297 use to set pci_dram_offset */
298 dma = (unsigned int *)
299 get_property(dev, "ibm,dma-ranges", &len);
300 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
301 pci_dram_offset = dma[2] - dma[3];
302 printk("pci_dram_offset = %lx\n", pci_dram_offset);
303 }
304 }
305
306 /* Do not fixup interrupts from OF tree on pegasos */
307 if (is_pegasos == 0)
308 ppc_md.pcibios_fixup = chrp_pcibios_fixup;
309}
diff --git a/arch/ppc/platforms/chrp_pegasos_eth.c b/arch/ppc/platforms/chrp_pegasos_eth.c
deleted file mode 100644
index 9305c8aa1373..000000000000
--- a/arch/ppc/platforms/chrp_pegasos_eth.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
3 * Thanks to :
4 * Dale Farnsworth <dale@farnsworth.org>
5 * Mark A. Greer <mgreer@mvista.com>
6 * Nicolas DET <nd@bplan-gmbh.de>
7 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
8 * And anyone else who helped me on this.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/ioport.h>
14#include <linux/platform_device.h>
15#include <linux/mv643xx.h>
16#include <linux/pci.h>
17
18#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
19#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
20#define PEGASOS2_SRAM_BASE (0xf2000000)
21#define PEGASOS2_SRAM_SIZE (256*1024)
22
23#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
24#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
25
26
27#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
28#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
29
30#undef BE_VERBOSE
31
32static struct resource mv643xx_eth_shared_resources[] = {
33 [0] = {
34 .name = "ethernet shared base",
35 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
36 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
37 MV643XX_ETH_SHARED_REGS_SIZE - 1,
38 .flags = IORESOURCE_MEM,
39 },
40};
41
42static struct platform_device mv643xx_eth_shared_device = {
43 .name = MV643XX_ETH_SHARED_NAME,
44 .id = 0,
45 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
46 .resource = mv643xx_eth_shared_resources,
47};
48
49static struct resource mv643xx_eth0_resources[] = {
50 [0] = {
51 .name = "eth0 irq",
52 .start = 9,
53 .end = 9,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58
59static struct mv643xx_eth_platform_data eth0_pd = {
60 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
61 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
62 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
63
64 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
65 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
66 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
67};
68
69static struct platform_device eth0_device = {
70 .name = MV643XX_ETH_NAME,
71 .id = 0,
72 .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
73 .resource = mv643xx_eth0_resources,
74 .dev = {
75 .platform_data = &eth0_pd,
76 },
77};
78
79static struct resource mv643xx_eth1_resources[] = {
80 [0] = {
81 .name = "eth1 irq",
82 .start = 9,
83 .end = 9,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct mv643xx_eth_platform_data eth1_pd = {
89 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
90 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
91 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
92
93 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
94 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
95 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
96};
97
98static struct platform_device eth1_device = {
99 .name = MV643XX_ETH_NAME,
100 .id = 1,
101 .num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
102 .resource = mv643xx_eth1_resources,
103 .dev = {
104 .platform_data = &eth1_pd,
105 },
106};
107
108static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
109 &mv643xx_eth_shared_device,
110 &eth0_device,
111 &eth1_device,
112};
113
114/***********/
115/***********/
116#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
117#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
118
119static void __iomem *mv643xx_reg_base;
120
121static int Enable_SRAM(void)
122{
123 u32 ALong;
124
125 if (mv643xx_reg_base == NULL)
126 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
127 PEGASOS2_MARVELL_REGSIZE);
128
129 if (mv643xx_reg_base == NULL)
130 return -ENOMEM;
131
132#ifdef BE_VERBOSE
133 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
134 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
135#endif
136
137 MV_WRITE(MV64340_SRAM_CONFIG, 0);
138
139 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
140
141 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
142 ALong &= ~(1 << 19);
143 MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
144
145 ALong = 0x02;
146 ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
147 MV_WRITE(MV643XX_ETH_BAR_4, ALong);
148
149 MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
150
151 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
152 ALong &= ~(1 << 4);
153 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
154
155#ifdef BE_VERBOSE
156 printk("Pegasos II/Marvell MV64361: register unmapped\n");
157 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
158#endif
159
160 iounmap(mv643xx_reg_base);
161 mv643xx_reg_base = NULL;
162
163 return 1;
164}
165
166
167/***********/
168/***********/
169int mv643xx_eth_add_pds(void)
170{
171 int ret = 0;
172 static struct pci_device_id pci_marvell_mv64360[] = {
173 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
174 { }
175 };
176
177#ifdef BE_VERBOSE
178 printk("Pegasos II/Marvell MV64361: init\n");
179#endif
180
181 if (pci_dev_present(pci_marvell_mv64360)) {
182 ret = platform_add_devices(mv643xx_eth_pd_devs,
183 ARRAY_SIZE(mv643xx_eth_pd_devs));
184
185 if ( Enable_SRAM() < 0)
186 {
187 eth0_pd.tx_sram_addr = 0;
188 eth0_pd.tx_sram_size = 0;
189 eth0_pd.rx_sram_addr = 0;
190 eth0_pd.rx_sram_size = 0;
191
192 eth1_pd.tx_sram_addr = 0;
193 eth1_pd.tx_sram_size = 0;
194 eth1_pd.rx_sram_addr = 0;
195 eth1_pd.rx_sram_size = 0;
196
197#ifdef BE_VERBOSE
198 printk("Pegasos II/Marvell MV64361: Can't enable the "
199 "SRAM\n");
200#endif
201 }
202 }
203
204#ifdef BE_VERBOSE
205 printk("Pegasos II/Marvell MV64361: init is over\n");
206#endif
207
208 return ret;
209}
210
211device_initcall(mv643xx_eth_add_pds);
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
deleted file mode 100644
index f9fd3f4f8e2e..000000000000
--- a/arch/ppc/platforms/chrp_setup.c
+++ /dev/null
@@ -1,669 +0,0 @@
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
5 */
6
7/*
8 * bootup setup stuff..
9 */
10
11#include <linux/config.h>
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/stddef.h>
17#include <linux/unistd.h>
18#include <linux/ptrace.h>
19#include <linux/slab.h>
20#include <linux/user.h>
21#include <linux/a.out.h>
22#include <linux/tty.h>
23#include <linux/major.h>
24#include <linux/interrupt.h>
25#include <linux/reboot.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/version.h>
29#include <linux/adb.h>
30#include <linux/module.h>
31#include <linux/delay.h>
32#include <linux/ide.h>
33#include <linux/console.h>
34#include <linux/seq_file.h>
35#include <linux/root_dev.h>
36#include <linux/initrd.h>
37#include <linux/module.h>
38
39#include <asm/io.h>
40#include <asm/pgtable.h>
41#include <asm/prom.h>
42#include <asm/gg2.h>
43#include <asm/pci-bridge.h>
44#include <asm/dma.h>
45#include <asm/machdep.h>
46#include <asm/irq.h>
47#include <asm/hydra.h>
48#include <asm/sections.h>
49#include <asm/time.h>
50#include <asm/btext.h>
51#include <asm/i8259.h>
52#include <asm/open_pic.h>
53#include <asm/xmon.h>
54#include "mem_pieces.h"
55
56unsigned long chrp_get_rtc_time(void);
57int chrp_set_rtc_time(unsigned long nowtime);
58void chrp_calibrate_decr(void);
59long chrp_time_init(void);
60
61void chrp_find_bridges(void);
62void chrp_event_scan(void);
63void rtas_display_progress(char *, unsigned short);
64void rtas_indicator_progress(char *, unsigned short);
65void btext_progress(char *, unsigned short);
66
67extern int of_show_percpuinfo(struct seq_file *, int);
68
69int _chrp_type;
70EXPORT_SYMBOL(_chrp_type);
71
72/*
73 * XXX this should be in xmon.h, but putting it there means xmon.h
74 * has to include <linux/interrupt.h> (to get irqreturn_t), which
75 * causes all sorts of problems. -- paulus
76 */
77extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
78
79extern dev_t boot_dev;
80
81extern PTE *Hash, *Hash_end;
82extern unsigned long Hash_size, Hash_mask;
83extern int probingmem;
84extern unsigned long loops_per_jiffy;
85static int max_width;
86
87#ifdef CONFIG_SMP
88extern struct smp_ops_t chrp_smp_ops;
89#endif
90
91static const char *gg2_memtypes[4] = {
92 "FPM", "SDRAM", "EDO", "BEDO"
93};
94static const char *gg2_cachesizes[4] = {
95 "256 KB", "512 KB", "1 MB", "Reserved"
96};
97static const char *gg2_cachetypes[4] = {
98 "Asynchronous", "Reserved", "Flow-Through Synchronous",
99 "Pipelined Synchronous"
100};
101static const char *gg2_cachemodes[4] = {
102 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
103};
104
105int
106chrp_show_cpuinfo(struct seq_file *m)
107{
108 int i, sdramen;
109 unsigned int t;
110 struct device_node *root;
111 const char *model = "";
112
113 root = find_path_device("/");
114 if (root)
115 model = get_property(root, "model", NULL);
116 seq_printf(m, "machine\t\t: CHRP %s\n", model);
117
118 /* longtrail (goldengate) stuff */
119 if (!strncmp(model, "IBM,LongTrail", 13)) {
120 /* VLSI VAS96011/12 `Golden Gate 2' */
121 /* Memory banks */
122 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
123 >>31) & 1;
124 for (i = 0; i < (sdramen ? 4 : 6); i++) {
125 t = in_le32(gg2_pci_config_base+
126 GG2_PCI_DRAM_BANK0+
127 i*4);
128 if (!(t & 1))
129 continue;
130 switch ((t>>8) & 0x1f) {
131 case 0x1f:
132 model = "4 MB";
133 break;
134 case 0x1e:
135 model = "8 MB";
136 break;
137 case 0x1c:
138 model = "16 MB";
139 break;
140 case 0x18:
141 model = "32 MB";
142 break;
143 case 0x10:
144 model = "64 MB";
145 break;
146 case 0x00:
147 model = "128 MB";
148 break;
149 default:
150 model = "Reserved";
151 break;
152 }
153 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
154 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
155 }
156 /* L2 cache */
157 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
158 seq_printf(m, "board l2\t: %s %s (%s)\n",
159 gg2_cachesizes[(t>>7) & 3],
160 gg2_cachetypes[(t>>2) & 3],
161 gg2_cachemodes[t & 3]);
162 }
163 return 0;
164}
165
166/*
167 * Fixes for the National Semiconductor PC78308VUL SuperI/O
168 *
169 * Some versions of Open Firmware incorrectly initialize the IRQ settings
170 * for keyboard and mouse
171 */
172static inline void __init sio_write(u8 val, u8 index)
173{
174 outb(index, 0x15c);
175 outb(val, 0x15d);
176}
177
178static inline u8 __init sio_read(u8 index)
179{
180 outb(index, 0x15c);
181 return inb(0x15d);
182}
183
184static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
185 u8 type)
186{
187 u8 level0, type0, active;
188
189 /* select logical device */
190 sio_write(device, 0x07);
191 active = sio_read(0x30);
192 level0 = sio_read(0x70);
193 type0 = sio_read(0x71);
194 if (level0 != level || type0 != type || !active) {
195 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
196 "remapping to level %d, type %d, active\n",
197 name, level0, type0, !active ? "in" : "", level, type);
198 sio_write(0x01, 0x30);
199 sio_write(level, 0x70);
200 sio_write(type, 0x71);
201 }
202}
203
204static void __init sio_init(void)
205{
206 struct device_node *root;
207
208 if ((root = find_path_device("/")) &&
209 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
210 /* logical device 0 (KBC/Keyboard) */
211 sio_fixup_irq("keyboard", 0, 1, 2);
212 /* select logical device 1 (KBC/Mouse) */
213 sio_fixup_irq("mouse", 1, 12, 2);
214 }
215}
216
217
218static void __init pegasos_set_l2cr(void)
219{
220 struct device_node *np;
221
222 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
223 if (_chrp_type != _CHRP_Pegasos)
224 return;
225
226 /* Enable L2 cache if needed */
227 np = find_type_devices("cpu");
228 if (np != NULL) {
229 unsigned int *l2cr = (unsigned int *)
230 get_property (np, "l2cr", NULL);
231 if (l2cr == NULL) {
232 printk ("Pegasos l2cr : no cpu l2cr property found\n");
233 return;
234 }
235 if (!((*l2cr) & 0x80000000)) {
236 printk ("Pegasos l2cr : L2 cache was not active, "
237 "activating\n");
238 _set_L2CR(0);
239 _set_L2CR((*l2cr) | 0x80000000);
240 }
241 }
242}
243
244void __init chrp_setup_arch(void)
245{
246 struct device_node *device;
247
248 /* init to some ~sane value until calibrate_delay() runs */
249 loops_per_jiffy = 50000000/HZ;
250
251#ifdef CONFIG_BLK_DEV_INITRD
252 /* this is fine for chrp */
253 initrd_below_start_ok = 1;
254
255 if (initrd_start)
256 ROOT_DEV = Root_RAM0;
257 else
258#endif
259 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
260
261 /* On pegasos, enable the L2 cache if not already done by OF */
262 pegasos_set_l2cr();
263
264 /* Lookup PCI host bridges */
265 chrp_find_bridges();
266
267#ifndef CONFIG_PPC64BRIDGE
268 /*
269 * Temporary fixes for PCI devices.
270 * -- Geert
271 */
272 hydra_init(); /* Mac I/O */
273
274#endif /* CONFIG_PPC64BRIDGE */
275
276 /*
277 * Fix the Super I/O configuration
278 */
279 sio_init();
280
281 /* Get the event scan rate for the rtas so we know how
282 * often it expects a heartbeat. -- Cort
283 */
284 if ( rtas_data ) {
285 struct property *p;
286 device = find_devices("rtas");
287 for ( p = device->properties;
288 p && strncmp(p->name, "rtas-event-scan-rate", 20);
289 p = p->next )
290 /* nothing */ ;
291 if ( p && *(unsigned long *)p->value ) {
292 ppc_md.heartbeat = chrp_event_scan;
293 ppc_md.heartbeat_reset = (HZ/(*(unsigned long *)p->value)*30)-1;
294 ppc_md.heartbeat_count = 1;
295 printk("RTAS Event Scan Rate: %lu (%lu jiffies)\n",
296 *(unsigned long *)p->value, ppc_md.heartbeat_reset );
297 }
298 }
299
300 pci_create_OF_bus_map();
301}
302
303void
304chrp_event_scan(void)
305{
306 unsigned char log[1024];
307 unsigned long ret = 0;
308 /* XXX: we should loop until the hardware says no more error logs -- Cort */
309 call_rtas( "event-scan", 4, 1, &ret, 0xffffffff, 0,
310 __pa(log), 1024 );
311 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
312}
313
314void
315chrp_restart(char *cmd)
316{
317 printk("RTAS system-reboot returned %d\n",
318 call_rtas("system-reboot", 0, 1, NULL));
319 for (;;);
320}
321
322void
323chrp_power_off(void)
324{
325 /* allow power on only with power button press */
326 printk("RTAS power-off returned %d\n",
327 call_rtas("power-off", 2, 1, NULL,0xffffffff,0xffffffff));
328 for (;;);
329}
330
331void
332chrp_halt(void)
333{
334 chrp_power_off();
335}
336
337/*
338 * Finds the open-pic node and sets OpenPIC_Addr based on its reg property.
339 * Then checks if it has an interrupt-ranges property. If it does then
340 * we have a distributed open-pic, so call openpic_set_sources to tell
341 * the openpic code where to find the interrupt source registers.
342 */
343static void __init chrp_find_openpic(void)
344{
345 struct device_node *np;
346 int len, i;
347 unsigned int *iranges;
348 void __iomem *isu;
349
350 np = find_type_devices("open-pic");
351 if (np == NULL || np->n_addrs == 0)
352 return;
353 printk(KERN_INFO "OpenPIC at %x (size %x)\n",
354 np->addrs[0].address, np->addrs[0].size);
355 OpenPIC_Addr = ioremap(np->addrs[0].address, 0x40000);
356 if (OpenPIC_Addr == NULL) {
357 printk(KERN_ERR "Failed to map OpenPIC!\n");
358 return;
359 }
360
361 iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
362 if (iranges == NULL || len < 2 * sizeof(unsigned int))
363 return; /* not distributed */
364
365 /*
366 * The first pair of cells in interrupt-ranges refers to the
367 * IDU; subsequent pairs refer to the ISUs.
368 */
369 len /= 2 * sizeof(unsigned int);
370 if (np->n_addrs < len) {
371 printk(KERN_ERR "Insufficient addresses for distributed"
372 " OpenPIC (%d < %d)\n", np->n_addrs, len);
373 return;
374 }
375 if (iranges[1] != 0) {
376 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
377 iranges[0], iranges[0] + iranges[1] - 1);
378 openpic_set_sources(iranges[0], iranges[1], NULL);
379 }
380 for (i = 1; i < len; ++i) {
381 iranges += 2;
382 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x (%x)\n",
383 iranges[0], iranges[0] + iranges[1] - 1,
384 np->addrs[i].address, np->addrs[i].size);
385 isu = ioremap(np->addrs[i].address, np->addrs[i].size);
386 if (isu != NULL)
387 openpic_set_sources(iranges[0], iranges[1], isu);
388 else
389 printk(KERN_ERR "Failed to map OpenPIC ISU at %x!\n",
390 np->addrs[i].address);
391 }
392}
393
394#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
395static struct irqaction xmon_irqaction = {
396 .handler = xmon_irq,
397 .mask = CPU_MASK_NONE,
398 .name = "XMON break",
399};
400#endif
401
402void __init chrp_init_IRQ(void)
403{
404 struct device_node *np;
405 unsigned long chrp_int_ack = 0;
406 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
407#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
408 struct device_node *kbd;
409#endif
410
411 for (np = find_devices("pci"); np != NULL; np = np->next) {
412 unsigned int *addrp = (unsigned int *)
413 get_property(np, "8259-interrupt-acknowledge", NULL);
414
415 if (addrp == NULL)
416 continue;
417 chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
418 break;
419 }
420 if (np == NULL)
421 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
422
423 chrp_find_openpic();
424
425 if (OpenPIC_Addr) {
426 prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
427 OpenPIC_InitSenses = init_senses;
428 OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
429
430 openpic_init(NUM_8259_INTERRUPTS);
431 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
432 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
433 i8259_irq);
434
435 }
436 i8259_init(chrp_int_ack, 0);
437
438#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
439 /* see if there is a keyboard in the device tree
440 with a parent of type "adb" */
441 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
442 if (kbd->parent && kbd->parent->type
443 && strcmp(kbd->parent->type, "adb") == 0)
444 break;
445 if (kbd)
446 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
447#endif
448}
449
450void __init
451chrp_init2(void)
452{
453#ifdef CONFIG_NVRAM
454 chrp_nvram_init();
455#endif
456
457 request_region(0x20,0x20,"pic1");
458 request_region(0xa0,0x20,"pic2");
459 request_region(0x00,0x20,"dma1");
460 request_region(0x40,0x20,"timer");
461 request_region(0x80,0x10,"dma page reg");
462 request_region(0xc0,0x20,"dma2");
463
464 if (ppc_md.progress)
465 ppc_md.progress(" Have fun! ", 0x7777);
466}
467
468static struct device_node *memory_node;
469
470static int __init get_mem_prop(char *name, struct mem_pieces *mp)
471{
472 struct reg_property *rp;
473 int i, s;
474 unsigned int *ip;
475 int nac = prom_n_addr_cells(memory_node);
476 int nsc = prom_n_size_cells(memory_node);
477
478 ip = (unsigned int *) get_property(memory_node, name, &s);
479 if (ip == NULL) {
480 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
481 name);
482 return 0;
483 }
484 s /= (nsc + nac) * 4;
485 rp = mp->regions;
486 for (i = 0; i < s; ++i, ip += nac+nsc) {
487 if (nac >= 2 && ip[nac-2] != 0)
488 continue;
489 rp->address = ip[nac-1];
490 if (nsc >= 2 && ip[nac+nsc-2] != 0)
491 rp->size = ~0U;
492 else
493 rp->size = ip[nac+nsc-1];
494 ++rp;
495 }
496 mp->n_regions = rp - mp->regions;
497
498 /* Make sure the pieces are sorted. */
499 mem_pieces_sort(mp);
500 mem_pieces_coalesce(mp);
501 return 1;
502}
503
504static unsigned long __init chrp_find_end_of_memory(void)
505{
506 unsigned long a, total;
507 struct mem_pieces phys_mem;
508
509 /*
510 * Find out where physical memory is, and check that it
511 * starts at 0 and is contiguous. It seems that RAM is
512 * always physically contiguous on Power Macintoshes.
513 *
514 * Supporting discontiguous physical memory isn't hard,
515 * it just makes the virtual <-> physical mapping functions
516 * more complicated (or else you end up wasting space
517 * in mem_map).
518 */
519 memory_node = find_devices("memory");
520 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
521 || phys_mem.n_regions == 0)
522 panic("No RAM??");
523 a = phys_mem.regions[0].address;
524 if (a != 0)
525 panic("RAM doesn't start at physical address 0");
526 total = phys_mem.regions[0].size;
527
528 if (phys_mem.n_regions > 1) {
529 printk("RAM starting at 0x%x is not contiguous\n",
530 phys_mem.regions[1].address);
531 printk("Using RAM from 0 to 0x%lx\n", total-1);
532 }
533
534 return total;
535}
536
537void __init
538chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
539 unsigned long r6, unsigned long r7)
540{
541 struct device_node *root = find_path_device ("/");
542 char *machine = NULL;
543
544#ifdef CONFIG_BLK_DEV_INITRD
545 /* take care of initrd if we have one */
546 if ( r6 )
547 {
548 initrd_start = r6 + KERNELBASE;
549 initrd_end = r6 + r7 + KERNELBASE;
550 }
551#endif /* CONFIG_BLK_DEV_INITRD */
552
553 ISA_DMA_THRESHOLD = ~0L;
554 DMA_MODE_READ = 0x44;
555 DMA_MODE_WRITE = 0x48;
556 isa_io_base = CHRP_ISA_IO_BASE; /* default value */
557 ppc_do_canonicalize_irqs = 1;
558
559 if (root)
560 machine = get_property(root, "model", NULL);
561 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
562 _chrp_type = _CHRP_Pegasos;
563 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
564 _chrp_type = _CHRP_IBM;
565 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
566 _chrp_type = _CHRP_Motorola;
567 } else {
568 /* Let's assume it is an IBM chrp if all else fails */
569 _chrp_type = _CHRP_IBM;
570 }
571
572 ppc_md.setup_arch = chrp_setup_arch;
573 ppc_md.show_percpuinfo = of_show_percpuinfo;
574 ppc_md.show_cpuinfo = chrp_show_cpuinfo;
575
576 ppc_md.init_IRQ = chrp_init_IRQ;
577 if (_chrp_type == _CHRP_Pegasos)
578 ppc_md.get_irq = i8259_irq;
579 else
580 ppc_md.get_irq = openpic_get_irq;
581
582 ppc_md.init = chrp_init2;
583
584 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
585
586 ppc_md.restart = chrp_restart;
587 ppc_md.power_off = chrp_power_off;
588 ppc_md.halt = chrp_halt;
589
590 ppc_md.time_init = chrp_time_init;
591 ppc_md.set_rtc_time = chrp_set_rtc_time;
592 ppc_md.get_rtc_time = chrp_get_rtc_time;
593 ppc_md.calibrate_decr = chrp_calibrate_decr;
594
595 ppc_md.find_end_of_memory = chrp_find_end_of_memory;
596
597 if (rtas_data) {
598 struct device_node *rtas;
599 unsigned int *p;
600
601 rtas = find_devices("rtas");
602 if (rtas != NULL) {
603 if (get_property(rtas, "display-character", NULL)) {
604 ppc_md.progress = rtas_display_progress;
605 p = (unsigned int *) get_property
606 (rtas, "ibm,display-line-length", NULL);
607 if (p)
608 max_width = *p;
609 } else if (get_property(rtas, "set-indicator", NULL))
610 ppc_md.progress = rtas_indicator_progress;
611 }
612 }
613#ifdef CONFIG_BOOTX_TEXT
614 if (ppc_md.progress == NULL && boot_text_mapped)
615 ppc_md.progress = btext_progress;
616#endif
617
618#ifdef CONFIG_SMP
619 smp_ops = &chrp_smp_ops;
620#endif /* CONFIG_SMP */
621
622 /*
623 * Print the banner, then scroll down so boot progress
624 * can be printed. -- Cort
625 */
626 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
627}
628
629void
630rtas_display_progress(char *s, unsigned short hex)
631{
632 int width;
633 char *os = s;
634
635 if ( call_rtas( "display-character", 1, 1, NULL, '\r' ) )
636 return;
637
638 width = max_width;
639 while ( *os )
640 {
641 if ( (*os == '\n') || (*os == '\r') )
642 width = max_width;
643 else
644 width--;
645 call_rtas( "display-character", 1, 1, NULL, *os++ );
646 /* if we overwrite the screen length */
647 if ( width == 0 )
648 while ( (*os != 0) && (*os != '\n') && (*os != '\r') )
649 os++;
650 }
651
652 /*while ( width-- > 0 )*/
653 call_rtas( "display-character", 1, 1, NULL, ' ' );
654}
655
656void
657rtas_indicator_progress(char *s, unsigned short hex)
658{
659 call_rtas("set-indicator", 3, 1, NULL, 6, 0, hex);
660}
661
662#ifdef CONFIG_BOOTX_TEXT
663void
664btext_progress(char *s, unsigned short hex)
665{
666 prom_print(s);
667 prom_print("\n");
668}
669#endif /* CONFIG_BOOTX_TEXT */
diff --git a/arch/ppc/platforms/chrp_smp.c b/arch/ppc/platforms/chrp_smp.c
deleted file mode 100644
index 97e539557ecb..000000000000
--- a/arch/ppc/platforms/chrp_smp.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Smp support for CHRP machines.
3 *
4 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
5 * deal of code from the sparc and intel versions.
6 *
7 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
8 *
9 */
10
11#include <linux/config.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15#include <linux/smp_lock.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18#include <linux/delay.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21
22#include <asm/ptrace.h>
23#include <asm/atomic.h>
24#include <asm/irq.h>
25#include <asm/page.h>
26#include <asm/pgtable.h>
27#include <asm/sections.h>
28#include <asm/io.h>
29#include <asm/prom.h>
30#include <asm/smp.h>
31#include <asm/residual.h>
32#include <asm/time.h>
33#include <asm/open_pic.h>
34#include <asm/machdep.h>
35
36extern unsigned long smp_chrp_cpu_nr;
37
38static int __init
39smp_chrp_probe(void)
40{
41 if (smp_chrp_cpu_nr > 1)
42 openpic_request_IPIs();
43
44 return smp_chrp_cpu_nr;
45}
46
47static void __devinit
48smp_chrp_kick_cpu(int nr)
49{
50 *(unsigned long *)KERNELBASE = nr;
51 asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
52}
53
54static void __devinit
55smp_chrp_setup_cpu(int cpu_nr)
56{
57 if (OpenPIC_Addr)
58 do_openpic_setup_cpu();
59}
60
61static DEFINE_SPINLOCK(timebase_lock);
62static unsigned int timebase_upper = 0, timebase_lower = 0;
63
64void __devinit
65smp_chrp_give_timebase(void)
66{
67 spin_lock(&timebase_lock);
68 call_rtas("freeze-time-base", 0, 1, NULL);
69 timebase_upper = get_tbu();
70 timebase_lower = get_tbl();
71 spin_unlock(&timebase_lock);
72
73 while (timebase_upper || timebase_lower)
74 barrier();
75 call_rtas("thaw-time-base", 0, 1, NULL);
76}
77
78void __devinit
79smp_chrp_take_timebase(void)
80{
81 while (!(timebase_upper || timebase_lower))
82 barrier();
83 spin_lock(&timebase_lock);
84 set_tb(timebase_upper, timebase_lower);
85 timebase_upper = 0;
86 timebase_lower = 0;
87 spin_unlock(&timebase_lock);
88 printk("CPU %i taken timebase\n", smp_processor_id());
89}
90
91/* CHRP with openpic */
92struct smp_ops_t chrp_smp_ops = {
93 .message_pass = smp_openpic_message_pass,
94 .probe = smp_chrp_probe,
95 .kick_cpu = smp_chrp_kick_cpu,
96 .setup_cpu = smp_chrp_setup_cpu,
97 .give_timebase = smp_chrp_give_timebase,
98 .take_timebase = smp_chrp_take_timebase,
99};
diff --git a/arch/ppc/platforms/chrp_time.c b/arch/ppc/platforms/chrp_time.c
deleted file mode 100644
index c8627770af13..000000000000
--- a/arch/ppc/platforms/chrp_time.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
3 *
4 * Adapted for PowerPC (PReP) by Gary Thomas
5 * Modified by Cort Dougan (cort@cs.nmt.edu).
6 * Copied and modified from arch/i386/kernel/time.c
7 *
8 */
9#include <linux/errno.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/string.h>
14#include <linux/mm.h>
15#include <linux/interrupt.h>
16#include <linux/time.h>
17#include <linux/timex.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/init.h>
21#include <linux/bcd.h>
22
23#include <asm/io.h>
24#include <asm/nvram.h>
25#include <asm/prom.h>
26#include <asm/sections.h>
27#include <asm/time.h>
28
29extern spinlock_t rtc_lock;
30
31static int nvram_as1 = NVRAM_AS1;
32static int nvram_as0 = NVRAM_AS0;
33static int nvram_data = NVRAM_DATA;
34
35long __init chrp_time_init(void)
36{
37 struct device_node *rtcs;
38 int base;
39
40 rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
41 if (rtcs == NULL)
42 rtcs = find_compatible_devices("rtc", "ds1385-rtc");
43 if (rtcs == NULL || rtcs->addrs == NULL)
44 return 0;
45 base = rtcs->addrs[0].address;
46 nvram_as1 = 0;
47 nvram_as0 = base;
48 nvram_data = base + 1;
49
50 return 0;
51}
52
53int chrp_cmos_clock_read(int addr)
54{
55 if (nvram_as1 != 0)
56 outb(addr>>8, nvram_as1);
57 outb(addr, nvram_as0);
58 return (inb(nvram_data));
59}
60
61void chrp_cmos_clock_write(unsigned long val, int addr)
62{
63 if (nvram_as1 != 0)
64 outb(addr>>8, nvram_as1);
65 outb(addr, nvram_as0);
66 outb(val, nvram_data);
67 return;
68}
69
70/*
71 * Set the hardware clock. -- Cort
72 */
73int chrp_set_rtc_time(unsigned long nowtime)
74{
75 unsigned char save_control, save_freq_select;
76 struct rtc_time tm;
77
78 spin_lock(&rtc_lock);
79 to_tm(nowtime, &tm);
80
81 save_control = chrp_cmos_clock_read(RTC_CONTROL); /* tell the clock it's being set */
82
83 chrp_cmos_clock_write((save_control|RTC_SET), RTC_CONTROL);
84
85 save_freq_select = chrp_cmos_clock_read(RTC_FREQ_SELECT); /* stop and reset prescaler */
86
87 chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
88
89 tm.tm_year -= 1900;
90 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
91 BIN_TO_BCD(tm.tm_sec);
92 BIN_TO_BCD(tm.tm_min);
93 BIN_TO_BCD(tm.tm_hour);
94 BIN_TO_BCD(tm.tm_mon);
95 BIN_TO_BCD(tm.tm_mday);
96 BIN_TO_BCD(tm.tm_year);
97 }
98 chrp_cmos_clock_write(tm.tm_sec,RTC_SECONDS);
99 chrp_cmos_clock_write(tm.tm_min,RTC_MINUTES);
100 chrp_cmos_clock_write(tm.tm_hour,RTC_HOURS);
101 chrp_cmos_clock_write(tm.tm_mon,RTC_MONTH);
102 chrp_cmos_clock_write(tm.tm_mday,RTC_DAY_OF_MONTH);
103 chrp_cmos_clock_write(tm.tm_year,RTC_YEAR);
104
105 /* The following flags have to be released exactly in this order,
106 * otherwise the DS12887 (popular MC146818A clone with integrated
107 * battery and quartz) will not reset the oscillator and will not
108 * update precisely 500 ms later. You won't find this mentioned in
109 * the Dallas Semiconductor data sheets, but who believes data
110 * sheets anyway ... -- Markus Kuhn
111 */
112 chrp_cmos_clock_write(save_control, RTC_CONTROL);
113 chrp_cmos_clock_write(save_freq_select, RTC_FREQ_SELECT);
114
115 spin_unlock(&rtc_lock);
116 return 0;
117}
118
119unsigned long chrp_get_rtc_time(void)
120{
121 unsigned int year, mon, day, hour, min, sec;
122 int uip, i;
123
124 /* The Linux interpretation of the CMOS clock register contents:
125 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
126 * RTC registers show the second which has precisely just started.
127 * Let's hope other operating systems interpret the RTC the same way.
128 */
129
130 /* Since the UIP flag is set for about 2.2 ms and the clock
131 * is typically written with a precision of 1 jiffy, trying
132 * to obtain a precision better than a few milliseconds is
133 * an illusion. Only consistency is interesting, this also
134 * allows to use the routine for /dev/rtc without a potential
135 * 1 second kernel busy loop triggered by any reader of /dev/rtc.
136 */
137
138 for ( i = 0; i<1000000; i++) {
139 uip = chrp_cmos_clock_read(RTC_FREQ_SELECT);
140 sec = chrp_cmos_clock_read(RTC_SECONDS);
141 min = chrp_cmos_clock_read(RTC_MINUTES);
142 hour = chrp_cmos_clock_read(RTC_HOURS);
143 day = chrp_cmos_clock_read(RTC_DAY_OF_MONTH);
144 mon = chrp_cmos_clock_read(RTC_MONTH);
145 year = chrp_cmos_clock_read(RTC_YEAR);
146 uip |= chrp_cmos_clock_read(RTC_FREQ_SELECT);
147 if ((uip & RTC_UIP)==0) break;
148 }
149
150 if (!(chrp_cmos_clock_read(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
151 {
152 BCD_TO_BIN(sec);
153 BCD_TO_BIN(min);
154 BCD_TO_BIN(hour);
155 BCD_TO_BIN(day);
156 BCD_TO_BIN(mon);
157 BCD_TO_BIN(year);
158 }
159 if ((year += 1900) < 1970)
160 year += 100;
161 return mktime(year, mon, day, hour, min, sec);
162}
163
164/*
165 * Calibrate the decrementer frequency with the VIA timer 1.
166 */
167#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
168
169/* VIA registers */
170#define RS 0x200 /* skip between registers */
171#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
172#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
173#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
174#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
175#define ACR (11*RS) /* Auxiliary control register */
176#define IFR (13*RS) /* Interrupt flag register */
177
178/* Bits in ACR */
179#define T1MODE 0xc0 /* Timer 1 mode */
180#define T1MODE_CONT 0x40 /* continuous interrupts */
181
182/* Bits in IFR and IER */
183#define T1_INT 0x40 /* Timer 1 interrupt */
184
185static int __init chrp_via_calibrate_decr(void)
186{
187 struct device_node *vias;
188 volatile unsigned char __iomem *via;
189 int count = VIA_TIMER_FREQ_6 / 100;
190 unsigned int dstart, dend;
191
192 vias = find_devices("via-cuda");
193 if (vias == 0)
194 vias = find_devices("via");
195 if (vias == 0 || vias->n_addrs == 0)
196 return 0;
197 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
198
199 /* set timer 1 for continuous interrupts */
200 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
201 /* set the counter to a small value */
202 out_8(&via[T1CH], 2);
203 /* set the latch to `count' */
204 out_8(&via[T1LL], count);
205 out_8(&via[T1LH], count >> 8);
206 /* wait until it hits 0 */
207 while ((in_8(&via[IFR]) & T1_INT) == 0)
208 ;
209 dstart = get_dec();
210 /* clear the interrupt & wait until it hits 0 again */
211 in_8(&via[T1CL]);
212 while ((in_8(&via[IFR]) & T1_INT) == 0)
213 ;
214 dend = get_dec();
215
216 tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
217 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
218
219 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
220 tb_ticks_per_jiffy, dstart - dend);
221
222 iounmap(via);
223
224 return 1;
225}
226
227void __init chrp_calibrate_decr(void)
228{
229 struct device_node *cpu;
230 unsigned int freq, *fp;
231
232 if (chrp_via_calibrate_decr())
233 return;
234
235 /*
236 * The cpu node should have a timebase-frequency property
237 * to tell us the rate at which the decrementer counts.
238 */
239 freq = 16666000; /* hardcoded default */
240 cpu = find_type_devices("cpu");
241 if (cpu != 0) {
242 fp = (unsigned int *)
243 get_property(cpu, "timebase-frequency", NULL);
244 if (fp != 0)
245 freq = *fp;
246 }
247 printk("time_init: decrementer frequency = %u.%.6u MHz\n",
248 freq/1000000, freq%1000000);
249 tb_ticks_per_jiffy = freq / HZ;
250 tb_to_us = mulhwu_scale_factor(freq, 1000000);
251}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 18:33:57 -0500