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-rw-r--r--arch/ppc/platforms/4xx/Kconfig2
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c2
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h64
-rw-r--r--arch/ppc/platforms/4xx/ebony.h4
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c7
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h67
-rw-r--r--arch/ppc/platforms/4xx/walnut.c2
-rw-r--r--arch/ppc/platforms/4xx/walnut.h67
8 files changed, 84 insertions, 131 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index e70e4c6ec787..d8837911bbc6 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -225,7 +225,7 @@ config EMBEDDEDBOOT
225 225
226config IBM_OPENBIOS 226config IBM_OPENBIOS
227 bool 227 bool
228 depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 228 depends on ASH || REDWOOD_5 || REDWOOD_6
229 default y 229 default y
230 230
231config PPC4xx_DMA 231config PPC4xx_DMA
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
index 3678abf86313..8110f55668c5 100644
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ b/arch/ppc/platforms/4xx/bubinga.c
@@ -89,7 +89,7 @@ bubinga_early_serial_map(void)
89 * by 16. 89 * by 16.
90 */ 90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); 91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_pllouta_freq / uart_div; 92 uart_clock = __res.bi_procfreq / uart_div;
93 93
94 /* Setup serial port access */ 94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port)); 95 memset(&port, 0, sizeof(port));
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
index b1df856f8e22..b5380cfaf5c0 100644
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ b/arch/ppc/platforms/4xx/bubinga.h
@@ -1,52 +1,34 @@
1/* 1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga). 2 * arch/ppc/platforms/4xx/bubinga.h
3 * 3 *
4 * Author: SAW (IBM), derived from walnut.h. 4 * Bubinga board definitions
5 * Maintained by MontaVista Software <source@mvista.com> 5 *
6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * Based on original work by
10 * SAW (IBM)
11 * 2003 (c) MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
6 * 17 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */ 18 */
12 19
13#ifdef __KERNEL__ 20#ifdef __KERNEL__
14#ifndef __BUBINGA_H__ 21#ifndef __BUBINGA_H__
15#define __BUBINGA_H__ 22#define __BUBINGA_H__
16 23
17/* 405EP */ 24#include <linux/config.h>
18#include <platforms/4xx/ibm405ep.h> 25#include <platforms/4xx/ibm405ep.h>
19 26#include <asm/ppcboot.h>
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
33 unsigned int bi_intfreq; /* Processor speed, in Hz */
34 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
35 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
36 unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
37 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44 27
45/* Memory map for the Bubinga board. 28/* Memory map for the Bubinga board.
46 * Generic 4xx plus RTC. 29 * Generic 4xx plus RTC.
47 */ 30 */
48 31
49extern void *bubinga_rtc_base;
50#define BUBINGA_RTC_PADDR ((uint)0xf0000000) 32#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
51#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR 33#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
52#define BUBINGA_RTC_SIZE ((uint)8*1024) 34#define BUBINGA_RTC_SIZE ((uint)8*1024)
@@ -58,12 +40,18 @@ extern void *bubinga_rtc_base;
58 * for typical configurations at various CPU speeds. 40 * for typical configurations at various CPU speeds.
59 * The base baud is calculated as (FWDA / EXT UART DIV / 16) 41 * The base baud is calculated as (FWDA / EXT UART DIV / 16)
60 */ 42 */
61#define BASE_BAUD 0 43#define BASE_BAUD 0
62 44
63#define BUBINGA_FPGA_BASE 0xF0300000 45/* Flash */
46#define PPC40x_FPGA_BASE 0xF0300000
47#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
48#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
49#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
50#define PPC40x_FLASH_LOW 0xFFF00000
51#define PPC40x_FLASH_HIGH 0xFFF80000
52#define PPC40x_FLASH_SIZE 0x80000
64 53
65#define PPC4xx_MACHINE_NAME "IBM Bubinga" 54#define PPC4xx_MACHINE_NAME "IBM Bubinga"
66 55
67#endif /* !__ASSEMBLY__ */
68#endif /* __BUBINGA_H__ */ 56#endif /* __BUBINGA_H__ */
69#endif /* __KERNEL__ */ 57#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index d08faa46a0ae..b91ad4272dfe 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -24,8 +24,8 @@
24#define PPC44x_EMAC0_MR0 0xE0000800 24#define PPC44x_EMAC0_MR0 0xE0000800
25 25
26/* Where to find the MAC info */ 26/* Where to find the MAC info */
27#define EBONY_OPENBIOS_MAC_BASE 0xfffffe0c 27#define OPENBIOS_MAC_BASE 0xfffffe0c
28#define EBONY_OPENBIOS_MAC_OFFSET 0x0c 28#define OPENBIOS_MAC_OFFSET 0x0c
29 29
30/* Default clock rates for Rev. B and Rev. C silicon */ 30/* Default clock rates for Rev. B and Rev. C silicon */
31#define EBONY_440GP_RB_SYSCLK 33000000 31#define EBONY_440GP_RB_SYSCLK 33000000
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
index d8019eec4704..281b4a2ffb96 100644
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ b/arch/ppc/platforms/4xx/sycamore.c
@@ -88,9 +88,6 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
88void __init 88void __init
89sycamore_setup_arch(void) 89sycamore_setup_arch(void)
90{ 90{
91#define SYCAMORE_PS2_BASE 0xF0100000
92#define SYCAMORE_FPGA_BASE 0xF0300000
93
94 void *fpga_brdc; 91 void *fpga_brdc;
95 unsigned char fpga_brdc_data; 92 unsigned char fpga_brdc_data;
96 void *fpga_enable; 93 void *fpga_enable;
@@ -100,7 +97,7 @@ sycamore_setup_arch(void)
100 97
101 ppc4xx_setup_arch(); 98 ppc4xx_setup_arch();
102 99
103 ibm_ocp_set_emac(0, 1); 100 ibm_ocp_set_emac(0, 0);
104 101
105 kb_data = ioremap(SYCAMORE_PS2_BASE, 8); 102 kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
106 if (!kb_data) { 103 if (!kb_data) {
@@ -111,7 +108,7 @@ sycamore_setup_arch(void)
111 108
112 kb_cs = kb_data + 1; 109 kb_cs = kb_data + 1;
113 110
114 fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8); 111 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
115 if (!fpga_status) { 112 if (!fpga_status) {
116 printk(KERN_CRIT 113 printk(KERN_CRIT
117 "sycamore_setup_arch() fpga_status ioremap failed\n"); 114 "sycamore_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
index 3e7b4e2c8c57..1cd6c824fd62 100644
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ b/arch/ppc/platforms/4xx/sycamore.h
@@ -1,67 +1,52 @@
1/* 1/*
2 * arch/ppc/platforms/4xx/sycamore.h 2 * arch/ppc/platforms/4xx/sycamore.h
3 * 3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC 4 * Sycamore board definitions
5 * 405GPr "Sycamore" evaluation board.
6 * 5 *
7 * Author: Armin Kuster <akuster@mvista.com> 6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * 2000 (c) MontaVista, Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
8 * 17 *
9 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */ 18 */
14 19
15#ifdef __KERNEL__ 20#ifdef __KERNEL__
16#ifndef __ASM_SYCAMORE_H__ 21#ifndef __ASM_SYCAMORE_H__
17#define __ASM_SYCAMORE_H__ 22#define __ASM_SYCAMORE_H__
18 23
24#include <linux/config.h>
19#include <platforms/4xx/ibm405gpr.h> 25#include <platforms/4xx/ibm405gpr.h>
26#include <asm/ppcboot.h>
20 27
21#ifndef __ASSEMBLY__ 28/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
22/*
23 * Data structure defining board information maintained by the boot
24 * ROM on IBM's "Sycamore" evaluation board. An effort has been made to
25 * keep the field names consistent with the 8xx 'bd_t' board info
26 * structures.
27 */
28
29typedef struct board_info {
30 unsigned char bi_s_version[4]; /* Version of this structure */
31 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
32 unsigned int bi_memsize; /* DRAM installed, in bytes */
33 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
34 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
35 unsigned int bi_intfreq; /* Processor speed, in Hz */
36 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
37 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44
45/* Memory map for the IBM "Sycamore" 405GP evaluation board.
46 * Generic 4xx plus RTC. 29 * Generic 4xx plus RTC.
47 */ 30 */
48 31
49extern void *sycamore_rtc_base;
50#define SYCAMORE_RTC_PADDR ((uint)0xf0000000) 32#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
51#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR 33#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
52#define SYCAMORE_RTC_SIZE ((uint)8*1024) 34#define SYCAMORE_RTC_SIZE ((uint)8*1024)
53 35
54#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
55#define BASE_BAUD 201600
56#else
57#define BASE_BAUD 691200 36#define BASE_BAUD 691200
58#endif
59 37
60#define SYCAMORE_PS2_BASE 0xF0100000 38#define SYCAMORE_PS2_BASE 0xF0100000
61#define SYCAMORE_FPGA_BASE 0xF0300000 39
40/* Flash */
41#define PPC40x_FPGA_BASE 0xF0300000
42#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
43#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
44#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
45#define PPC40x_FLASH_LOW 0xFFF00000
46#define PPC40x_FLASH_HIGH 0xFFF80000
47#define PPC40x_FLASH_SIZE 0x80000
62 48
63#define PPC4xx_MACHINE_NAME "IBM Sycamore" 49#define PPC4xx_MACHINE_NAME "IBM Sycamore"
64 50
65#endif /* !__ASSEMBLY__ */
66#endif /* __ASM_SYCAMORE_H__ */ 51#endif /* __ASM_SYCAMORE_H__ */
67#endif /* __KERNEL__ */ 52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
index a33eda4b7489..74cb33182d9f 100644
--- a/arch/ppc/platforms/4xx/walnut.c
+++ b/arch/ppc/platforms/4xx/walnut.c
@@ -90,7 +90,7 @@ walnut_setup_arch(void)
90 90
91 kb_cs = kb_data + 1; 91 kb_cs = kb_data + 1;
92 92
93 fpga_status = ioremap(WALNUT_FPGA_BASE, 8); 93 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
94 if (!fpga_status) { 94 if (!fpga_status) {
95 printk(KERN_CRIT 95 printk(KERN_CRIT
96 "walnut_setup_arch() fpga_status ioremap failed\n"); 96 "walnut_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
index 04cfbf3696b9..dcf2691698c0 100644
--- a/arch/ppc/platforms/4xx/walnut.h
+++ b/arch/ppc/platforms/4xx/walnut.h
@@ -1,72 +1,55 @@
1/* 1/*
2 * arch/ppc/platforms/4xx/walnut.h 2 * arch/ppc/platforms/4xx/walnut.h
3 * 3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC 4 * Walnut board definitions
5 * 405GP "Walnut" evaluation board.
6 * 5 *
7 * Authors: Grant Erickson <grant@lcse.umn.edu>, Frank Rowand 6 * Copyright (c) 2005 DENX Software Engineering
8 * <frank_rowand@mvista.com>, Debbie Chu <debbie_chu@mvista.com> or 7 * Stefan Roese <sr@denx.de>
9 * source@mvista.com
10 * 8 *
11 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 9 * Based on original work by
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 * Frank Rowand <frank_rowand@mvista.com>
12 * Debbie Chu <debbie_chu@mvista.com>
13 * 2000 (c) MontaVista, Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
12 * 19 *
13 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */ 20 */
18 21
19#ifdef __KERNEL__ 22#ifdef __KERNEL__
20#ifndef __ASM_WALNUT_H__ 23#ifndef __ASM_WALNUT_H__
21#define __ASM_WALNUT_H__ 24#define __ASM_WALNUT_H__
22 25
23/* We have a 405GP core */ 26#include <linux/config.h>
24#include <platforms/4xx/ibm405gp.h> 27#include <platforms/4xx/ibm405gp.h>
25 28#include <asm/ppcboot.h>
26#ifndef __ASSEMBLY__
27/*
28 * Data structure defining board information maintained by the boot
29 * ROM on IBM's "Walnut" evaluation board. An effort has been made to
30 * keep the field names consistent with the 8xx 'bd_t' board info
31 * structures.
32 */
33
34typedef struct board_info {
35 unsigned char bi_s_version[4]; /* Version of this structure */
36 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
37 unsigned int bi_memsize; /* DRAM installed, in bytes */
38 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
39 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
40 unsigned int bi_intfreq; /* Processor speed, in Hz */
41 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
42 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
43} bd_t;
44
45/* Some 4xx parts use a different timebase frequency from the internal clock.
46*/
47#define bi_tbfreq bi_intfreq
48
49 29
50/* Memory map for the IBM "Walnut" 405GP evaluation board. 30/* Memory map for the IBM "Walnut" 405GP evaluation board.
51 * Generic 4xx plus RTC. 31 * Generic 4xx plus RTC.
52 */ 32 */
53 33
54extern void *walnut_rtc_base;
55#define WALNUT_RTC_PADDR ((uint)0xf0000000) 34#define WALNUT_RTC_PADDR ((uint)0xf0000000)
56#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR 35#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
57#define WALNUT_RTC_SIZE ((uint)8*1024) 36#define WALNUT_RTC_SIZE ((uint)8*1024)
58 37
59#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
60#define BASE_BAUD 201600
61#else
62#define BASE_BAUD 691200 38#define BASE_BAUD 691200
63#endif
64 39
65#define WALNUT_PS2_BASE 0xF0100000 40#define WALNUT_PS2_BASE 0xF0100000
66#define WALNUT_FPGA_BASE 0xF0300000 41
42/* Flash */
43#define PPC40x_FPGA_BASE 0xF0300000
44#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
45#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
46#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
47#define PPC40x_FLASH_LOW 0xFFF00000
48#define PPC40x_FLASH_HIGH 0xFFF80000
49#define PPC40x_FLASH_SIZE 0x80000
50#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE
67 51
68#define PPC4xx_MACHINE_NAME "IBM Walnut" 52#define PPC4xx_MACHINE_NAME "IBM Walnut"
69 53
70#endif /* !__ASSEMBLY__ */
71#endif /* __ASM_WALNUT_H__ */ 54#endif /* __ASM_WALNUT_H__ */
72#endif /* __KERNEL__ */ 55#endif /* __KERNEL__ */