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-rw-r--r--arch/ppc/platforms/4xx/ebony.c7
-rw-r--r--arch/ppc/platforms/4xx/luan.c5
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c5
-rw-r--r--arch/ppc/platforms/chrp_pci.c7
-rw-r--r--arch/ppc/platforms/chrp_setup.c2
-rw-r--r--arch/ppc/platforms/pmac_cache.S54
-rw-r--r--arch/ppc/platforms/pmac_feature.c216
-rw-r--r--arch/ppc/platforms/pmac_low_i2c.c10
-rw-r--r--arch/ppc/platforms/pmac_sleep.S4
-rw-r--r--arch/ppc/platforms/pmac_smp.c14
-rw-r--r--arch/ppc/platforms/pmac_time.c7
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.c60
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.h1
13 files changed, 240 insertions, 152 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index f63bca83e757..cd11734ef7c5 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -149,7 +149,7 @@ ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
149static void __init 149static void __init
150ebony_setup_pcix(void) 150ebony_setup_pcix(void)
151{ 151{
152 void *pcix_reg_base; 152 void __iomem *pcix_reg_base;
153 153
154 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); 154 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
155 155
@@ -210,9 +210,8 @@ ebony_setup_hose(void)
210 hose->io_space.end = EBONY_PCI_UPPER_IO; 210 hose->io_space.end = EBONY_PCI_UPPER_IO;
211 hose->mem_space.start = EBONY_PCI_LOWER_MEM; 211 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
212 hose->mem_space.end = EBONY_PCI_UPPER_MEM; 212 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
213 isa_io_base = 213 hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
214 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); 214 isa_io_base = (unsigned long)hose->io_base_virt;
215 hose->io_base_virt = (void *)isa_io_base;
216 215
217 setup_indirect_pci(hose, 216 setup_indirect_pci(hose,
218 EBONY_PCI_CFGA_PLB32, 217 EBONY_PCI_CFGA_PLB32,
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
index 1df2339f1f6c..95359f748e7b 100644
--- a/arch/ppc/platforms/4xx/luan.c
+++ b/arch/ppc/platforms/4xx/luan.c
@@ -223,9 +223,8 @@ luan_setup_hose(struct pci_controller *hose,
223 hose->io_space.end = LUAN_PCIX_UPPER_IO; 223 hose->io_space.end = LUAN_PCIX_UPPER_IO;
224 hose->mem_space.start = lower_mem; 224 hose->mem_space.start = lower_mem;
225 hose->mem_space.end = upper_mem; 225 hose->mem_space.end = upper_mem;
226 isa_io_base = 226 hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
227 (unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE); 227 isa_io_base = (unsigned long) hose->io_base_virt;
228 hose->io_base_virt = (void *)isa_io_base;
229 228
230 setup_indirect_pci(hose, cfga, cfgd); 229 setup_indirect_pci(hose, cfga, cfgd);
231 hose->set_cfg_type = 1; 230 hose->set_cfg_type = 1;
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 28de707434f1..5f82a6bc7046 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -227,9 +227,8 @@ ocotea_setup_hose(void)
227 hose->io_space.end = OCOTEA_PCI_UPPER_IO; 227 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
228 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; 228 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
229 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; 229 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
230 isa_io_base = 230 hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
231 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); 231 isa_io_base = (unsigned long) hose->io_base_virt;
232 hose->io_base_virt = (void *)isa_io_base;
233 232
234 setup_indirect_pci(hose, 233 setup_indirect_pci(hose,
235 OCOTEA_PCI_CFGA_PLB32, 234 OCOTEA_PCI_CFGA_PLB32,
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
index 5bb6492ecf8c..7d0ee308f662 100644
--- a/arch/ppc/platforms/chrp_pci.c
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -129,7 +129,7 @@ static struct pci_ops rtas_pci_ops =
129 rtas_write_config 129 rtas_write_config
130}; 130};
131 131
132volatile struct Hydra *Hydra = NULL; 132volatile struct Hydra __iomem *Hydra = NULL;
133 133
134int __init 134int __init
135hydra_init(void) 135hydra_init(void)
@@ -175,13 +175,14 @@ chrp_pcibios_fixup(void)
175static void __init 175static void __init
176setup_python(struct pci_controller *hose, struct device_node *dev) 176setup_python(struct pci_controller *hose, struct device_node *dev)
177{ 177{
178 u32 *reg, val; 178 u32 __iomem *reg;
179 u32 val;
179 unsigned long addr = dev->addrs[0].address; 180 unsigned long addr = dev->addrs[0].address;
180 181
181 setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010); 182 setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
182 183
183 /* Clear the magic go-slow bit */ 184 /* Clear the magic go-slow bit */
184 reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40); 185 reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
185 val = in_be32(&reg[12]); 186 val = in_be32(&reg[12]);
186 if (val & PRG_CL_RESET_VALID) { 187 if (val & PRG_CL_RESET_VALID) {
187 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID); 188 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
index f23c4f320760..57f29ab29bda 100644
--- a/arch/ppc/platforms/chrp_setup.c
+++ b/arch/ppc/platforms/chrp_setup.c
@@ -356,7 +356,7 @@ static void __init chrp_find_openpic(void)
356 struct device_node *np; 356 struct device_node *np;
357 int len, i; 357 int len, i;
358 unsigned int *iranges; 358 unsigned int *iranges;
359 void *isu; 359 void __iomem *isu;
360 360
361 np = find_type_devices("open-pic"); 361 np = find_type_devices("open-pic");
362 if (np == NULL || np->n_addrs == 0) 362 if (np == NULL || np->n_addrs == 0)
diff --git a/arch/ppc/platforms/pmac_cache.S b/arch/ppc/platforms/pmac_cache.S
index da34a9bc9299..fb977de6b704 100644
--- a/arch/ppc/platforms/pmac_cache.S
+++ b/arch/ppc/platforms/pmac_cache.S
@@ -64,27 +64,39 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
64 mtspr SPRN_HID0,r4 /* Disable DPM */ 64 mtspr SPRN_HID0,r4 /* Disable DPM */
65 sync 65 sync
66 66
67 /* disp-flush L1 */ 67 /* Disp-flush L1. We have a weird problem here that I never
68 li r4,0x4000 68 * totally figured out. On 750FX, using the ROM for the flush
69 mtctr r4 69 * results in a non-working flush. We use that workaround for
70 * now until I finally understand what's going on. --BenH
71 */
72
73 /* ROM base by default */
70 lis r4,0xfff0 74 lis r4,0xfff0
711: lwzx r0,r0,r4 75 mfpvr r3
76 srwi r3,r3,16
77 cmplwi cr0,r3,0x7000
78 bne+ 1f
79 /* RAM base on 750FX */
80 li r4,0
811: li r4,0x4000
82 mtctr r4
831: lwz r0,0(r4)
72 addi r4,r4,32 84 addi r4,r4,32
73 bdnz 1b 85 bdnz 1b
74 sync 86 sync
75 isync 87 isync
76 88
77 /* disable / invalidate / enable L1 data */ 89 /* Disable / invalidate / enable L1 data */
78 mfspr r3,SPRN_HID0 90 mfspr r3,SPRN_HID0
79 rlwinm r0,r0,0,~HID0_DCE 91 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
80 mtspr SPRN_HID0,r3 92 mtspr SPRN_HID0,r3
81 sync 93 sync
82 isync 94 isync
83 ori r3,r3,HID0_DCE|HID0_DCI 95 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
84 sync 96 sync
85 isync 97 isync
86 mtspr SPRN_HID0,r3 98 mtspr SPRN_HID0,r3
87 xori r3,r3,HID0_DCI 99 xori r3,r3,(HID0_DCI|HID0_ICFI)
88 mtspr SPRN_HID0,r3 100 mtspr SPRN_HID0,r3
89 sync 101 sync
90 102
@@ -110,11 +122,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
110 lis r4,2 122 lis r4,2
111 mtctr r4 123 mtctr r4
112 lis r4,0xfff0 124 lis r4,0xfff0
1131: lwzx r0,r0,r4 1251: lwz r0,0(r4)
126 addi r4,r4,32
127 bdnz 1b
128 sync
129 isync
130 lis r4,2
131 mtctr r4
132 lis r4,0xfff0
1331: dcbf 0,r4
114 addi r4,r4,32 134 addi r4,r4,32
115 bdnz 1b 135 bdnz 1b
116 sync 136 sync
117 isync 137 isync
138
118 /* now disable L2 */ 139 /* now disable L2 */
119 rlwinm r5,r5,0,~L2CR_L2E 140 rlwinm r5,r5,0,~L2CR_L2E
120 b 2f 141 b 2f
@@ -135,6 +156,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
135 mtspr SPRN_L2CR,r4 156 mtspr SPRN_L2CR,r4
136 sync 157 sync
137 isync 158 isync
159
160 /* Wait for the invalidation to complete */
1611: mfspr r3,SPRN_L2CR
162 rlwinm. r0,r3,0,31,31
163 bne 1b
164
165 /* Clear L2I */
138 xoris r4,r4,L2CR_L2I@h 166 xoris r4,r4,L2CR_L2I@h
139 sync 167 sync
140 mtspr SPRN_L2CR,r4 168 mtspr SPRN_L2CR,r4
@@ -142,14 +170,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
142 170
143 /* now disable the L1 data cache */ 171 /* now disable the L1 data cache */
144 mfspr r0,SPRN_HID0 172 mfspr r0,SPRN_HID0
145 rlwinm r0,r0,0,~HID0_DCE 173 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
146 mtspr SPRN_HID0,r0 174 mtspr SPRN_HID0,r0
147 sync 175 sync
148 isync 176 isync
149 177
150 /* Restore HID0[DPM] to whatever it was before */ 178 /* Restore HID0[DPM] to whatever it was before */
151 sync 179 sync
152 mtspr SPRN_HID0,r8 180 mfspr r0,SPRN_HID0
181 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
182 mtspr SPRN_HID0,r0
153 sync 183 sync
154 184
155 /* restore DR and EE */ 185 /* restore DR and EE */
@@ -201,7 +231,7 @@ flush_disable_745x:
201 mtctr r4 231 mtctr r4
202 li r4,0 232 li r4,0
2031: 2331:
204 lwzx r0,r0,r4 234 lwz r0,0(r4)
205 addi r4,r4,32 /* Go to start of next cache line */ 235 addi r4,r4,32 /* Go to start of next cache line */
206 bdnz 1b 236 bdnz 1b
207 isync 237 isync
diff --git a/arch/ppc/platforms/pmac_feature.c b/arch/ppc/platforms/pmac_feature.c
index 46cbf36722db..867336ad5d36 100644
--- a/arch/ppc/platforms/pmac_feature.c
+++ b/arch/ppc/platforms/pmac_feature.c
@@ -1590,6 +1590,114 @@ intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
1590 mdelay(10); 1590 mdelay(10);
1591} 1591}
1592 1592
1593
1594void __pmac pmac_tweak_clock_spreading(int enable)
1595{
1596 struct macio_chip* macio = &macio_chips[0];
1597
1598 /* Hack for doing clock spreading on some machines PowerBooks and
1599 * iBooks. This implements the "platform-do-clockspreading" OF
1600 * property as decoded manually on various models. For safety, we also
1601 * check the product ID in the device-tree in cases we'll whack the i2c
1602 * chip to make reasonably sure we won't set wrong values in there
1603 *
1604 * Of course, ultimately, we have to implement a real parser for
1605 * the platform-do-* stuff...
1606 */
1607
1608 if (macio->type == macio_intrepid) {
1609 if (enable)
1610 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1611 else
1612 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1613 mdelay(40);
1614 }
1615
1616 while (machine_is_compatible("PowerBook5,2") ||
1617 machine_is_compatible("PowerBook5,3") ||
1618 machine_is_compatible("PowerBook6,2") ||
1619 machine_is_compatible("PowerBook6,3")) {
1620 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
1621 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
1622 u8 buffer[9];
1623 u32 *productID;
1624 int i, rc, changed = 0;
1625
1626 if (dt == NULL)
1627 break;
1628 productID = (u32 *)get_property(dt, "pid#", NULL);
1629 if (productID == NULL)
1630 break;
1631 while(ui2c) {
1632 struct device_node *p = of_get_parent(ui2c);
1633 if (p && !strcmp(p->name, "uni-n"))
1634 break;
1635 ui2c = of_find_node_by_type(ui2c, "i2c");
1636 }
1637 if (ui2c == NULL)
1638 break;
1639 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
1640 rc = pmac_low_i2c_open(ui2c, 1);
1641 if (rc != 0)
1642 break;
1643 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1644 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1645 DBG("read result: %d,", rc);
1646 if (rc != 0) {
1647 pmac_low_i2c_close(ui2c);
1648 break;
1649 }
1650 for (i=0; i<9; i++)
1651 DBG(" %02x", buffer[i]);
1652 DBG("\n");
1653
1654 switch(*productID) {
1655 case 0x1182: /* AlBook 12" rev 2 */
1656 case 0x1183: /* iBook G4 12" */
1657 buffer[0] = (buffer[0] & 0x8f) | 0x70;
1658 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1659 buffer[5] = (buffer[5] & 0x80) | 0x31;
1660 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1661 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
1662 buffer[8] = (buffer[8] & 0x00) | 0x30;
1663 changed = 1;
1664 break;
1665 case 0x3142: /* AlBook 15" (ATI M10) */
1666 case 0x3143: /* AlBook 17" (ATI M10) */
1667 buffer[0] = (buffer[0] & 0xaf) | 0x50;
1668 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1669 buffer[5] = (buffer[5] & 0x80) | 0x31;
1670 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1671 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
1672 buffer[8] = (buffer[8] & 0x00) | 0x30;
1673 changed = 1;
1674 break;
1675 default:
1676 DBG("i2c-hwclock: Machine model not handled\n");
1677 break;
1678 }
1679 if (!changed) {
1680 pmac_low_i2c_close(ui2c);
1681 break;
1682 }
1683 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
1684 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
1685 DBG("write result: %d,", rc);
1686 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1687 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1688 DBG("read result: %d,", rc);
1689 if (rc != 0) {
1690 pmac_low_i2c_close(ui2c);
1691 break;
1692 }
1693 for (i=0; i<9; i++)
1694 DBG(" %02x", buffer[i]);
1695 pmac_low_i2c_close(ui2c);
1696 break;
1697 }
1698}
1699
1700
1593static int __pmac 1701static int __pmac
1594core99_sleep(void) 1702core99_sleep(void)
1595{ 1703{
@@ -1601,12 +1709,6 @@ core99_sleep(void)
1601 macio->type != macio_intrepid) 1709 macio->type != macio_intrepid)
1602 return -ENODEV; 1710 return -ENODEV;
1603 1711
1604 /* The device-tree contains that in the hwclock node */
1605 if (macio->type == macio_intrepid) {
1606 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1607 mdelay(40);
1608 }
1609
1610 /* We power off the wireless slot in case it was not done 1712 /* We power off the wireless slot in case it was not done
1611 * by the driver. We don't power it on automatically however 1713 * by the driver. We don't power it on automatically however
1612 */ 1714 */
@@ -1749,12 +1851,6 @@ core99_wake_up(void)
1749 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl); 1851 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1750 udelay(100); 1852 udelay(100);
1751 1853
1752 /* Restore clock spreading */
1753 if (macio->type == macio_intrepid) {
1754 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1755 mdelay(40);
1756 }
1757
1758 return 0; 1854 return 0;
1759} 1855}
1760 1856
@@ -2149,7 +2245,7 @@ static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
2149 }, 2245 },
2150 { "PowerBook1,1", "PowerBook 101 (Lombard)", 2246 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2151 PMAC_TYPE_101_PBOOK, paddington_features, 2247 PMAC_TYPE_101_PBOOK, paddington_features,
2152 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE 2248 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2153 }, 2249 },
2154 { "PowerBook2,1", "iBook (first generation)", 2250 { "PowerBook2,1", "iBook (first generation)",
2155 PMAC_TYPE_ORIG_IBOOK, core99_features, 2251 PMAC_TYPE_ORIG_IBOOK, core99_features,
@@ -2718,97 +2814,11 @@ set_initial_features(void)
2718 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 2814 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2719 } 2815 }
2720 2816
2721 /* Hack for bumping clock speed on the new PowerBooks and the 2817 /* Some machine models need the clock chip to be properly setup for
2722 * iBook G4. This implements the "platform-do-clockspreading" OF 2818 * clock spreading now. This should be a platform function but we
2723 * property. For safety, we also check the product ID in the 2819 * don't do these at the moment
2724 * device-tree to make reasonably sure we won't set wrong values
2725 * in the clock chip.
2726 *
2727 * Of course, ultimately, we have to implement a real parser for
2728 * the platform-do-* stuff...
2729 */ 2820 */
2730 while (machine_is_compatible("PowerBook5,2") || 2821 pmac_tweak_clock_spreading(1);
2731 machine_is_compatible("PowerBook5,3") ||
2732 machine_is_compatible("PowerBook6,2") ||
2733 machine_is_compatible("PowerBook6,3")) {
2734 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
2735 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
2736 u8 buffer[9];
2737 u32 *productID;
2738 int i, rc, changed = 0;
2739
2740 if (dt == NULL)
2741 break;
2742 productID = (u32 *)get_property(dt, "pid#", NULL);
2743 if (productID == NULL)
2744 break;
2745 while(ui2c) {
2746 struct device_node *p = of_get_parent(ui2c);
2747 if (p && !strcmp(p->name, "uni-n"))
2748 break;
2749 ui2c = of_find_node_by_type(ui2c, "i2c");
2750 }
2751 if (ui2c == NULL)
2752 break;
2753 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
2754 rc = pmac_low_i2c_open(ui2c, 1);
2755 if (rc != 0)
2756 break;
2757 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
2758 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
2759 DBG("read result: %d,", rc);
2760 if (rc != 0) {
2761 pmac_low_i2c_close(ui2c);
2762 break;
2763 }
2764 for (i=0; i<9; i++)
2765 DBG(" %02x", buffer[i]);
2766 DBG("\n");
2767
2768 switch(*productID) {
2769 case 0x1182: /* AlBook 12" rev 2 */
2770 case 0x1183: /* iBook G4 12" */
2771 buffer[0] = (buffer[0] & 0x8f) | 0x70;
2772 buffer[2] = (buffer[2] & 0x7f) | 0x00;
2773 buffer[5] = (buffer[5] & 0x80) | 0x31;
2774 buffer[6] = (buffer[6] & 0x40) | 0xb0;
2775 buffer[7] = (buffer[7] & 0x00) | 0xc0;
2776 buffer[8] = (buffer[8] & 0x00) | 0x30;
2777 changed = 1;
2778 break;
2779 case 0x3142: /* AlBook 15" (ATI M10) */
2780 case 0x3143: /* AlBook 17" (ATI M10) */
2781 buffer[0] = (buffer[0] & 0xaf) | 0x50;
2782 buffer[2] = (buffer[2] & 0x7f) | 0x00;
2783 buffer[5] = (buffer[5] & 0x80) | 0x31;
2784 buffer[6] = (buffer[6] & 0x40) | 0xb0;
2785 buffer[7] = (buffer[7] & 0x00) | 0xd0;
2786 buffer[8] = (buffer[8] & 0x00) | 0x30;
2787 changed = 1;
2788 break;
2789 default:
2790 DBG("i2c-hwclock: Machine model not handled\n");
2791 break;
2792 }
2793 if (!changed) {
2794 pmac_low_i2c_close(ui2c);
2795 break;
2796 }
2797 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
2798 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
2799 DBG("write result: %d,", rc);
2800 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
2801 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
2802 DBG("read result: %d,", rc);
2803 if (rc != 0) {
2804 pmac_low_i2c_close(ui2c);
2805 break;
2806 }
2807 for (i=0; i<9; i++)
2808 DBG(" %02x", buffer[i]);
2809 pmac_low_i2c_close(ui2c);
2810 break;
2811 }
2812 2822
2813#endif /* CONFIG_POWER4 */ 2823#endif /* CONFIG_POWER4 */
2814 2824
diff --git a/arch/ppc/platforms/pmac_low_i2c.c b/arch/ppc/platforms/pmac_low_i2c.c
index d07579f2b8b9..08583fce1692 100644
--- a/arch/ppc/platforms/pmac_low_i2c.c
+++ b/arch/ppc/platforms/pmac_low_i2c.c
@@ -54,7 +54,7 @@ struct low_i2c_host
54 int mode; /* Current mode */ 54 int mode; /* Current mode */
55 int channel; /* Current channel */ 55 int channel; /* Current channel */
56 int num_channels; /* Number of channels */ 56 int num_channels; /* Number of channels */
57 unsigned long base; /* For keywest-i2c, base address */ 57 void __iomem * base; /* For keywest-i2c, base address */
58 int bsteps; /* And register stepping */ 58 int bsteps; /* And register stepping */
59 int speed; /* And speed */ 59 int speed; /* And speed */
60}; 60};
@@ -154,14 +154,12 @@ static const char *__kw_state_names[] = {
154 154
155static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg) 155static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg)
156{ 156{
157 return in_8(((volatile u8 *)host->base) 157 return in_8(host->base + (((unsigned)reg) << host->bsteps));
158 + (((unsigned)reg) << host->bsteps));
159} 158}
160 159
161static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val) 160static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val)
162{ 161{
163 out_8(((volatile u8 *)host->base) 162 out_8(host->base + (((unsigned)reg) << host->bsteps), val);
164 + (((unsigned)reg) << host->bsteps), val);
165 (void)__kw_read_reg(host, reg_subaddr); 163 (void)__kw_read_reg(host, reg_subaddr);
166} 164}
167 165
@@ -370,7 +368,7 @@ static void keywest_low_i2c_add(struct device_node *np)
370 break; 368 break;
371 } 369 }
372 host->mode = pmac_low_i2c_mode_std; 370 host->mode = pmac_low_i2c_mode_std;
373 host->base = (unsigned long)ioremap(np->addrs[0].address + aoffset, 371 host->base = ioremap(np->addrs[0].address + aoffset,
374 np->addrs[0].size); 372 np->addrs[0].size);
375 host->func = keywest_low_i2c_func; 373 host->func = keywest_low_i2c_func;
376} 374}
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
index 3139b6766ad3..f459ade1bd63 100644
--- a/arch/ppc/platforms/pmac_sleep.S
+++ b/arch/ppc/platforms/pmac_sleep.S
@@ -267,6 +267,10 @@ grackle_wake_up:
267 /* Restore various CPU config stuffs */ 267 /* Restore various CPU config stuffs */
268 bl __restore_cpu_setup 268 bl __restore_cpu_setup
269 269
270 /* Make sure all FPRs have been initialized */
271 bl reloc_offset
272 bl __init_fpu_registers
273
270 /* Invalidate & enable L1 cache, we don't care about 274 /* Invalidate & enable L1 cache, we don't care about
271 * whatever the ROM may have tried to write to memory 275 * whatever the ROM may have tried to write to memory
272 */ 276 */
diff --git a/arch/ppc/platforms/pmac_smp.c b/arch/ppc/platforms/pmac_smp.c
index 731841f9a5b8..8e049dab4e63 100644
--- a/arch/ppc/platforms/pmac_smp.c
+++ b/arch/ppc/platforms/pmac_smp.c
@@ -91,11 +91,11 @@ extern void __secondary_start_psurge3(void); /* Temporary horrible hack */
91#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 91#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
92 92
93/* virtual addresses for the above */ 93/* virtual addresses for the above */
94static volatile u8 *hhead_base; 94static volatile u8 __iomem *hhead_base;
95static volatile u8 *quad_base; 95static volatile u8 __iomem *quad_base;
96static volatile u32 *psurge_pri_intr; 96static volatile u32 __iomem *psurge_pri_intr;
97static volatile u8 *psurge_sec_intr; 97static volatile u8 __iomem *psurge_sec_intr;
98static volatile u32 *psurge_start; 98static volatile u32 __iomem *psurge_start;
99 99
100/* values for psurge_type */ 100/* values for psurge_type */
101#define PSURGE_NONE -1 101#define PSURGE_NONE -1
@@ -322,10 +322,10 @@ static int __init smp_psurge_probe(void)
322 /* All released cards using this HW design have 4 CPUs */ 322 /* All released cards using this HW design have 4 CPUs */
323 ncpus = 4; 323 ncpus = 4;
324 } else { 324 } else {
325 iounmap((void *) quad_base); 325 iounmap(quad_base);
326 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 326 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
327 /* not a dual-cpu card */ 327 /* not a dual-cpu card */
328 iounmap((void *) hhead_base); 328 iounmap(hhead_base);
329 psurge_type = PSURGE_NONE; 329 psurge_type = PSURGE_NONE;
330 return 1; 330 return 1;
331 } 331 }
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
index 09636546f44e..de60ccc7db9f 100644
--- a/arch/ppc/platforms/pmac_time.c
+++ b/arch/ppc/platforms/pmac_time.c
@@ -165,7 +165,7 @@ int __init
165via_calibrate_decr(void) 165via_calibrate_decr(void)
166{ 166{
167 struct device_node *vias; 167 struct device_node *vias;
168 volatile unsigned char *via; 168 volatile unsigned char __iomem *via;
169 int count = VIA_TIMER_FREQ_6 / 100; 169 int count = VIA_TIMER_FREQ_6 / 100;
170 unsigned int dstart, dend; 170 unsigned int dstart, dend;
171 171
@@ -176,8 +176,7 @@ via_calibrate_decr(void)
176 vias = find_devices("via"); 176 vias = find_devices("via");
177 if (vias == 0 || vias->n_addrs == 0) 177 if (vias == 0 || vias->n_addrs == 0)
178 return 0; 178 return 0;
179 via = (volatile unsigned char *) 179 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
180 ioremap(vias->addrs[0].address, vias->addrs[0].size);
181 180
182 /* set timer 1 for continuous interrupts */ 181 /* set timer 1 for continuous interrupts */
183 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); 182 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
@@ -202,7 +201,7 @@ via_calibrate_decr(void)
202 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n", 201 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
203 tb_ticks_per_jiffy, dstart - dend); 202 tb_ticks_per_jiffy, dstart - dend);
204 203
205 iounmap((void*)via); 204 iounmap(via);
206 205
207 return 1; 206 return 1;
208} 207}
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c
index 2a99b43737a8..c30607a972d8 100644
--- a/arch/ppc/platforms/radstone_ppc7d.c
+++ b/arch/ppc/platforms/radstone_ppc7d.c
@@ -68,6 +68,7 @@
68#define PPC7D_RST_PIN 17 /* GPP17 */ 68#define PPC7D_RST_PIN 17 /* GPP17 */
69 69
70extern u32 mv64360_irq_base; 70extern u32 mv64360_irq_base;
71extern spinlock_t rtc_lock;
71 72
72static struct mv64x60_handle bh; 73static struct mv64x60_handle bh;
73static int ppc7d_has_alma; 74static int ppc7d_has_alma;
@@ -75,6 +76,11 @@ static int ppc7d_has_alma;
75extern void gen550_progress(char *, unsigned short); 76extern void gen550_progress(char *, unsigned short);
76extern void gen550_init(int, struct uart_port *); 77extern void gen550_init(int, struct uart_port *);
77 78
79/* FIXME - move to h file */
80extern int ds1337_do_command(int id, int cmd, void *arg);
81#define DS1337_GET_DATE 0
82#define DS1337_SET_DATE 1
83
78/* residual data */ 84/* residual data */
79unsigned char __res[sizeof(bd_t)]; 85unsigned char __res[sizeof(bd_t)];
80 86
@@ -253,6 +259,8 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
253 u8 val1, val2; 259 u8 val1, val2;
254 static int flash_sizes[4] = { 64, 32, 0, 16 }; 260 static int flash_sizes[4] = { 64, 32, 0, 16 };
255 static int flash_banks[4] = { 4, 3, 2, 1 }; 261 static int flash_banks[4] = { 4, 3, 2, 1 };
262 static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
263 int sdram_num_banks = 2;
256 static char *pci_modes[] = { "PCI33", "PCI66", 264 static char *pci_modes[] = { "PCI33", "PCI66",
257 "Unknown", "Unknown", 265 "Unknown", "Unknown",
258 "PCIX33", "PCIX66", 266 "PCIX33", "PCIX66",
@@ -279,13 +287,17 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
279 (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : 287 (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
280 (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); 288 (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
281 289
290 val = inb(PPC7D_CPLD_MEM_CONFIG);
291 if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
292
282 val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); 293 val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
283 val1 = val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK; 294 val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
284 seq_printf(m, "SDRAM\t\t: %d%c", 295 seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
285 (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_128M) ? 128 : 296 sdram_num_banks,
286 (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_256M) ? 256 : 297 sdram_bank_sizes[val1],
287 (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_512M) ? 512 : 1, 298 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
288 (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_1G) ? 'G' : 'M'); 299 sdram_num_banks * sdram_bank_sizes[val1],
300 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
289 if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { 301 if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
290 seq_printf(m, " [ECC %sabled]", 302 seq_printf(m, " [ECC %sabled]",
291 (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : 303 (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
@@ -1236,6 +1248,38 @@ static void __init ppc7d_setup_arch(void)
1236 printk(KERN_INFO "Radstone Technology PPC7D\n"); 1248 printk(KERN_INFO "Radstone Technology PPC7D\n");
1237 if (ppc_md.progress) 1249 if (ppc_md.progress)
1238 ppc_md.progress("ppc7d_setup_arch: exit", 0); 1250 ppc_md.progress("ppc7d_setup_arch: exit", 0);
1251
1252}
1253
1254/* Real Time Clock support.
1255 * PPC7D has a DS1337 accessed by I2C.
1256 */
1257static ulong ppc7d_get_rtc_time(void)
1258{
1259 struct rtc_time tm;
1260 int result;
1261
1262 spin_lock(&rtc_lock);
1263 result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
1264 spin_unlock(&rtc_lock);
1265
1266 if (result == 0)
1267 result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
1268
1269 return result;
1270}
1271
1272static int ppc7d_set_rtc_time(unsigned long nowtime)
1273{
1274 struct rtc_time tm;
1275 int result;
1276
1277 spin_lock(&rtc_lock);
1278 to_tm(nowtime, &tm);
1279 result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
1280 spin_unlock(&rtc_lock);
1281
1282 return result;
1239} 1283}
1240 1284
1241/* This kernel command line parameter can be used to have the target 1285/* This kernel command line parameter can be used to have the target
@@ -1293,6 +1337,10 @@ static void ppc7d_init2(void)
1293 data8 |= 0x07; 1337 data8 |= 0x07;
1294 outb(data8, PPC7D_CPLD_LEDS); 1338 outb(data8, PPC7D_CPLD_LEDS);
1295 1339
1340 /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
1341 ppc_md.set_rtc_time = ppc7d_set_rtc_time;
1342 ppc_md.get_rtc_time = ppc7d_get_rtc_time;
1343
1296 pr_debug("%s: exit\n", __FUNCTION__); 1344 pr_debug("%s: exit\n", __FUNCTION__);
1297} 1345}
1298 1346
diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h
index 4546fff2b0c3..938375510be4 100644
--- a/arch/ppc/platforms/radstone_ppc7d.h
+++ b/arch/ppc/platforms/radstone_ppc7d.h
@@ -240,6 +240,7 @@
240#define PPC7D_CPLD_FLASH_CNTL 0x086E 240#define PPC7D_CPLD_FLASH_CNTL 0x086E
241 241
242/* MEMORY_CONFIG_EXTEND */ 242/* MEMORY_CONFIG_EXTEND */
243#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
243#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0 244#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
244#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0 245#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
245#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40 246#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 18:14:39 -0500