diff options
Diffstat (limited to 'arch/ppc/platforms/pq2ads.h')
| -rw-r--r-- | arch/ppc/platforms/pq2ads.h | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h index cf5e5dd06d63..067d9a5aebc1 100644 --- a/arch/ppc/platforms/pq2ads.h +++ b/arch/ppc/platforms/pq2ads.h | |||
| @@ -49,10 +49,10 @@ | |||
| 49 | /* PCI interrupt controller */ | 49 | /* PCI interrupt controller */ |
| 50 | #define PCI_INT_STAT_REG 0xF8200000 | 50 | #define PCI_INT_STAT_REG 0xF8200000 |
| 51 | #define PCI_INT_MASK_REG 0xF8200004 | 51 | #define PCI_INT_MASK_REG 0xF8200004 |
| 52 | #define PIRQA (NR_SIU_INTS + 0) | 52 | #define PIRQA (NR_CPM_INTS + 0) |
| 53 | #define PIRQB (NR_SIU_INTS + 1) | 53 | #define PIRQB (NR_CPM_INTS + 1) |
| 54 | #define PIRQC (NR_SIU_INTS + 2) | 54 | #define PIRQC (NR_CPM_INTS + 2) |
| 55 | #define PIRQD (NR_SIU_INTS + 3) | 55 | #define PIRQD (NR_CPM_INTS + 3) |
| 56 | 56 | ||
| 57 | /* | 57 | /* |
| 58 | * PCI memory map definitions for MPC8266ADS-PCI. | 58 | * PCI memory map definitions for MPC8266ADS-PCI. |
| @@ -68,28 +68,23 @@ | |||
| 68 | * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory | 68 | * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory |
| 69 | */ | 69 | */ |
| 70 | 70 | ||
| 71 | /* window for a PCI master to access MPC8266 memory */ | 71 | /* All the other PCI memory map definitions reside at syslib/m82xx_pci.h |
| 72 | #define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */ | 72 | Here we should redefine what is unique for this board */ |
| 73 | #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ | 73 | #define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */ |
| 74 | #define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */ | ||
| 75 | #define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */ | ||
| 74 | 76 | ||
| 75 | /* window for the processor to access PCI memory with prefetching */ | 77 | #define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */ |
| 76 | #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ | 78 | #define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */ |
| 77 | #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ | ||
| 78 | #define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ | ||
| 79 | 79 | ||
| 80 | /* window for the processor to access PCI memory without prefetching */ | 80 | #if defined(CONFIG_ADS8272) |
| 81 | #define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ | 81 | #define PCI_INT_TO_SIU SIU_INT_IRQ2 |
| 82 | #define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ | 82 | #elif defined(CONFIG_PQ2FADS) |
| 83 | #define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ | 83 | #define PCI_INT_TO_SIU SIU_INT_IRQ6 |
| 84 | #else | ||
| 85 | #warning PCI Bridge will be without interrupts support | ||
| 86 | #endif | ||
| 84 | 87 | ||
| 85 | /* window for the processor to access PCI I/O */ | ||
| 86 | #define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ | ||
| 87 | #define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ | ||
| 88 | #define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ | ||
| 89 | |||
| 90 | #define _IO_BASE PCI_MSTR_IO_LOCAL | ||
| 91 | #define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL | ||
| 92 | #define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS | ||
| 93 | #endif /* CONFIG_PCI */ | 88 | #endif /* CONFIG_PCI */ |
| 94 | 89 | ||
| 95 | #endif /* __MACH_ADS8260_DEFS */ | 90 | #endif /* __MACH_ADS8260_DEFS */ |