aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc/platforms/pmac_pci.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/ppc/platforms/pmac_pci.c')
-rw-r--r--arch/ppc/platforms/pmac_pci.c1124
1 files changed, 0 insertions, 1124 deletions
diff --git a/arch/ppc/platforms/pmac_pci.c b/arch/ppc/platforms/pmac_pci.c
deleted file mode 100644
index 786295b6ddd0..000000000000
--- a/arch/ppc/platforms/pmac_pci.c
+++ /dev/null
@@ -1,1124 +0,0 @@
1/*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/pmac_feature.h>
27
28#undef DEBUG
29
30#ifdef DEBUG
31#ifdef CONFIG_XMON
32extern void xmon_printf(const char *fmt, ...);
33#define DBG(x...) xmon_printf(x)
34#else
35#define DBG(x...) printk(x)
36#endif
37#else
38#define DBG(x...)
39#endif
40
41static int add_bridge(struct device_node *dev);
42extern void pmac_check_ht_link(void);
43
44/* XXX Could be per-controller, but I don't think we risk anything by
45 * assuming we won't have both UniNorth and Bandit */
46static int has_uninorth;
47#ifdef CONFIG_POWER4
48static struct pci_controller *u3_agp;
49#endif /* CONFIG_POWER4 */
50
51extern u8 pci_cache_line_size;
52extern int pcibios_assign_bus_offset;
53
54struct device_node *k2_skiplist[2];
55
56/*
57 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
58 */
59#define BANDIT_DEVID_2 8
60#define BANDIT_REVID 3
61
62#define BANDIT_DEVNUM 11
63#define BANDIT_MAGIC 0x50
64#define BANDIT_COHERENT 0x40
65
66static int __init
67fixup_one_level_bus_range(struct device_node *node, int higher)
68{
69 for (; node != 0;node = node->sibling) {
70 int * bus_range;
71 unsigned int *class_code;
72 int len;
73
74 /* For PCI<->PCI bridges or CardBus bridges, we go down */
75 class_code = (unsigned int *) get_property(node, "class-code", NULL);
76 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
77 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
78 continue;
79 bus_range = (int *) get_property(node, "bus-range", &len);
80 if (bus_range != NULL && len > 2 * sizeof(int)) {
81 if (bus_range[1] > higher)
82 higher = bus_range[1];
83 }
84 higher = fixup_one_level_bus_range(node->child, higher);
85 }
86 return higher;
87}
88
89/* This routine fixes the "bus-range" property of all bridges in the
90 * system since they tend to have their "last" member wrong on macs
91 *
92 * Note that the bus numbers manipulated here are OF bus numbers, they
93 * are not Linux bus numbers.
94 */
95static void __init
96fixup_bus_range(struct device_node *bridge)
97{
98 int * bus_range;
99 int len;
100
101 /* Lookup the "bus-range" property for the hose */
102 bus_range = (int *) get_property(bridge, "bus-range", &len);
103 if (bus_range == NULL || len < 2 * sizeof(int)) {
104 printk(KERN_WARNING "Can't get bus-range for %s\n",
105 bridge->full_name);
106 return;
107 }
108 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
109}
110
111/*
112 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
113 *
114 * The "Bandit" version is present in all early PCI PowerMacs,
115 * and up to the first ones using Grackle. Some machines may
116 * have 2 bandit controllers (2 PCI busses).
117 *
118 * "Chaos" is used in some "Bandit"-type machines as a bridge
119 * for the separate display bus. It is accessed the same
120 * way as bandit, but cannot be probed for devices. It therefore
121 * has its own config access functions.
122 *
123 * The "UniNorth" version is present in all Core99 machines
124 * (iBook, G4, new IMacs, and all the recent Apple machines).
125 * It contains 3 controllers in one ASIC.
126 *
127 * The U3 is the bridge used on G5 machines. It contains an
128 * AGP bus which is dealt with the old UniNorth access routines
129 * and a HyperTransport bus which uses its own set of access
130 * functions.
131 */
132
133#define MACRISC_CFA0(devfn, off) \
134 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
135 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
136 | (((unsigned long)(off)) & 0xFCUL))
137
138#define MACRISC_CFA1(bus, devfn, off) \
139 ((((unsigned long)(bus)) << 16) \
140 |(((unsigned long)(devfn)) << 8) \
141 |(((unsigned long)(off)) & 0xFCUL) \
142 |1UL)
143
144static void volatile __iomem *
145macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
146{
147 unsigned int caddr;
148
149 if (bus == hose->first_busno) {
150 if (dev_fn < (11 << 3))
151 return NULL;
152 caddr = MACRISC_CFA0(dev_fn, offset);
153 } else
154 caddr = MACRISC_CFA1(bus, dev_fn, offset);
155
156 /* Uninorth will return garbage if we don't read back the value ! */
157 do {
158 out_le32(hose->cfg_addr, caddr);
159 } while (in_le32(hose->cfg_addr) != caddr);
160
161 offset &= has_uninorth ? 0x07 : 0x03;
162 return hose->cfg_data + offset;
163}
164
165static int
166macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
167 int len, u32 *val)
168{
169 struct pci_controller *hose = bus->sysdata;
170 void volatile __iomem *addr;
171
172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 if (!addr)
174 return PCIBIOS_DEVICE_NOT_FOUND;
175 /*
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
178 */
179 switch (len) {
180 case 1:
181 *val = in_8(addr);
182 break;
183 case 2:
184 *val = in_le16(addr);
185 break;
186 default:
187 *val = in_le32(addr);
188 break;
189 }
190 return PCIBIOS_SUCCESSFUL;
191}
192
193static int
194macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
195 int len, u32 val)
196{
197 struct pci_controller *hose = bus->sysdata;
198 void volatile __iomem *addr;
199
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
201 if (!addr)
202 return PCIBIOS_DEVICE_NOT_FOUND;
203 /*
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
206 */
207 switch (len) {
208 case 1:
209 out_8(addr, val);
210 (void) in_8(addr);
211 break;
212 case 2:
213 out_le16(addr, val);
214 (void) in_le16(addr);
215 break;
216 default:
217 out_le32(addr, val);
218 (void) in_le32(addr);
219 break;
220 }
221 return PCIBIOS_SUCCESSFUL;
222}
223
224static struct pci_ops macrisc_pci_ops =
225{
226 macrisc_read_config,
227 macrisc_write_config
228};
229
230/*
231 * Verifiy that a specific (bus, dev_fn) exists on chaos
232 */
233static int
234chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
235{
236 struct device_node *np;
237 u32 *vendor, *device;
238
239 np = pci_busdev_to_OF_node(bus, devfn);
240 if (np == NULL)
241 return PCIBIOS_DEVICE_NOT_FOUND;
242
243 vendor = (u32 *)get_property(np, "vendor-id", NULL);
244 device = (u32 *)get_property(np, "device-id", NULL);
245 if (vendor == NULL || device == NULL)
246 return PCIBIOS_DEVICE_NOT_FOUND;
247
248 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
250 return PCIBIOS_BAD_REGISTER_NUMBER;
251
252 return PCIBIOS_SUCCESSFUL;
253}
254
255static int
256chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
257 int len, u32 *val)
258{
259 int result = chaos_validate_dev(bus, devfn, offset);
260 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
261 *val = ~0U;
262 if (result != PCIBIOS_SUCCESSFUL)
263 return result;
264 return macrisc_read_config(bus, devfn, offset, len, val);
265}
266
267static int
268chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
269 int len, u32 val)
270{
271 int result = chaos_validate_dev(bus, devfn, offset);
272 if (result != PCIBIOS_SUCCESSFUL)
273 return result;
274 return macrisc_write_config(bus, devfn, offset, len, val);
275}
276
277static struct pci_ops chaos_pci_ops =
278{
279 chaos_read_config,
280 chaos_write_config
281};
282
283#ifdef CONFIG_POWER4
284
285/*
286 * These versions of U3 HyperTransport config space access ops do not
287 * implement self-view of the HT host yet
288 */
289
290#define U3_HT_CFA0(devfn, off) \
291 ((((unsigned long)devfn) << 8) | offset)
292#define U3_HT_CFA1(bus, devfn, off) \
293 (U3_HT_CFA0(devfn, off) \
294 + (((unsigned long)bus) << 16) \
295 + 0x01000000UL)
296
297static void volatile __iomem *
298u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset)
299{
300 if (bus == hose->first_busno) {
301 /* For now, we don't self probe U3 HT bridge */
302 if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 ||
303 PCI_SLOT(devfn) < 1)
304 return 0;
305 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
306 } else
307 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
308}
309
310static int
311u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
312 int len, u32 *val)
313{
314 struct pci_controller *hose = bus->sysdata;
315 void volatile __iomem *addr;
316 int i;
317
318 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
319 if (np == NULL)
320 return PCIBIOS_DEVICE_NOT_FOUND;
321
322 /*
323 * When a device in K2 is powered down, we die on config
324 * cycle accesses. Fix that here.
325 */
326 for (i=0; i<2; i++)
327 if (k2_skiplist[i] == np) {
328 switch (len) {
329 case 1:
330 *val = 0xff; break;
331 case 2:
332 *val = 0xffff; break;
333 default:
334 *val = 0xfffffffful; break;
335 }
336 return PCIBIOS_SUCCESSFUL;
337 }
338
339 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
340 if (!addr)
341 return PCIBIOS_DEVICE_NOT_FOUND;
342 /*
343 * Note: the caller has already checked that offset is
344 * suitably aligned and that len is 1, 2 or 4.
345 */
346 switch (len) {
347 case 1:
348 *val = in_8(addr);
349 break;
350 case 2:
351 *val = in_le16(addr);
352 break;
353 default:
354 *val = in_le32(addr);
355 break;
356 }
357 return PCIBIOS_SUCCESSFUL;
358}
359
360static int
361u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
362 int len, u32 val)
363{
364 struct pci_controller *hose = bus->sysdata;
365 void volatile __iomem *addr;
366 int i;
367
368 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
369 if (np == NULL)
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 /*
372 * When a device in K2 is powered down, we die on config
373 * cycle accesses. Fix that here.
374 */
375 for (i=0; i<2; i++)
376 if (k2_skiplist[i] == np)
377 return PCIBIOS_SUCCESSFUL;
378
379 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
380 if (!addr)
381 return PCIBIOS_DEVICE_NOT_FOUND;
382 /*
383 * Note: the caller has already checked that offset is
384 * suitably aligned and that len is 1, 2 or 4.
385 */
386 switch (len) {
387 case 1:
388 out_8(addr, val);
389 (void) in_8(addr);
390 break;
391 case 2:
392 out_le16(addr, val);
393 (void) in_le16(addr);
394 break;
395 default:
396 out_le32(addr, val);
397 (void) in_le32(addr);
398 break;
399 }
400 return PCIBIOS_SUCCESSFUL;
401}
402
403static struct pci_ops u3_ht_pci_ops =
404{
405 u3_ht_read_config,
406 u3_ht_write_config
407};
408
409#endif /* CONFIG_POWER4 */
410
411/*
412 * For a bandit bridge, turn on cache coherency if necessary.
413 * N.B. we could clean this up using the hose ops directly.
414 */
415static void __init
416init_bandit(struct pci_controller *bp)
417{
418 unsigned int vendev, magic;
419 int rev;
420
421 /* read the word at offset 0 in config space for device 11 */
422 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
423 udelay(2);
424 vendev = in_le32(bp->cfg_data);
425 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
426 PCI_VENDOR_ID_APPLE) {
427 /* read the revision id */
428 out_le32(bp->cfg_addr,
429 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
430 udelay(2);
431 rev = in_8(bp->cfg_data);
432 if (rev != BANDIT_REVID)
433 printk(KERN_WARNING
434 "Unknown revision %d for bandit\n", rev);
435 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
436 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
437 return;
438 }
439
440 /* read the word at offset 0x50 */
441 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
442 udelay(2);
443 magic = in_le32(bp->cfg_data);
444 if ((magic & BANDIT_COHERENT) != 0)
445 return;
446 magic |= BANDIT_COHERENT;
447 udelay(2);
448 out_le32(bp->cfg_data, magic);
449 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
450}
451
452
453/*
454 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
455 */
456static void __init
457init_p2pbridge(void)
458{
459 struct device_node *p2pbridge;
460 struct pci_controller* hose;
461 u8 bus, devfn;
462 u16 val;
463
464 /* XXX it would be better here to identify the specific
465 PCI-PCI bridge chip we have. */
466 if ((p2pbridge = find_devices("pci-bridge")) == 0
467 || p2pbridge->parent == NULL
468 || strcmp(p2pbridge->parent->name, "pci") != 0)
469 return;
470 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
471 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
472 return;
473 }
474 /* Warning: At this point, we have not yet renumbered all busses.
475 * So we must use OF walking to find out hose
476 */
477 hose = pci_find_hose_for_OF_device(p2pbridge);
478 if (!hose) {
479 DBG("Can't find hose for PCI<->PCI bridge\n");
480 return;
481 }
482 if (early_read_config_word(hose, bus, devfn,
483 PCI_BRIDGE_CONTROL, &val) < 0) {
484 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
485 return;
486 }
487 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
488 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
489}
490
491/*
492 * Some Apple desktop machines have a NEC PD720100A USB2 controller
493 * on the motherboard. Open Firmware, on these, will disable the
494 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
495 * code re-enables it ;)
496 */
497static void __init
498fixup_nec_usb2(void)
499{
500 struct device_node *nec;
501
502 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
503 struct pci_controller *hose;
504 u32 data, *prop;
505 u8 bus, devfn;
506
507 prop = (u32 *)get_property(nec, "vendor-id", NULL);
508 if (prop == NULL)
509 continue;
510 if (0x1033 != *prop)
511 continue;
512 prop = (u32 *)get_property(nec, "device-id", NULL);
513 if (prop == NULL)
514 continue;
515 if (0x0035 != *prop)
516 continue;
517 prop = (u32 *)get_property(nec, "reg", NULL);
518 if (prop == NULL)
519 continue;
520 devfn = (prop[0] >> 8) & 0xff;
521 bus = (prop[0] >> 16) & 0xff;
522 if (PCI_FUNC(devfn) != 0)
523 continue;
524 hose = pci_find_hose_for_OF_device(nec);
525 if (!hose)
526 continue;
527 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
528 if (data & 1UL) {
529 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
530 data &= ~1UL;
531 early_write_config_dword(hose, bus, devfn, 0xe4, data);
532 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
533 nec->intrs[0].line);
534 }
535 }
536}
537
538void __init
539pmac_find_bridges(void)
540{
541 struct device_node *np, *root;
542 struct device_node *ht = NULL;
543
544 root = of_find_node_by_path("/");
545 if (root == NULL) {
546 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
547 return;
548 }
549 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
550 if (np->name == NULL)
551 continue;
552 if (strcmp(np->name, "bandit") == 0
553 || strcmp(np->name, "chaos") == 0
554 || strcmp(np->name, "pci") == 0) {
555 if (add_bridge(np) == 0)
556 of_node_get(np);
557 }
558 if (strcmp(np->name, "ht") == 0) {
559 of_node_get(np);
560 ht = np;
561 }
562 }
563 of_node_put(root);
564
565 /* Probe HT last as it relies on the agp resources to be already
566 * setup
567 */
568 if (ht && add_bridge(ht) != 0)
569 of_node_put(ht);
570
571 init_p2pbridge();
572 fixup_nec_usb2();
573
574 /* We are still having some issues with the Xserve G4, enabling
575 * some offset between bus number and domains for now when we
576 * assign all busses should help for now
577 */
578 if (pci_assign_all_buses)
579 pcibios_assign_bus_offset = 0x10;
580
581#ifdef CONFIG_POWER4
582 /* There is something wrong with DMA on U3/HT. I haven't figured out
583 * the details yet, but if I set the cache line size to 128 bytes like
584 * it should, I'm getting memory corruption caused by devices like
585 * sungem (even without the MWI bit set, but maybe sungem doesn't
586 * care). Right now, it appears that setting up a 64 bytes line size
587 * works properly, 64 bytes beeing the max transfer size of HT, I
588 * suppose this is related the way HT/PCI are hooked together. I still
589 * need to dive into more specs though to be really sure of what's
590 * going on. --BenH.
591 *
592 * Ok, apparently, it's just that HT can't do more than 64 bytes
593 * transactions. MWI seem to be meaningless there as well, it may
594 * be worth nop'ing out pci_set_mwi too though I haven't done that
595 * yet.
596 *
597 * Note that it's a bit different for whatever is in the AGP slot.
598 * For now, I don't care, but this can become a real issue, we
599 * should probably hook pci_set_mwi anyway to make sure it sets
600 * the real cache line size in there.
601 */
602 if (machine_is_compatible("MacRISC4"))
603 pci_cache_line_size = 16; /* 64 bytes */
604
605 pmac_check_ht_link();
606#endif /* CONFIG_POWER4 */
607}
608
609#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
610 | (((o) & ~3) << 24))
611
612#define GRACKLE_PICR1_STG 0x00000040
613#define GRACKLE_PICR1_LOOPSNOOP 0x00000010
614
615/* N.B. this is called before bridges is initialized, so we can't
616 use grackle_pcibios_{read,write}_config_dword. */
617static inline void grackle_set_stg(struct pci_controller* bp, int enable)
618{
619 unsigned int val;
620
621 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
622 val = in_le32(bp->cfg_data);
623 val = enable? (val | GRACKLE_PICR1_STG) :
624 (val & ~GRACKLE_PICR1_STG);
625 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
626 out_le32(bp->cfg_data, val);
627 (void)in_le32(bp->cfg_data);
628}
629
630static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
631{
632 unsigned int val;
633
634 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
635 val = in_le32(bp->cfg_data);
636 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
637 (val & ~GRACKLE_PICR1_LOOPSNOOP);
638 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
639 out_le32(bp->cfg_data, val);
640 (void)in_le32(bp->cfg_data);
641}
642
643static int __init
644setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
645{
646 pci_assign_all_buses = 1;
647 has_uninorth = 1;
648 hose->ops = &macrisc_pci_ops;
649 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
650 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
651 /* We "know" that the bridge at f2000000 has the PCI slots. */
652 return addr->address == 0xf2000000;
653}
654
655static void __init
656setup_bandit(struct pci_controller* hose, struct reg_property* addr)
657{
658 hose->ops = &macrisc_pci_ops;
659 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
660 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
661 init_bandit(hose);
662}
663
664static void __init
665setup_chaos(struct pci_controller* hose, struct reg_property* addr)
666{
667 /* assume a `chaos' bridge */
668 hose->ops = &chaos_pci_ops;
669 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
670 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
671}
672
673#ifdef CONFIG_POWER4
674
675static void __init
676setup_u3_agp(struct pci_controller* hose, struct reg_property* addr)
677{
678 /* On G5, we move AGP up to high bus number so we don't need
679 * to reassign bus numbers for HT. If we ever have P2P bridges
680 * on AGP, we'll have to move pci_assign_all_buses to the
681 * pci_controller structure so we enable it for AGP and not for
682 * HT childs.
683 * We hard code the address because of the different size of
684 * the reg address cell, we shall fix that by killing struct
685 * reg_property and using some accessor functions instead
686 */
687 hose->first_busno = 0xf0;
688 hose->last_busno = 0xff;
689 has_uninorth = 1;
690 hose->ops = &macrisc_pci_ops;
691 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
692 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
693
694 u3_agp = hose;
695}
696
697static void __init
698setup_u3_ht(struct pci_controller* hose, struct reg_property *addr)
699{
700 struct device_node *np = (struct device_node *)hose->arch_data;
701 int i, cur;
702
703 hose->ops = &u3_ht_pci_ops;
704
705 /* We hard code the address because of the different size of
706 * the reg address cell, we shall fix that by killing struct
707 * reg_property and using some accessor functions instead
708 */
709 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
710
711 /*
712 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
713 * have been allocated to AGP. So far, this version of the code doesn't assign
714 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
715 * We need to fix that sooner or later by either parsing all child "ranges"
716 * properties or figuring out the U3 address space decoding logic and
717 * then read its configuration register (if any).
718 */
719 hose->io_base_phys = 0xf4000000;
720 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
721 isa_io_base = (unsigned long) hose->io_base_virt;
722 hose->io_resource.name = np->full_name;
723 hose->io_resource.start = 0;
724 hose->io_resource.end = 0x003fffff;
725 hose->io_resource.flags = IORESOURCE_IO;
726 hose->pci_mem_offset = 0;
727 hose->first_busno = 0;
728 hose->last_busno = 0xef;
729 hose->mem_resources[0].name = np->full_name;
730 hose->mem_resources[0].start = 0x80000000;
731 hose->mem_resources[0].end = 0xefffffff;
732 hose->mem_resources[0].flags = IORESOURCE_MEM;
733
734 if (u3_agp == NULL) {
735 DBG("U3 has no AGP, using full resource range\n");
736 return;
737 }
738
739 /* We "remove" the AGP resources from the resources allocated to HT, that
740 * is we create "holes". However, that code does assumptions that so far
741 * happen to be true (cross fingers...), typically that resources in the
742 * AGP node are properly ordered
743 */
744 cur = 0;
745 for (i=0; i<3; i++) {
746 struct resource *res = &u3_agp->mem_resources[i];
747 if (res->flags != IORESOURCE_MEM)
748 continue;
749 /* We don't care about "fine" resources */
750 if (res->start >= 0xf0000000)
751 continue;
752 /* Check if it's just a matter of "shrinking" us in one direction */
753 if (hose->mem_resources[cur].start == res->start) {
754 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
755 cur, hose->mem_resources[cur].start, res->end + 1);
756 hose->mem_resources[cur].start = res->end + 1;
757 continue;
758 }
759 if (hose->mem_resources[cur].end == res->end) {
760 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
761 cur, hose->mem_resources[cur].end, res->start - 1);
762 hose->mem_resources[cur].end = res->start - 1;
763 continue;
764 }
765 /* No, it's not the case, we need a hole */
766 if (cur == 2) {
767 /* not enough resources to make a hole, we drop part of the range */
768 printk(KERN_WARNING "Running out of resources for /ht host !\n");
769 hose->mem_resources[cur].end = res->start - 1;
770 continue;
771 }
772 cur++;
773 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
774 cur-1, res->start - 1, cur, res->end + 1);
775 hose->mem_resources[cur].name = np->full_name;
776 hose->mem_resources[cur].flags = IORESOURCE_MEM;
777 hose->mem_resources[cur].start = res->end + 1;
778 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
779 hose->mem_resources[cur-1].end = res->start - 1;
780 }
781}
782
783#endif /* CONFIG_POWER4 */
784
785void __init
786setup_grackle(struct pci_controller *hose)
787{
788 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
789 if (machine_is_compatible("AAPL,PowerBook1998"))
790 grackle_set_loop_snoop(hose, 1);
791#if 0 /* Disabled for now, HW problems ??? */
792 grackle_set_stg(hose, 1);
793#endif
794}
795
796/*
797 * We assume that if we have a G3 powermac, we have one bridge called
798 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
799 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
800 */
801static int __init
802add_bridge(struct device_node *dev)
803{
804 int len;
805 struct pci_controller *hose;
806 struct reg_property *addr;
807 char* disp_name;
808 int *bus_range;
809 int primary = 1;
810
811 DBG("Adding PCI host bridge %s\n", dev->full_name);
812
813 addr = (struct reg_property *) get_property(dev, "reg", &len);
814 if (addr == NULL || len < sizeof(*addr)) {
815 printk(KERN_WARNING "Can't use %s: no address\n",
816 dev->full_name);
817 return -ENODEV;
818 }
819 bus_range = (int *) get_property(dev, "bus-range", &len);
820 if (bus_range == NULL || len < 2 * sizeof(int)) {
821 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
822 dev->full_name);
823 }
824
825 hose = pcibios_alloc_controller();
826 if (!hose)
827 return -ENOMEM;
828 hose->arch_data = dev;
829 hose->first_busno = bus_range ? bus_range[0] : 0;
830 hose->last_busno = bus_range ? bus_range[1] : 0xff;
831
832 disp_name = NULL;
833#ifdef CONFIG_POWER4
834 if (device_is_compatible(dev, "u3-agp")) {
835 setup_u3_agp(hose, addr);
836 disp_name = "U3-AGP";
837 primary = 0;
838 } else if (device_is_compatible(dev, "u3-ht")) {
839 setup_u3_ht(hose, addr);
840 disp_name = "U3-HT";
841 primary = 1;
842 } else
843#endif /* CONFIG_POWER4 */
844 if (device_is_compatible(dev, "uni-north")) {
845 primary = setup_uninorth(hose, addr);
846 disp_name = "UniNorth";
847 } else if (strcmp(dev->name, "pci") == 0) {
848 /* XXX assume this is a mpc106 (grackle) */
849 setup_grackle(hose);
850 disp_name = "Grackle (MPC106)";
851 } else if (strcmp(dev->name, "bandit") == 0) {
852 setup_bandit(hose, addr);
853 disp_name = "Bandit";
854 } else if (strcmp(dev->name, "chaos") == 0) {
855 setup_chaos(hose, addr);
856 disp_name = "Chaos";
857 primary = 0;
858 }
859 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
860 disp_name, addr->address, hose->first_busno, hose->last_busno);
861 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
862 hose, hose->cfg_addr, hose->cfg_data);
863
864 /* Interpret the "ranges" property */
865 /* This also maps the I/O region and sets isa_io/mem_base */
866 pci_process_bridge_OF_ranges(hose, dev, primary);
867
868 /* Fixup "bus-range" OF property */
869 fixup_bus_range(dev);
870
871 return 0;
872}
873
874static void __init
875pcibios_fixup_OF_interrupts(void)
876{
877 struct pci_dev* dev = NULL;
878
879 /*
880 * Open Firmware often doesn't initialize the
881 * PCI_INTERRUPT_LINE config register properly, so we
882 * should find the device node and apply the interrupt
883 * obtained from the OF device-tree
884 */
885 for_each_pci_dev(dev) {
886 struct device_node *node;
887 node = pci_device_to_OF_node(dev);
888 /* this is the node, see if it has interrupts */
889 if (node && node->n_intrs > 0)
890 dev->irq = node->intrs[0].line;
891 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
892 }
893}
894
895void __init
896pmac_pcibios_fixup(void)
897{
898 /* Fixup interrupts according to OF tree */
899 pcibios_fixup_OF_interrupts();
900}
901
902int
903pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
904{
905 struct device_node* node;
906 int updatecfg = 0;
907 int uninorth_child;
908
909 node = pci_device_to_OF_node(dev);
910
911 /* We don't want to enable USB controllers absent from the OF tree
912 * (iBook second controller)
913 */
914 if (dev->vendor == PCI_VENDOR_ID_APPLE
915 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
916 && !node) {
917 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
918 pci_name(dev));
919 return -EINVAL;
920 }
921
922 if (!node)
923 return 0;
924
925 uninorth_child = node->parent &&
926 device_is_compatible(node->parent, "uni-north");
927
928 /* Firewire & GMAC were disabled after PCI probe, the driver is
929 * claiming them, we must re-enable them now.
930 */
931 if (uninorth_child && !strcmp(node->name, "firewire") &&
932 (device_is_compatible(node, "pci106b,18") ||
933 device_is_compatible(node, "pci106b,30") ||
934 device_is_compatible(node, "pci11c1,5811"))) {
935 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
936 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
937 updatecfg = 1;
938 }
939 if (uninorth_child && !strcmp(node->name, "ethernet") &&
940 device_is_compatible(node, "gmac")) {
941 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
942 updatecfg = 1;
943 }
944
945 if (updatecfg) {
946 u16 cmd;
947
948 /*
949 * Make sure PCI is correctly configured
950 *
951 * We use old pci_bios versions of the function since, by
952 * default, gmac is not powered up, and so will be absent
953 * from the kernel initial PCI lookup.
954 *
955 * Should be replaced by 2.4 new PCI mechanisms and really
956 * register the device.
957 */
958 pci_read_config_word(dev, PCI_COMMAND, &cmd);
959 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
960 pci_write_config_word(dev, PCI_COMMAND, cmd);
961 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
962 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
963 }
964
965 return 0;
966}
967
968/* We power down some devices after they have been probed. They'll
969 * be powered back on later on
970 */
971void __init
972pmac_pcibios_after_init(void)
973{
974 struct device_node* nd;
975
976#ifdef CONFIG_BLK_DEV_IDE
977 struct pci_dev *dev = NULL;
978
979 /* OF fails to initialize IDE controllers on macs
980 * (and maybe other machines)
981 *
982 * Ideally, this should be moved to the IDE layer, but we need
983 * to check specifically with Andre Hedrick how to do it cleanly
984 * since the common IDE code seem to care about the fact that the
985 * BIOS may have disabled a controller.
986 *
987 * -- BenH
988 */
989 for_each_pci_dev(dev) {
990 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
991 pci_enable_device(dev);
992 }
993#endif /* CONFIG_BLK_DEV_IDE */
994
995 nd = find_devices("firewire");
996 while (nd) {
997 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
998 device_is_compatible(nd, "pci106b,30") ||
999 device_is_compatible(nd, "pci11c1,5811"))
1000 && device_is_compatible(nd->parent, "uni-north")) {
1001 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1002 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1003 }
1004 nd = nd->next;
1005 }
1006 nd = find_devices("ethernet");
1007 while (nd) {
1008 if (nd->parent && device_is_compatible(nd, "gmac")
1009 && device_is_compatible(nd->parent, "uni-north"))
1010 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1011 nd = nd->next;
1012 }
1013}
1014
1015void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1016{
1017 if (_machine != _MACH_Pmac)
1018 return;
1019 /*
1020 * Fix the interrupt routing on the various cardbus bridges
1021 * used on powerbooks
1022 */
1023 if (dev->vendor != PCI_VENDOR_ID_TI)
1024 return;
1025 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1026 dev->device == PCI_DEVICE_ID_TI_1131) {
1027 u8 val;
1028 /* Enable PCI interrupt */
1029 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1030 pci_write_config_byte(dev, 0x91, val | 0x30);
1031 /* Disable ISA interrupt mode */
1032 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1033 pci_write_config_byte(dev, 0x92, val & ~0x06);
1034 }
1035 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1036 dev->device == PCI_DEVICE_ID_TI_1211 ||
1037 dev->device == PCI_DEVICE_ID_TI_1410 ||
1038 dev->device == PCI_DEVICE_ID_TI_1510) {
1039 u8 val;
1040 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1041 signal out the MFUNC0 pin */
1042 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1043 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1044 /* Disable ISA interrupt mode */
1045 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1046 pci_write_config_byte(dev, 0x92, val & ~0x06);
1047 }
1048}
1049
1050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1051
1052void pmac_pci_fixup_pciata(struct pci_dev* dev)
1053{
1054 u8 progif = 0;
1055
1056 /*
1057 * On PowerMacs, we try to switch any PCI ATA controller to
1058 * fully native mode
1059 */
1060 if (_machine != _MACH_Pmac)
1061 return;
1062 /* Some controllers don't have the class IDE */
1063 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1064 switch(dev->device) {
1065 case PCI_DEVICE_ID_PROMISE_20246:
1066 case PCI_DEVICE_ID_PROMISE_20262:
1067 case PCI_DEVICE_ID_PROMISE_20263:
1068 case PCI_DEVICE_ID_PROMISE_20265:
1069 case PCI_DEVICE_ID_PROMISE_20267:
1070 case PCI_DEVICE_ID_PROMISE_20268:
1071 case PCI_DEVICE_ID_PROMISE_20269:
1072 case PCI_DEVICE_ID_PROMISE_20270:
1073 case PCI_DEVICE_ID_PROMISE_20271:
1074 case PCI_DEVICE_ID_PROMISE_20275:
1075 case PCI_DEVICE_ID_PROMISE_20276:
1076 case PCI_DEVICE_ID_PROMISE_20277:
1077 goto good;
1078 }
1079 /* Others, check PCI class */
1080 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1081 return;
1082 good:
1083 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1084 if ((progif & 5) != 5) {
1085 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1086 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1087 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1088 (progif & 5) != 5)
1089 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1090 }
1091}
1092DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1093
1094
1095/*
1096 * Disable second function on K2-SATA, it's broken
1097 * and disable IO BARs on first one
1098 */
1099void pmac_pci_fixup_k2_sata(struct pci_dev* dev)
1100{
1101 int i;
1102 u16 cmd;
1103
1104 if (PCI_FUNC(dev->devfn) > 0) {
1105 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1106 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1107 pci_write_config_word(dev, PCI_COMMAND, cmd);
1108 for (i = 0; i < 6; i++) {
1109 dev->resource[i].start = dev->resource[i].end = 0;
1110 dev->resource[i].flags = 0;
1111 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1112 }
1113 } else {
1114 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1115 cmd &= ~PCI_COMMAND_IO;
1116 pci_write_config_word(dev, PCI_COMMAND, cmd);
1117 for (i = 0; i < 5; i++) {
1118 dev->resource[i].start = dev->resource[i].end = 0;
1119 dev->resource[i].flags = 0;
1120 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1121 }
1122 }
1123}
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 19:43:31 -0500