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-rw-r--r--arch/ppc/platforms/chrp_setup.c669
1 files changed, 0 insertions, 669 deletions
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
deleted file mode 100644
index f9fd3f4f8e2e..000000000000
--- a/arch/ppc/platforms/chrp_setup.c
+++ /dev/null
@@ -1,669 +0,0 @@
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
5 */
6
7/*
8 * bootup setup stuff..
9 */
10
11#include <linux/config.h>
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/stddef.h>
17#include <linux/unistd.h>
18#include <linux/ptrace.h>
19#include <linux/slab.h>
20#include <linux/user.h>
21#include <linux/a.out.h>
22#include <linux/tty.h>
23#include <linux/major.h>
24#include <linux/interrupt.h>
25#include <linux/reboot.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/version.h>
29#include <linux/adb.h>
30#include <linux/module.h>
31#include <linux/delay.h>
32#include <linux/ide.h>
33#include <linux/console.h>
34#include <linux/seq_file.h>
35#include <linux/root_dev.h>
36#include <linux/initrd.h>
37#include <linux/module.h>
38
39#include <asm/io.h>
40#include <asm/pgtable.h>
41#include <asm/prom.h>
42#include <asm/gg2.h>
43#include <asm/pci-bridge.h>
44#include <asm/dma.h>
45#include <asm/machdep.h>
46#include <asm/irq.h>
47#include <asm/hydra.h>
48#include <asm/sections.h>
49#include <asm/time.h>
50#include <asm/btext.h>
51#include <asm/i8259.h>
52#include <asm/open_pic.h>
53#include <asm/xmon.h>
54#include "mem_pieces.h"
55
56unsigned long chrp_get_rtc_time(void);
57int chrp_set_rtc_time(unsigned long nowtime);
58void chrp_calibrate_decr(void);
59long chrp_time_init(void);
60
61void chrp_find_bridges(void);
62void chrp_event_scan(void);
63void rtas_display_progress(char *, unsigned short);
64void rtas_indicator_progress(char *, unsigned short);
65void btext_progress(char *, unsigned short);
66
67extern int of_show_percpuinfo(struct seq_file *, int);
68
69int _chrp_type;
70EXPORT_SYMBOL(_chrp_type);
71
72/*
73 * XXX this should be in xmon.h, but putting it there means xmon.h
74 * has to include <linux/interrupt.h> (to get irqreturn_t), which
75 * causes all sorts of problems. -- paulus
76 */
77extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
78
79extern dev_t boot_dev;
80
81extern PTE *Hash, *Hash_end;
82extern unsigned long Hash_size, Hash_mask;
83extern int probingmem;
84extern unsigned long loops_per_jiffy;
85static int max_width;
86
87#ifdef CONFIG_SMP
88extern struct smp_ops_t chrp_smp_ops;
89#endif
90
91static const char *gg2_memtypes[4] = {
92 "FPM", "SDRAM", "EDO", "BEDO"
93};
94static const char *gg2_cachesizes[4] = {
95 "256 KB", "512 KB", "1 MB", "Reserved"
96};
97static const char *gg2_cachetypes[4] = {
98 "Asynchronous", "Reserved", "Flow-Through Synchronous",
99 "Pipelined Synchronous"
100};
101static const char *gg2_cachemodes[4] = {
102 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
103};
104
105int
106chrp_show_cpuinfo(struct seq_file *m)
107{
108 int i, sdramen;
109 unsigned int t;
110 struct device_node *root;
111 const char *model = "";
112
113 root = find_path_device("/");
114 if (root)
115 model = get_property(root, "model", NULL);
116 seq_printf(m, "machine\t\t: CHRP %s\n", model);
117
118 /* longtrail (goldengate) stuff */
119 if (!strncmp(model, "IBM,LongTrail", 13)) {
120 /* VLSI VAS96011/12 `Golden Gate 2' */
121 /* Memory banks */
122 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
123 >>31) & 1;
124 for (i = 0; i < (sdramen ? 4 : 6); i++) {
125 t = in_le32(gg2_pci_config_base+
126 GG2_PCI_DRAM_BANK0+
127 i*4);
128 if (!(t & 1))
129 continue;
130 switch ((t>>8) & 0x1f) {
131 case 0x1f:
132 model = "4 MB";
133 break;
134 case 0x1e:
135 model = "8 MB";
136 break;
137 case 0x1c:
138 model = "16 MB";
139 break;
140 case 0x18:
141 model = "32 MB";
142 break;
143 case 0x10:
144 model = "64 MB";
145 break;
146 case 0x00:
147 model = "128 MB";
148 break;
149 default:
150 model = "Reserved";
151 break;
152 }
153 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
154 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
155 }
156 /* L2 cache */
157 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
158 seq_printf(m, "board l2\t: %s %s (%s)\n",
159 gg2_cachesizes[(t>>7) & 3],
160 gg2_cachetypes[(t>>2) & 3],
161 gg2_cachemodes[t & 3]);
162 }
163 return 0;
164}
165
166/*
167 * Fixes for the National Semiconductor PC78308VUL SuperI/O
168 *
169 * Some versions of Open Firmware incorrectly initialize the IRQ settings
170 * for keyboard and mouse
171 */
172static inline void __init sio_write(u8 val, u8 index)
173{
174 outb(index, 0x15c);
175 outb(val, 0x15d);
176}
177
178static inline u8 __init sio_read(u8 index)
179{
180 outb(index, 0x15c);
181 return inb(0x15d);
182}
183
184static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
185 u8 type)
186{
187 u8 level0, type0, active;
188
189 /* select logical device */
190 sio_write(device, 0x07);
191 active = sio_read(0x30);
192 level0 = sio_read(0x70);
193 type0 = sio_read(0x71);
194 if (level0 != level || type0 != type || !active) {
195 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
196 "remapping to level %d, type %d, active\n",
197 name, level0, type0, !active ? "in" : "", level, type);
198 sio_write(0x01, 0x30);
199 sio_write(level, 0x70);
200 sio_write(type, 0x71);
201 }
202}
203
204static void __init sio_init(void)
205{
206 struct device_node *root;
207
208 if ((root = find_path_device("/")) &&
209 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
210 /* logical device 0 (KBC/Keyboard) */
211 sio_fixup_irq("keyboard", 0, 1, 2);
212 /* select logical device 1 (KBC/Mouse) */
213 sio_fixup_irq("mouse", 1, 12, 2);
214 }
215}
216
217
218static void __init pegasos_set_l2cr(void)
219{
220 struct device_node *np;
221
222 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
223 if (_chrp_type != _CHRP_Pegasos)
224 return;
225
226 /* Enable L2 cache if needed */
227 np = find_type_devices("cpu");
228 if (np != NULL) {
229 unsigned int *l2cr = (unsigned int *)
230 get_property (np, "l2cr", NULL);
231 if (l2cr == NULL) {
232 printk ("Pegasos l2cr : no cpu l2cr property found\n");
233 return;
234 }
235 if (!((*l2cr) & 0x80000000)) {
236 printk ("Pegasos l2cr : L2 cache was not active, "
237 "activating\n");
238 _set_L2CR(0);
239 _set_L2CR((*l2cr) | 0x80000000);
240 }
241 }
242}
243
244void __init chrp_setup_arch(void)
245{
246 struct device_node *device;
247
248 /* init to some ~sane value until calibrate_delay() runs */
249 loops_per_jiffy = 50000000/HZ;
250
251#ifdef CONFIG_BLK_DEV_INITRD
252 /* this is fine for chrp */
253 initrd_below_start_ok = 1;
254
255 if (initrd_start)
256 ROOT_DEV = Root_RAM0;
257 else
258#endif
259 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
260
261 /* On pegasos, enable the L2 cache if not already done by OF */
262 pegasos_set_l2cr();
263
264 /* Lookup PCI host bridges */
265 chrp_find_bridges();
266
267#ifndef CONFIG_PPC64BRIDGE
268 /*
269 * Temporary fixes for PCI devices.
270 * -- Geert
271 */
272 hydra_init(); /* Mac I/O */
273
274#endif /* CONFIG_PPC64BRIDGE */
275
276 /*
277 * Fix the Super I/O configuration
278 */
279 sio_init();
280
281 /* Get the event scan rate for the rtas so we know how
282 * often it expects a heartbeat. -- Cort
283 */
284 if ( rtas_data ) {
285 struct property *p;
286 device = find_devices("rtas");
287 for ( p = device->properties;
288 p && strncmp(p->name, "rtas-event-scan-rate", 20);
289 p = p->next )
290 /* nothing */ ;
291 if ( p && *(unsigned long *)p->value ) {
292 ppc_md.heartbeat = chrp_event_scan;
293 ppc_md.heartbeat_reset = (HZ/(*(unsigned long *)p->value)*30)-1;
294 ppc_md.heartbeat_count = 1;
295 printk("RTAS Event Scan Rate: %lu (%lu jiffies)\n",
296 *(unsigned long *)p->value, ppc_md.heartbeat_reset );
297 }
298 }
299
300 pci_create_OF_bus_map();
301}
302
303void
304chrp_event_scan(void)
305{
306 unsigned char log[1024];
307 unsigned long ret = 0;
308 /* XXX: we should loop until the hardware says no more error logs -- Cort */
309 call_rtas( "event-scan", 4, 1, &ret, 0xffffffff, 0,
310 __pa(log), 1024 );
311 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
312}
313
314void
315chrp_restart(char *cmd)
316{
317 printk("RTAS system-reboot returned %d\n",
318 call_rtas("system-reboot", 0, 1, NULL));
319 for (;;);
320}
321
322void
323chrp_power_off(void)
324{
325 /* allow power on only with power button press */
326 printk("RTAS power-off returned %d\n",
327 call_rtas("power-off", 2, 1, NULL,0xffffffff,0xffffffff));
328 for (;;);
329}
330
331void
332chrp_halt(void)
333{
334 chrp_power_off();
335}
336
337/*
338 * Finds the open-pic node and sets OpenPIC_Addr based on its reg property.
339 * Then checks if it has an interrupt-ranges property. If it does then
340 * we have a distributed open-pic, so call openpic_set_sources to tell
341 * the openpic code where to find the interrupt source registers.
342 */
343static void __init chrp_find_openpic(void)
344{
345 struct device_node *np;
346 int len, i;
347 unsigned int *iranges;
348 void __iomem *isu;
349
350 np = find_type_devices("open-pic");
351 if (np == NULL || np->n_addrs == 0)
352 return;
353 printk(KERN_INFO "OpenPIC at %x (size %x)\n",
354 np->addrs[0].address, np->addrs[0].size);
355 OpenPIC_Addr = ioremap(np->addrs[0].address, 0x40000);
356 if (OpenPIC_Addr == NULL) {
357 printk(KERN_ERR "Failed to map OpenPIC!\n");
358 return;
359 }
360
361 iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
362 if (iranges == NULL || len < 2 * sizeof(unsigned int))
363 return; /* not distributed */
364
365 /*
366 * The first pair of cells in interrupt-ranges refers to the
367 * IDU; subsequent pairs refer to the ISUs.
368 */
369 len /= 2 * sizeof(unsigned int);
370 if (np->n_addrs < len) {
371 printk(KERN_ERR "Insufficient addresses for distributed"
372 " OpenPIC (%d < %d)\n", np->n_addrs, len);
373 return;
374 }
375 if (iranges[1] != 0) {
376 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
377 iranges[0], iranges[0] + iranges[1] - 1);
378 openpic_set_sources(iranges[0], iranges[1], NULL);
379 }
380 for (i = 1; i < len; ++i) {
381 iranges += 2;
382 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x (%x)\n",
383 iranges[0], iranges[0] + iranges[1] - 1,
384 np->addrs[i].address, np->addrs[i].size);
385 isu = ioremap(np->addrs[i].address, np->addrs[i].size);
386 if (isu != NULL)
387 openpic_set_sources(iranges[0], iranges[1], isu);
388 else
389 printk(KERN_ERR "Failed to map OpenPIC ISU at %x!\n",
390 np->addrs[i].address);
391 }
392}
393
394#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
395static struct irqaction xmon_irqaction = {
396 .handler = xmon_irq,
397 .mask = CPU_MASK_NONE,
398 .name = "XMON break",
399};
400#endif
401
402void __init chrp_init_IRQ(void)
403{
404 struct device_node *np;
405 unsigned long chrp_int_ack = 0;
406 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
407#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
408 struct device_node *kbd;
409#endif
410
411 for (np = find_devices("pci"); np != NULL; np = np->next) {
412 unsigned int *addrp = (unsigned int *)
413 get_property(np, "8259-interrupt-acknowledge", NULL);
414
415 if (addrp == NULL)
416 continue;
417 chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
418 break;
419 }
420 if (np == NULL)
421 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
422
423 chrp_find_openpic();
424
425 if (OpenPIC_Addr) {
426 prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
427 OpenPIC_InitSenses = init_senses;
428 OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
429
430 openpic_init(NUM_8259_INTERRUPTS);
431 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
432 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
433 i8259_irq);
434
435 }
436 i8259_init(chrp_int_ack, 0);
437
438#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
439 /* see if there is a keyboard in the device tree
440 with a parent of type "adb" */
441 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
442 if (kbd->parent && kbd->parent->type
443 && strcmp(kbd->parent->type, "adb") == 0)
444 break;
445 if (kbd)
446 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
447#endif
448}
449
450void __init
451chrp_init2(void)
452{
453#ifdef CONFIG_NVRAM
454 chrp_nvram_init();
455#endif
456
457 request_region(0x20,0x20,"pic1");
458 request_region(0xa0,0x20,"pic2");
459 request_region(0x00,0x20,"dma1");
460 request_region(0x40,0x20,"timer");
461 request_region(0x80,0x10,"dma page reg");
462 request_region(0xc0,0x20,"dma2");
463
464 if (ppc_md.progress)
465 ppc_md.progress(" Have fun! ", 0x7777);
466}
467
468static struct device_node *memory_node;
469
470static int __init get_mem_prop(char *name, struct mem_pieces *mp)
471{
472 struct reg_property *rp;
473 int i, s;
474 unsigned int *ip;
475 int nac = prom_n_addr_cells(memory_node);
476 int nsc = prom_n_size_cells(memory_node);
477
478 ip = (unsigned int *) get_property(memory_node, name, &s);
479 if (ip == NULL) {
480 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
481 name);
482 return 0;
483 }
484 s /= (nsc + nac) * 4;
485 rp = mp->regions;
486 for (i = 0; i < s; ++i, ip += nac+nsc) {
487 if (nac >= 2 && ip[nac-2] != 0)
488 continue;
489 rp->address = ip[nac-1];
490 if (nsc >= 2 && ip[nac+nsc-2] != 0)
491 rp->size = ~0U;
492 else
493 rp->size = ip[nac+nsc-1];
494 ++rp;
495 }
496 mp->n_regions = rp - mp->regions;
497
498 /* Make sure the pieces are sorted. */
499 mem_pieces_sort(mp);
500 mem_pieces_coalesce(mp);
501 return 1;
502}
503
504static unsigned long __init chrp_find_end_of_memory(void)
505{
506 unsigned long a, total;
507 struct mem_pieces phys_mem;
508
509 /*
510 * Find out where physical memory is, and check that it
511 * starts at 0 and is contiguous. It seems that RAM is
512 * always physically contiguous on Power Macintoshes.
513 *
514 * Supporting discontiguous physical memory isn't hard,
515 * it just makes the virtual <-> physical mapping functions
516 * more complicated (or else you end up wasting space
517 * in mem_map).
518 */
519 memory_node = find_devices("memory");
520 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
521 || phys_mem.n_regions == 0)
522 panic("No RAM??");
523 a = phys_mem.regions[0].address;
524 if (a != 0)
525 panic("RAM doesn't start at physical address 0");
526 total = phys_mem.regions[0].size;
527
528 if (phys_mem.n_regions > 1) {
529 printk("RAM starting at 0x%x is not contiguous\n",
530 phys_mem.regions[1].address);
531 printk("Using RAM from 0 to 0x%lx\n", total-1);
532 }
533
534 return total;
535}
536
537void __init
538chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
539 unsigned long r6, unsigned long r7)
540{
541 struct device_node *root = find_path_device ("/");
542 char *machine = NULL;
543
544#ifdef CONFIG_BLK_DEV_INITRD
545 /* take care of initrd if we have one */
546 if ( r6 )
547 {
548 initrd_start = r6 + KERNELBASE;
549 initrd_end = r6 + r7 + KERNELBASE;
550 }
551#endif /* CONFIG_BLK_DEV_INITRD */
552
553 ISA_DMA_THRESHOLD = ~0L;
554 DMA_MODE_READ = 0x44;
555 DMA_MODE_WRITE = 0x48;
556 isa_io_base = CHRP_ISA_IO_BASE; /* default value */
557 ppc_do_canonicalize_irqs = 1;
558
559 if (root)
560 machine = get_property(root, "model", NULL);
561 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
562 _chrp_type = _CHRP_Pegasos;
563 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
564 _chrp_type = _CHRP_IBM;
565 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
566 _chrp_type = _CHRP_Motorola;
567 } else {
568 /* Let's assume it is an IBM chrp if all else fails */
569 _chrp_type = _CHRP_IBM;
570 }
571
572 ppc_md.setup_arch = chrp_setup_arch;
573 ppc_md.show_percpuinfo = of_show_percpuinfo;
574 ppc_md.show_cpuinfo = chrp_show_cpuinfo;
575
576 ppc_md.init_IRQ = chrp_init_IRQ;
577 if (_chrp_type == _CHRP_Pegasos)
578 ppc_md.get_irq = i8259_irq;
579 else
580 ppc_md.get_irq = openpic_get_irq;
581
582 ppc_md.init = chrp_init2;
583
584 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
585
586 ppc_md.restart = chrp_restart;
587 ppc_md.power_off = chrp_power_off;
588 ppc_md.halt = chrp_halt;
589
590 ppc_md.time_init = chrp_time_init;
591 ppc_md.set_rtc_time = chrp_set_rtc_time;
592 ppc_md.get_rtc_time = chrp_get_rtc_time;
593 ppc_md.calibrate_decr = chrp_calibrate_decr;
594
595 ppc_md.find_end_of_memory = chrp_find_end_of_memory;
596
597 if (rtas_data) {
598 struct device_node *rtas;
599 unsigned int *p;
600
601 rtas = find_devices("rtas");
602 if (rtas != NULL) {
603 if (get_property(rtas, "display-character", NULL)) {
604 ppc_md.progress = rtas_display_progress;
605 p = (unsigned int *) get_property
606 (rtas, "ibm,display-line-length", NULL);
607 if (p)
608 max_width = *p;
609 } else if (get_property(rtas, "set-indicator", NULL))
610 ppc_md.progress = rtas_indicator_progress;
611 }
612 }
613#ifdef CONFIG_BOOTX_TEXT
614 if (ppc_md.progress == NULL && boot_text_mapped)
615 ppc_md.progress = btext_progress;
616#endif
617
618#ifdef CONFIG_SMP
619 smp_ops = &chrp_smp_ops;
620#endif /* CONFIG_SMP */
621
622 /*
623 * Print the banner, then scroll down so boot progress
624 * can be printed. -- Cort
625 */
626 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
627}
628
629void
630rtas_display_progress(char *s, unsigned short hex)
631{
632 int width;
633 char *os = s;
634
635 if ( call_rtas( "display-character", 1, 1, NULL, '\r' ) )
636 return;
637
638 width = max_width;
639 while ( *os )
640 {
641 if ( (*os == '\n') || (*os == '\r') )
642 width = max_width;
643 else
644 width--;
645 call_rtas( "display-character", 1, 1, NULL, *os++ );
646 /* if we overwrite the screen length */
647 if ( width == 0 )
648 while ( (*os != 0) && (*os != '\n') && (*os != '\r') )
649 os++;
650 }
651
652 /*while ( width-- > 0 )*/
653 call_rtas( "display-character", 1, 1, NULL, ' ' );
654}
655
656void
657rtas_indicator_progress(char *s, unsigned short hex)
658{
659 call_rtas("set-indicator", 3, 1, NULL, 6, 0, hex);
660}
661
662#ifdef CONFIG_BOOTX_TEXT
663void
664btext_progress(char *s, unsigned short hex)
665{
666 prom_print(s);
667 prom_print("\n");
668}
669#endif /* CONFIG_BOOTX_TEXT */
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