1 files changed, 309 insertions, 0 deletions
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
new file mode 100644
index 000000000000..5bb6492ecf8c
--- /dev/null
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -0,0 +1,309 @@
+/*
+ * CHRP pci routines.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+#include <linux/bootmem.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/hydra.h>
+#include <asm/prom.h>
+#include <asm/gg2.h>
+#include <asm/machdep.h>
+#include <asm/sections.h>
+#include <asm/pci-bridge.h>
+#include <asm/open_pic.h>
+/* LongTrail */
+void __iomem *gg2_pci_config_base;
+/*
+ * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
+ * limit the bus number to 3 bits
+ */
+int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
+                           int len, u32 *val)
+{
+        volatile void __iomem *cfg_data;
+        struct pci_controller *hose = bus->sysdata;
+        if (bus->number > 7)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        /*
+         * Note: the caller has already checked that off is
+         * suitably aligned and that len is 1, 2 or 4.
+         */
+        cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
+        switch (len) {
+        case 1:
+                *val =  in_8(cfg_data);
+                break;
+        case 2:
+                *val = in_le16(cfg_data);
+                break;
+        default:
+                *val = in_le32(cfg_data);
+                break;
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
+                            int len, u32 val)
+{
+        volatile void __iomem *cfg_data;
+        struct pci_controller *hose = bus->sysdata;
+        if (bus->number > 7)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        /*
+         * Note: the caller has already checked that off is
+         * suitably aligned and that len is 1, 2 or 4.
+         */
+        cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
+        switch (len) {
+        case 1:
+                out_8(cfg_data, val);
+                break;
+        case 2:
+                out_le16(cfg_data, val);
+                break;
+        default:
+                out_le32(cfg_data, val);
+                break;
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+static struct pci_ops gg2_pci_ops =
+{
+        gg2_read_config,
+        gg2_write_config
+};
+/*
+ * Access functions for PCI config space using RTAS calls.
+ */
+int __chrp
+rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
+                 int len, u32 *val)
+{
+        struct pci_controller *hose = bus->sysdata;
+        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+                | (((bus->number - hose->first_busno) & 0xff) << 16)
+                | (hose->index << 24);
+        unsigned long ret = ~0UL;
+        int rval;
+        rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len);
+        *val = ret;
+        return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
+}
+int __chrp
+rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
+                  int len, u32 val)
+{
+        struct pci_controller *hose = bus->sysdata;
+        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+                | (((bus->number - hose->first_busno) & 0xff) << 16)
+                | (hose->index << 24);
+        int rval;
+        rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
+        return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
+}
+static struct pci_ops rtas_pci_ops =
+{
+        rtas_read_config,
+        rtas_write_config
+};
+volatile struct Hydra *Hydra = NULL;
+int __init
+hydra_init(void)
+{
+        struct device_node *np;
+        np = find_devices("mac-io");
+        if (np == NULL || np->n_addrs == 0)
+                return 0;
+        Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
+        printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
+        printk("Hydra Feature_Control was %x",
+               in_le32(&Hydra->Feature_Control));
+        out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
+                                           HYDRA_FC_SCSI_CELL_EN |
+                                           HYDRA_FC_SCCA_ENABLE |
+                                           HYDRA_FC_SCCB_ENABLE |
+                                           HYDRA_FC_ARB_BYPASS |
+                                           HYDRA_FC_MPIC_ENABLE |
+                                           HYDRA_FC_SLOW_SCC_PCLK |
+                                           HYDRA_FC_MPIC_IS_MASTER));
+        printk(", now %x\n", in_le32(&Hydra->Feature_Control));
+        return 1;
+}
+void __init
+chrp_pcibios_fixup(void)
+{
+        struct pci_dev *dev = NULL;
+        struct device_node *np;
+        /* PCI interrupts are controlled by the OpenPIC */
+        for_each_pci_dev(dev) {
+                np = pci_device_to_OF_node(dev);
+                if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
+                        dev->irq = np->intrs[0].line;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+        }
+}
+#define PRG_CL_RESET_VALID 0x00010000
+static void __init
+setup_python(struct pci_controller *hose, struct device_node *dev)
+{
+        u32 *reg, val;
+        unsigned long addr = dev->addrs[0].address;
+        setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
+        /* Clear the magic go-slow bit */
+        reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
+        val = in_be32(&reg[12]);
+        if (val & PRG_CL_RESET_VALID) {
+                out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
+                in_be32(&reg[12]);
+        }
+        iounmap(reg);
+}
+/* Marvell Discovery II based Pegasos 2 */
+static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
+{
+        struct device_node *root = find_path_device("/");
+        struct device_node *rtas;
+        rtas = of_find_node_by_name (root, "rtas");
+        if (rtas) {
+                hose->ops = &rtas_pci_ops;
+        } else {
+                printk ("RTAS supporting Pegasos OF not found, please upgrade"
+                        " your firmware\n");
+        }
+        pci_assign_all_busses = 1;
+}
+void __init
+chrp_find_bridges(void)
+{
+        struct device_node *dev;
+        int *bus_range;
+        int len, index = -1;
+        struct pci_controller *hose;
+        unsigned int *dma;
+        char *model, *machine;
+        int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
+        struct device_node *root = find_path_device("/");
+        /*
+         * The PCI host bridge nodes on some machines don't have
+         * properties to adequately identify them, so we have to
+         * look at what sort of machine this is as well.
+         */
+        machine = get_property(root, "model", NULL);
+        if (machine != NULL) {
+                is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
+                is_mot = strncmp(machine, "MOT", 3) == 0;
+                if (strncmp(machine, "Pegasos2", 8) == 0)
+                        is_pegasos = 2;
+                else if (strncmp(machine, "Pegasos", 7) == 0)
+                        is_pegasos = 1;
+        }
+        for (dev = root->child; dev != NULL; dev = dev->sibling) {
+                if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
+                        continue;
+                ++index;
+                /* The GG2 bridge on the LongTrail doesn't have an address */
+                if (dev->n_addrs < 1 && !is_longtrail) {
+                        printk(KERN_WARNING "Can't use %s: no address\n",
+                               dev->full_name);
+                        continue;
+                }
+                bus_range = (int *) get_property(dev, "bus-range", &len);
+                if (bus_range == NULL || len < 2 * sizeof(int)) {
+                        printk(KERN_WARNING "Can't get bus-range for %s\n",
+                                dev->full_name);
+                        continue;
+                }
+                if (bus_range[1] == bus_range[0])
+                        printk(KERN_INFO "PCI bus %d", bus_range[0]);
+                else
+                        printk(KERN_INFO "PCI buses %d..%d",
+                               bus_range[0], bus_range[1]);
+                printk(" controlled by %s", dev->type);
+                if (dev->n_addrs > 0)
+                        printk(" at %x", dev->addrs[0].address);
+                printk("\n");
+                hose = pcibios_alloc_controller();
+                if (!hose) {
+                        printk("Can't allocate PCI controller structure for %s\n",
+                                dev->full_name);
+                        continue;
+                }
+                hose->arch_data = dev;
+                hose->first_busno = bus_range[0];
+                hose->last_busno = bus_range[1];
+                model = get_property(dev, "model", NULL);
+                if (model == NULL)
+                        model = "<none>";
+                if (device_is_compatible(dev, "IBM,python")) {
+                        setup_python(hose, dev);
+                } else if (is_mot
+                           || strncmp(model, "Motorola, Grackle", 17) == 0) {
+                        setup_grackle(hose);
+                } else if (is_longtrail) {
+                        void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
+                        hose->ops = &gg2_pci_ops;
+                        hose->cfg_data = p;
+                        gg2_pci_config_base = p;
+                } else if (is_pegasos == 1) {
+                        setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
+                } else if (is_pegasos == 2) {
+                        setup_peg2(hose, dev);
+                } else {
+                        printk("No methods for %s (model %s), using RTAS\n",
+                               dev->full_name, model);
+                        hose->ops = &rtas_pci_ops;
+                }
+                pci_process_bridge_OF_ranges(hose, dev, index == 0);
+                /* check the first bridge for a property that we can
+                   use to set pci_dram_offset */
+                dma = (unsigned int *)
+                        get_property(dev, "ibm,dma-ranges", &len);
+                if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
+                        pci_dram_offset = dma[2] - dma[3];
+                        printk("pci_dram_offset = %lx\n", pci_dram_offset);
+                }
+        }
+        /* Do not fixup interrupts from OF tree on pegasos */
+        if (is_pegasos == 0)
+                ppc_md.pcibios_fixup = chrp_pcibios_fixup;
+}

diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c new file mode 100644 index 000000000000..5bb6492ecf8c --- /dev/null +++ b/arch/ppc/platforms/chrp_pci.c
@@ -0,0 +1,309 @@
	1	/*
	2	* CHRP pci routines.
	3	*/
	4
	5	#include <linux/config.h>
	6	#include <linux/kernel.h>
	7	#include <linux/pci.h>
	8	#include <linux/delay.h>
	9	#include <linux/string.h>
	10	#include <linux/init.h>
	11	#include <linux/ide.h>
	12	#include <linux/bootmem.h>
	13
	14	#include <asm/io.h>
	15	#include <asm/pgtable.h>
	16	#include <asm/irq.h>
	17	#include <asm/hydra.h>
	18	#include <asm/prom.h>
	19	#include <asm/gg2.h>
	20	#include <asm/machdep.h>
	21	#include <asm/sections.h>
	22	#include <asm/pci-bridge.h>
	23	#include <asm/open_pic.h>
	24
	25	/* LongTrail */
	26	void __iomem *gg2_pci_config_base;
	27
	28	/*
	29	* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
	30	* limit the bus number to 3 bits
	31	*/
	32
	33	int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
	34	int len, u32 *val)
	35	{
	36	volatile void __iomem *cfg_data;
	37	struct pci_controller *hose = bus->sysdata;
	38
	39	if (bus->number > 7)
	40	return PCIBIOS_DEVICE_NOT_FOUND;
	41	/*
	42	* Note: the caller has already checked that off is
	43	* suitably aligned and that len is 1, 2 or 4.
	44	*/
	45	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	46	switch (len) {
	47	case 1:
	48	*val = in_8(cfg_data);
	49	break;
	50	case 2:
	51	*val = in_le16(cfg_data);
	52	break;
	53	default:
	54	*val = in_le32(cfg_data);
	55	break;
	56	}
	57	return PCIBIOS_SUCCESSFUL;
	58	}
	59
	60	int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
	61	int len, u32 val)
	62	{
	63	volatile void __iomem *cfg_data;
	64	struct pci_controller *hose = bus->sysdata;
	65
	66	if (bus->number > 7)
	67	return PCIBIOS_DEVICE_NOT_FOUND;
	68	/*
	69	* Note: the caller has already checked that off is
	70	* suitably aligned and that len is 1, 2 or 4.
	71	*/
	72	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	73	switch (len) {
	74	case 1:
	75	out_8(cfg_data, val);
	76	break;
	77	case 2:
	78	out_le16(cfg_data, val);
	79	break;
	80	default:
	81	out_le32(cfg_data, val);
	82	break;
	83	}
	84	return PCIBIOS_SUCCESSFUL;
	85	}
	86
	87	static struct pci_ops gg2_pci_ops =
	88	{
	89	gg2_read_config,
	90	gg2_write_config
	91	};
	92
	93	/*
	94	* Access functions for PCI config space using RTAS calls.
	95	*/
	96	int __chrp
	97	rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
	98	int len, u32 *val)
	99	{
	100	struct pci_controller *hose = bus->sysdata;
	101	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
	102	\| (((bus->number - hose->first_busno) & 0xff) << 16)
	103	\| (hose->index << 24);
	104	unsigned long ret = ~0UL;
	105	int rval;
	106
	107	rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len);
	108	*val = ret;
	109	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
	110	}
	111
	112	int __chrp
	113	rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
	114	int len, u32 val)
	115	{
	116	struct pci_controller *hose = bus->sysdata;
	117	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
	118	\| (((bus->number - hose->first_busno) & 0xff) << 16)
	119	\| (hose->index << 24);
	120	int rval;
	121
	122	rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
	123	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
	124	}
	125
	126	static struct pci_ops rtas_pci_ops =
	127	{
	128	rtas_read_config,
	129	rtas_write_config
	130	};
	131
	132	volatile struct Hydra *Hydra = NULL;
	133
	134	int __init
	135	hydra_init(void)
	136	{
	137	struct device_node *np;
	138
	139	np = find_devices("mac-io");
	140	if (np == NULL \|\| np->n_addrs == 0)
	141	return 0;
	142	Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
	143	printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
	144	printk("Hydra Feature_Control was %x",
	145	in_le32(&Hydra->Feature_Control));
	146	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN \|
	147	HYDRA_FC_SCSI_CELL_EN \|
	148	HYDRA_FC_SCCA_ENABLE \|
	149	HYDRA_FC_SCCB_ENABLE \|
	150	HYDRA_FC_ARB_BYPASS \|
	151	HYDRA_FC_MPIC_ENABLE \|
	152	HYDRA_FC_SLOW_SCC_PCLK \|
	153	HYDRA_FC_MPIC_IS_MASTER));
	154	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
	155	return 1;
	156	}
	157
	158	void __init
	159	chrp_pcibios_fixup(void)
	160	{
	161	struct pci_dev *dev = NULL;
	162	struct device_node *np;
	163
	164	/* PCI interrupts are controlled by the OpenPIC */
	165	for_each_pci_dev(dev) {
	166	np = pci_device_to_OF_node(dev);
	167	if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
	168	dev->irq = np->intrs[0].line;
	169	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	170	}
	171	}
	172
	173	#define PRG_CL_RESET_VALID 0x00010000
	174
	175	static void __init
	176	setup_python(struct pci_controller hose, struct device_node dev)
	177	{
	178	u32 *reg, val;
	179	unsigned long addr = dev->addrs[0].address;
	180
	181	setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
	182
	183	/* Clear the magic go-slow bit */
	184	reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
	185	val = in_be32(&reg[12]);
	186	if (val & PRG_CL_RESET_VALID) {
	187	out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
	188	in_be32(&reg[12]);
	189	}
	190	iounmap(reg);
	191	}
	192
	193	/* Marvell Discovery II based Pegasos 2 */
	194	static void __init setup_peg2(struct pci_controller hose, struct device_node dev)
	195	{
	196	struct device_node *root = find_path_device("/");
	197	struct device_node *rtas;
	198
	199	rtas = of_find_node_by_name (root, "rtas");
	200	if (rtas) {
	201	hose->ops = &rtas_pci_ops;
	202	} else {
	203	printk ("RTAS supporting Pegasos OF not found, please upgrade"
	204	" your firmware\n");
	205	}
	206	pci_assign_all_busses = 1;
	207	}
	208
	209	void __init
	210	chrp_find_bridges(void)
	211	{
	212	struct device_node *dev;
	213	int *bus_range;
	214	int len, index = -1;
	215	struct pci_controller *hose;
	216	unsigned int *dma;
	217	char model, machine;
	218	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
	219	struct device_node *root = find_path_device("/");
	220
	221	/*
	222	* The PCI host bridge nodes on some machines don't have
	223	* properties to adequately identify them, so we have to
	224	* look at what sort of machine this is as well.
	225	*/
	226	machine = get_property(root, "model", NULL);
	227	if (machine != NULL) {
	228	is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
	229	is_mot = strncmp(machine, "MOT", 3) == 0;
	230	if (strncmp(machine, "Pegasos2", 8) == 0)
	231	is_pegasos = 2;
	232	else if (strncmp(machine, "Pegasos", 7) == 0)
	233	is_pegasos = 1;
	234	}
	235	for (dev = root->child; dev != NULL; dev = dev->sibling) {
	236	if (dev->type == NULL \|\| strcmp(dev->type, "pci") != 0)
	237	continue;
	238	++index;
	239	/* The GG2 bridge on the LongTrail doesn't have an address */
	240	if (dev->n_addrs < 1 && !is_longtrail) {
	241	printk(KERN_WARNING "Can't use %s: no address\n",
	242	dev->full_name);
	243	continue;
	244	}
	245	bus_range = (int *) get_property(dev, "bus-range", &len);
	246	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	247	printk(KERN_WARNING "Can't get bus-range for %s\n",
	248	dev->full_name);
	249	continue;
	250	}
	251	if (bus_range[1] == bus_range[0])
	252	printk(KERN_INFO "PCI bus %d", bus_range[0]);
	253	else
	254	printk(KERN_INFO "PCI buses %d..%d",
	255	bus_range[0], bus_range[1]);
	256	printk(" controlled by %s", dev->type);
	257	if (dev->n_addrs > 0)
	258	printk(" at %x", dev->addrs[0].address);
	259	printk("\n");
	260
	261	hose = pcibios_alloc_controller();
	262	if (!hose) {
	263	printk("Can't allocate PCI controller structure for %s\n",
	264	dev->full_name);
	265	continue;
	266	}
	267	hose->arch_data = dev;
	268	hose->first_busno = bus_range[0];
	269	hose->last_busno = bus_range[1];
	270
	271	model = get_property(dev, "model", NULL);
	272	if (model == NULL)
	273	model = "<none>";
	274	if (device_is_compatible(dev, "IBM,python")) {
	275	setup_python(hose, dev);
	276	} else if (is_mot
	277	\|\| strncmp(model, "Motorola, Grackle", 17) == 0) {
	278	setup_grackle(hose);
	279	} else if (is_longtrail) {
	280	void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
	281	hose->ops = &gg2_pci_ops;
	282	hose->cfg_data = p;
	283	gg2_pci_config_base = p;
	284	} else if (is_pegasos == 1) {
	285	setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
	286	} else if (is_pegasos == 2) {
	287	setup_peg2(hose, dev);
	288	} else {
	289	printk("No methods for %s (model %s), using RTAS\n",
	290	dev->full_name, model);
	291	hose->ops = &rtas_pci_ops;
	292	}
	293
	294	pci_process_bridge_OF_ranges(hose, dev, index == 0);
	295
	296	/* check the first bridge for a property that we can
	297	use to set pci_dram_offset */
	298	dma = (unsigned int *)
	299	get_property(dev, "ibm,dma-ranges", &len);
	300	if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
	301	pci_dram_offset = dma[2] - dma[3];
	302	printk("pci_dram_offset = %lx\n", pci_dram_offset);
	303	}
	304	}
	305
	306	/* Do not fixup interrupts from OF tree on pegasos */
	307	if (is_pegasos == 0)
	308	ppc_md.pcibios_fixup = chrp_pcibios_fixup;
	309	}