2 files changed, 139 insertions, 2 deletions

diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index 11fb758d269f..c2a512735183 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -44,6 +44,7 @@
 #include <asm/machdep.h>
 #include <asm/prom.h>
 #include <asm/open_pic.h>
+#include <asm/i8259.h>
 #include <asm/bootinfo.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpc85xx.h>
@@ -181,6 +182,7 @@ void __init
 mpc85xx_cds_init_IRQ(void)
 {
         bd_t *binfo = (bd_t *) __res;
+        int i;
 
         /* Determine the Physical Address of the OpenPIC regs */
         phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -198,6 +200,13 @@ mpc85xx_cds_init_IRQ(void)
          */
         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 
+        openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
+
+        for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+                irq_desc[i].handler = &i8259_pic;
+
+        i8259_init(0);
+
 #ifdef CONFIG_CPM2
         /* Setup CPM2 PIC */
         cpm2_init_IRQ();
@@ -231,7 +240,7 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
                          * interrupt on slot */
                 {
                         { 0, 1, 2, 3 }, /* 16 - PMC */
-                        { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
+                        { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
                         { 0, 1, 2, 3 }, /* 18 - Slot 1 */
                         { 1, 2, 3, 0 }, /* 19 - Slot 2 */
                         { 2, 3, 0, 1 }, /* 20 - Slot 3 */
@@ -280,13 +289,135 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
                         return PCIBIOS_DEVICE_NOT_FOUND;
 #endif
         /* We explicitly do not go past the Tundra 320 Bridge */
-        if (bus == 1)
+        if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                 return PCIBIOS_DEVICE_NOT_FOUND;
         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                 return PCIBIOS_DEVICE_NOT_FOUND;
         else
                 return PCIBIOS_SUCCESSFUL;
 }
+
+void __init
+mpc85xx_cds_enable_via(struct pci_controller *hose)
+{
+        u32 pci_class;
+        u16 vid, did;
+
+        early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+        if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+                return;
+
+        /* Configure P2P so that we can reach bus 1 */
+        early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
+        early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
+        early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
+
+        early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+        early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+
+        if ((vid != PCI_VENDOR_ID_VIA) ||
+                        (did != PCI_DEVICE_ID_VIA_82C686))
+                return;
+
+        /* Enable USB and IDE functions */
+        early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
+}
+
+void __init
+mpc85xx_cds_fixup_via(struct pci_controller *hose)
+{
+        u32 pci_class;
+        u16 vid, did;
+
+        early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+        if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+                return;
+
+        /*
+         * Force the backplane P2P bridge to have a window
+         * open from 0x00000000-0x00001fff in PCI I/O space.
+         * This allows legacy I/O (i8259, etc) on the VIA
+         * southbridge to be accessed.
+         */
+        early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
+        early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
+        early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
+        early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
+
+        early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+        early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+        if ((vid != PCI_VENDOR_ID_VIA) ||
+                        (did != PCI_DEVICE_ID_VIA_82C686))
+                return;
+
+        /*
+         * Since the P2P window was forced to cover the fixed
+         * legacy I/O addresses, it is necessary to manually
+         * place the base addresses for the IDE and USB functions
+         * within this window.
+         */
+        /* Function 1, IDE */
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
+
+        /* Function 2, USB ports 0-1 */
+        early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
+
+        /* Function 3, USB ports 2-3 */
+        early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
+
+        /* Function 5, Power Management */
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
+
+        /* Function 6, AC97 Interface */
+        early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
+}
+
+void __init
+mpc85xx_cds_pcibios_fixup(void)
+{
+        struct pci_dev *dev = NULL;
+        u_char          c;
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
+                /*
+                 * U-Boot does not set the enable bits
+                 * for the IDE device. Force them on here.
+                 */
+                pci_read_config_byte(dev, 0x40, &c);
+                c |= 0x03; /* IDE: Chip Enable Bits */
+                pci_write_config_byte(dev, 0x40, c);
+
+                /*
+                 * Since only primary interface works, force the
+                 * IDE function to standard primary IDE interrupt
+                 * w/ 8259 offset
+                 */
+                dev->irq = 14;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+        }
+
+        /*
+         * Force legacy USB interrupt routing
+         */
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
+                dev->irq = 10;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
+        }
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, dev))) {
+                dev->irq = 11;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+        }
+}
 #endif /* CONFIG_PCI */
 
 TODC_ALLOC();
@@ -308,6 +439,9 @@ mpc85xx_cds_setup_arch(void)
 
         printk("mpc85xx_cds_setup_arch\n");
 
+        /* VIA IDE configuration */
+        ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
+
 #ifdef CONFIG_CPM2
         cpm2_reset();
 #endif
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
index 7627d77504bd..12b292c6ae32 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -77,4 +77,7 @@
 
 #define MPC85XX_PCI2_IO_SIZE         0x01000000
 
+#define NR_8259_INTS                 16
+#define CPM_IRQ_OFFSET               NR_8259_INTS
+
 #endif /* __MACH_MPC85XX_CDS_H__ */