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-rw-r--r--arch/ppc/platforms/4xx/Kconfig285
-rw-r--r--arch/ppc/platforms/4xx/Makefile31
-rw-r--r--arch/ppc/platforms/4xx/bamboo.c442
-rw-r--r--arch/ppc/platforms/4xx/bamboo.h133
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c265
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h54
-rw-r--r--arch/ppc/platforms/4xx/cpci405.c201
-rw-r--r--arch/ppc/platforms/4xx/cpci405.h28
-rw-r--r--arch/ppc/platforms/4xx/ebony.c334
-rw-r--r--arch/ppc/platforms/4xx/ebony.h97
-rw-r--r--arch/ppc/platforms/4xx/ep405.c196
-rw-r--r--arch/ppc/platforms/4xx/ep405.h52
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.c141
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.h145
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.c120
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.c115
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c220
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.h73
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.c163
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.h63
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c231
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.h71
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c129
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.h61
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.c170
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.h154
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.c122
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h235
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.c66
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.h258
-rw-r--r--arch/ppc/platforms/4xx/luan.c371
-rw-r--r--arch/ppc/platforms/4xx/luan.h77
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c350
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h94
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.c146
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.h63
-rw-r--r--arch/ppc/platforms/4xx/redwood5.c120
-rw-r--r--arch/ppc/platforms/4xx/redwood5.h52
-rw-r--r--arch/ppc/platforms/4xx/redwood6.c156
-rw-r--r--arch/ppc/platforms/4xx/redwood6.h53
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c272
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h49
-rw-r--r--arch/ppc/platforms/4xx/taishan.c395
-rw-r--r--arch/ppc/platforms/4xx/taishan.h67
-rw-r--r--arch/ppc/platforms/4xx/virtex.h35
-rw-r--r--arch/ppc/platforms/4xx/walnut.c246
-rw-r--r--arch/ppc/platforms/4xx/walnut.h52
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.c118
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml403.c120
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters.h104
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h310
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h243
-rw-r--r--arch/ppc/platforms/4xx/yucca.c393
-rw-r--r--arch/ppc/platforms/4xx/yucca.h108
56 files changed, 0 insertions, 8945 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
deleted file mode 100644
index 76551b679030..000000000000
--- a/arch/ppc/platforms/4xx/Kconfig
+++ /dev/null
@@ -1,285 +0,0 @@
1config 4xx
2 bool
3 depends on 40x || 44x
4 default y
5
6config WANT_EARLY_SERIAL
7 bool
8 select SERIAL_8250
9 default n
10
11menu "IBM 4xx options"
12 depends on 4xx
13
14choice
15 prompt "Machine Type"
16 depends on 40x
17 default WALNUT
18
19config BUBINGA
20 bool "Bubinga"
21 select WANT_EARLY_SERIAL
22 help
23 This option enables support for the IBM 405EP evaluation board.
24
25config CPCI405
26 bool "CPCI405"
27 help
28 This option enables support for the CPCI405 board.
29
30config EP405
31 bool "EP405/EP405PC"
32 select EMBEDDEDBOOT
33 help
34 This option enables support for the EP405/EP405PC boards.
35
36config REDWOOD_5
37 bool "Redwood-5"
38 help
39 This option enables support for the IBM STB04 evaluation board.
40
41config REDWOOD_6
42 bool "Redwood-6"
43 help
44 This option enables support for the IBM STBx25xx evaluation board.
45
46config SYCAMORE
47 bool "Sycamore"
48 help
49 This option enables support for the IBM PPC405GPr evaluation board.
50
51config WALNUT
52 bool "Walnut"
53 help
54 This option enables support for the IBM PPC405GP evaluation board.
55
56config XILINX_ML300
57 bool "Xilinx-ML300"
58 select XILINX_VIRTEX_II_PRO
59 select EMBEDDEDBOOT
60 help
61 This option enables support for the Xilinx ML300 evaluation board.
62
63config XILINX_ML403
64 bool "Xilinx-ML403"
65 select XILINX_VIRTEX_4_FX
66 select EMBEDDEDBOOT
67 help
68 This option enables support for the Xilinx ML403 evaluation board.
69endchoice
70
71choice
72 prompt "Machine Type"
73 depends on 44x
74 default EBONY
75
76config BAMBOO
77 bool "Bamboo"
78 select WANT_EARLY_SERIAL
79 help
80 This option enables support for the IBM PPC440EP evaluation board.
81
82config EBONY
83 bool "Ebony"
84 select WANT_EARLY_SERIAL
85 help
86 This option enables support for the IBM PPC440GP evaluation board.
87
88config LUAN
89 bool "Luan"
90 select WANT_EARLY_SERIAL
91 help
92 This option enables support for the IBM PPC440SP evaluation board.
93
94config YUCCA
95 bool "Yucca"
96 select WANT_EARLY_SERIAL
97 help
98 This option enables support for the AMCC PPC440SPe evaluation board.
99
100config OCOTEA
101 bool "Ocotea"
102 select WANT_EARLY_SERIAL
103 help
104 This option enables support for the IBM PPC440GX evaluation board.
105
106config TAISHAN
107 bool "Taishan"
108 select WANT_EARLY_SERIAL
109 help
110 This option enables support for the AMCC PPC440GX evaluation board.
111
112endchoice
113
114config EP405PC
115 bool "EP405PC Support"
116 depends on EP405
117
118
119# It's often necessary to know the specific 4xx processor type.
120# Fortunately, it is impled (so far) from the board type, so we
121# don't need to ask more redundant questions.
122config NP405H
123 bool
124 depends on ASH
125 default y
126
127config 440EP
128 bool
129 depends on BAMBOO
130 select PPC_FPU
131 default y
132
133config 440GP
134 bool
135 depends on EBONY
136 default y
137
138config 440GX
139 bool
140 depends on OCOTEA || TAISHAN
141 default y
142
143config 440SP
144 bool
145 depends on LUAN
146 default y
147
148config 440SPE
149 bool
150 depends on YUCCA
151 default y
152
153config 440
154 bool
155 depends on 440GP || 440SP || 440SPE || 440EP
156 default y
157
158config 440A
159 bool
160 depends on 440GX
161 default y
162
163config IBM440EP_ERR42
164 bool
165 depends on 440EP
166 default y
167
168# All 405-based cores up until the 405GPR and 405EP have this errata.
169config IBM405_ERR77
170 bool
171 depends on 40x && !403GCX && !405GPR && !405EP
172 default y
173
174# All 40x-based cores, up until the 405GPR and 405EP have this errata.
175config IBM405_ERR51
176 bool
177 depends on 40x && !405GPR && !405EP
178 default y
179
180config BOOKE
181 bool
182 depends on 44x
183 default y
184
185config IBM_OCP
186 bool
187 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
188 default y
189
190config IBM_EMAC4
191 bool
192 depends on 440GX || 440SP || 440SPE
193 default y
194
195config BIOS_FIXUP
196 bool
197 depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
198 default y
199
200# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
201config 403GCX
202 bool
203 depends on OAK
204 default y
205
206config 405EP
207 bool
208 depends on BUBINGA
209 default y
210
211config 405GP
212 bool
213 depends on CPCI405 || EP405 || WALNUT
214 default y
215
216config 405GPR
217 bool
218 depends on SYCAMORE
219 default y
220
221config XILINX_VIRTEX_II_PRO
222 bool
223 select XILINX_VIRTEX
224
225config XILINX_VIRTEX_4_FX
226 bool
227 select XILINX_VIRTEX
228
229config XILINX_VIRTEX
230 bool
231
232config STB03xxx
233 bool
234 depends on REDWOOD_5 || REDWOOD_6
235 default y
236
237config EMBEDDEDBOOT
238 bool
239
240config IBM_OPENBIOS
241 bool
242 depends on ASH || REDWOOD_5 || REDWOOD_6
243 default y
244
245config PPC4xx_DMA
246 bool "PPC4xx DMA controller support"
247 depends on 4xx
248
249config PPC4xx_EDMA
250 bool
251 depends on !STB03xxx && PPC4xx_DMA
252 default y
253
254config PPC_GEN550
255 bool
256 depends on 4xx
257 default y
258
259choice
260 prompt "TTYS0 device and default console"
261 depends on 40x
262 default UART0_TTYS0
263
264config UART0_TTYS0
265 bool "UART0"
266
267config UART0_TTYS1
268 bool "UART1"
269
270endchoice
271
272config SERIAL_SICC
273 bool "SICC Serial port support"
274 depends on STB03xxx
275
276config UART1_DFLT_CONSOLE
277 bool
278 depends on SERIAL_SICC && UART0_TTYS1
279 default y
280
281config SERIAL_SICC_CONSOLE
282 bool
283 depends on SERIAL_SICC && UART0_TTYS1
284 default y
285endmenu
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
deleted file mode 100644
index 723ad7985cc6..000000000000
--- a/arch/ppc/platforms/4xx/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
1#
2# Makefile for the PowerPC 4xx linux kernel.
3
4obj-$(CONFIG_BAMBOO) += bamboo.o
5obj-$(CONFIG_CPCI405) += cpci405.o
6obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o
8obj-$(CONFIG_BUBINGA) += bubinga.o
9obj-$(CONFIG_LUAN) += luan.o
10obj-$(CONFIG_YUCCA) += yucca.o
11obj-$(CONFIG_OCOTEA) += ocotea.o
12obj-$(CONFIG_REDWOOD_5) += redwood5.o
13obj-$(CONFIG_REDWOOD_6) += redwood6.o
14obj-$(CONFIG_SYCAMORE) += sycamore.o
15obj-$(CONFIG_TAISHAN) += taishan.o
16obj-$(CONFIG_WALNUT) += walnut.o
17obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
18obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
19
20obj-$(CONFIG_405GP) += ibm405gp.o
21obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
22obj-$(CONFIG_NP405H) += ibmnp405h.o
23obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
24obj-$(CONFIG_440EP) += ibm440ep.o
25obj-$(CONFIG_440GP) += ibm440gp.o
26obj-$(CONFIG_440GX) += ibm440gx.o
27obj-$(CONFIG_440SP) += ibm440sp.o
28obj-$(CONFIG_440SPE) += ppc440spe.o
29obj-$(CONFIG_405EP) += ibm405ep.o
30obj-$(CONFIG_405GPR) += ibm405gpr.o
31
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
deleted file mode 100644
index 01f20f4c14fe..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.c
+++ /dev/null
@@ -1,442 +0,0 @@
1/*
2 * Bamboo board specific routines
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 * Copyright 2004 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/stddef.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/reboot.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/types.h>
21#include <linux/major.h>
22#include <linux/blkdev.h>
23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/initrd.h>
26#include <linux/seq_file.h>
27#include <linux/root_dev.h>
28#include <linux/tty.h>
29#include <linux/serial.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32#include <linux/ethtool.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47
48#include <syslib/gen550.h>
49#include <syslib/ibm440gx_common.h>
50
51extern bd_t __res;
52
53static struct ibm44x_clocks clocks __initdata;
54
55/*
56 * Bamboo external IRQ triggering/polarity settings
57 */
58unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
65 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
69};
70
71static void __init
72bamboo_calibrate_decr(void)
73{
74 unsigned int freq;
75
76 if (mfspr(SPRN_CCR1) & CCR1_TCS)
77 freq = BAMBOO_TMRCLK;
78 else
79 freq = clocks.cpu;
80
81 ibm44x_calibrate_decr(freq);
82
83}
84
85static int
86bamboo_show_cpuinfo(struct seq_file *m)
87{
88 seq_printf(m, "vendor\t\t: IBM\n");
89 seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
90
91 return 0;
92}
93
94static inline int
95bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
96{
97 static char pci_irq_table[][4] =
98 /*
99 * PCI IDSEL/INTPIN->INTLINE
100 * A B C D
101 */
102 {
103 { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
104 { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
105 { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
106 { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
107 };
108
109 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111}
112
113static void __init bamboo_set_emacdata(void)
114{
115 u8 * base_addr;
116 struct ocp_def *def;
117 struct ocp_func_emac_data *emacdata;
118 u8 val;
119 int mode;
120 u32 excluded = 0;
121
122 base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
123 val = readb(base_addr);
124 iounmap((void *) base_addr);
125 if (BAMBOO_SEL_MII(val))
126 mode = PHY_MODE_MII;
127 else if (BAMBOO_SEL_RMII(val))
128 mode = PHY_MODE_RMII;
129 else
130 mode = PHY_MODE_SMII;
131
132 /*
133 * SW2 on the Bamboo is used for ethernet configuration and is accessed
134 * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
135 * overwrite the supported features with the settings in SW2.
136 *
137 * This is used as a workaround for the improperly biased RJ-45 sockets
138 * on the Rev. 0 Bamboo. By default only 10baseT is functional.
139 * Removing inductors L17 and L18 from the board allows 100baseT, but
140 * disables 10baseT. The Rev. 1 has no such limitations.
141 */
142
143 base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
144 val = readb(base_addr);
145 iounmap((void *) base_addr);
146 if (!BAMBOO_AUTONEGOTIATE(val)) {
147 excluded |= SUPPORTED_Autoneg;
148 if (BAMBOO_FORCE_100Mbps(val)) {
149 excluded |= SUPPORTED_10baseT_Full;
150 excluded |= SUPPORTED_10baseT_Half;
151 if (BAMBOO_FULL_DUPLEX_EN(val))
152 excluded |= SUPPORTED_100baseT_Half;
153 else
154 excluded |= SUPPORTED_100baseT_Full;
155 } else {
156 excluded |= SUPPORTED_100baseT_Full;
157 excluded |= SUPPORTED_100baseT_Half;
158 if (BAMBOO_FULL_DUPLEX_EN(val))
159 excluded |= SUPPORTED_10baseT_Half;
160 else
161 excluded |= SUPPORTED_10baseT_Full;
162 }
163 }
164
165 /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
166
167 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
168 emacdata = def->additions;
169 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
170 emacdata->phy_mode = mode;
171 emacdata->phy_feat_exc = excluded;
172
173 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
174 emacdata = def->additions;
175 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
176 emacdata->phy_mode = mode;
177 emacdata->phy_feat_exc = excluded;
178}
179
180static int
181bamboo_exclude_device(unsigned char bus, unsigned char devfn)
182{
183 return (bus == 0 && devfn == 0);
184}
185
186#define PCI_READW(offset) \
187 (readw((void *)((u32)pci_reg_base+offset)))
188
189#define PCI_WRITEW(value, offset) \
190 (writew(value, (void *)((u32)pci_reg_base+offset)))
191
192#define PCI_WRITEL(value, offset) \
193 (writel(value, (void *)((u32)pci_reg_base+offset)))
194
195static void __init
196bamboo_setup_pci(void)
197{
198 void *pci_reg_base;
199 unsigned long memory_size;
200 memory_size = ppc_md.find_end_of_memory();
201
202 pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
203
204 /* Enable PCI I/O, Mem, and Busmaster cycles */
205 PCI_WRITEW(PCI_READW(PCI_COMMAND) |
206 PCI_COMMAND_MEMORY |
207 PCI_COMMAND_MASTER, PCI_COMMAND);
208
209 /* Disable region first */
210 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
211
212 /* PLB starting addr: 0x00000000A0000000 */
213 PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
214
215 /* PCI start addr, 0xA0000000 (PCI Address) */
216 PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
217 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
218
219 /* Enable no pre-fetch, enable region */
220 PCI_WRITEL(((0xffffffff -
221 (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
222 BAMBOO_PCIL0_PMM0MA);
223
224 /* Disable region one */
225 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
226 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
227 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
228 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
229 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
230
231 /* Disable region two */
232 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
233 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
234 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
235 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
236 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
237
238 /* Now configure the PCI->PLB windows, we only use PTM1
239 *
240 * For Inbound flow, set the window size to all available memory
241 * This is required because if size is smaller,
242 * then Eth/PCI DD would fail as PCI card not able to access
243 * the memory allocated by DD.
244 */
245
246 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
247 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
248
249 memory_size = 1 << fls(memory_size - 1);
250
251 /* Size low + Enabled */
252 PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
253
254 eieio();
255 iounmap(pci_reg_base);
256}
257
258static void __init
259bamboo_setup_hose(void)
260{
261 unsigned int bar_response, bar;
262 struct pci_controller *hose;
263
264 bamboo_setup_pci();
265
266 hose = pcibios_alloc_controller();
267
268 if (!hose)
269 return;
270
271 hose->first_busno = 0;
272 hose->last_busno = 0xff;
273
274 hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
275
276 pci_init_resource(&hose->io_resource,
277 BAMBOO_PCI_LOWER_IO,
278 BAMBOO_PCI_UPPER_IO,
279 IORESOURCE_IO,
280 "PCI host bridge");
281
282 pci_init_resource(&hose->mem_resources[0],
283 BAMBOO_PCI_LOWER_MEM,
284 BAMBOO_PCI_UPPER_MEM,
285 IORESOURCE_MEM,
286 "PCI host bridge");
287
288 ppc_md.pci_exclude_device = bamboo_exclude_device;
289
290 hose->io_space.start = BAMBOO_PCI_LOWER_IO;
291 hose->io_space.end = BAMBOO_PCI_UPPER_IO;
292 hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
293 hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
294 isa_io_base =
295 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
296 hose->io_base_virt = (void *)isa_io_base;
297
298 setup_indirect_pci(hose,
299 BAMBOO_PCI_CFGA_PLB32,
300 BAMBOO_PCI_CFGD_PLB32);
301 hose->set_cfg_type = 1;
302
303 /* Zero config bars */
304 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
305 early_write_config_dword(hose, hose->first_busno,
306 PCI_FUNC(hose->first_busno), bar,
307 0x00000000);
308 early_read_config_dword(hose, hose->first_busno,
309 PCI_FUNC(hose->first_busno), bar,
310 &bar_response);
311 }
312
313 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
314
315 ppc_md.pci_swizzle = common_swizzle;
316 ppc_md.pci_map_irq = bamboo_map_irq;
317}
318
319TODC_ALLOC();
320
321static void __init
322bamboo_early_serial_map(void)
323{
324 struct uart_port port;
325
326 /* Setup ioremapped serial port access */
327 memset(&port, 0, sizeof(port));
328 port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
329 port.irq = 0;
330 port.uartclk = clocks.uart0;
331 port.regshift = 0;
332 port.iotype = UPIO_MEM;
333 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
334 port.line = 0;
335
336 if (early_serial_setup(&port) != 0) {
337 printk("Early serial init of port 0 failed\n");
338 }
339
340#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
341 /* Configure debug serial access */
342 gen550_init(0, &port);
343#endif
344
345 port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
346 port.irq = 1;
347 port.uartclk = clocks.uart1;
348 port.line = 1;
349
350 if (early_serial_setup(&port) != 0) {
351 printk("Early serial init of port 1 failed\n");
352 }
353
354#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
355 /* Configure debug serial access */
356 gen550_init(1, &port);
357#endif
358
359 port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
360 port.irq = 3;
361 port.uartclk = clocks.uart2;
362 port.line = 2;
363
364 if (early_serial_setup(&port) != 0) {
365 printk("Early serial init of port 2 failed\n");
366 }
367
368#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
369 /* Configure debug serial access */
370 gen550_init(2, &port);
371#endif
372
373 port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
374 port.irq = 4;
375 port.uartclk = clocks.uart3;
376 port.line = 3;
377
378 if (early_serial_setup(&port) != 0) {
379 printk("Early serial init of port 3 failed\n");
380 }
381}
382
383static void __init
384bamboo_setup_arch(void)
385{
386
387 bamboo_set_emacdata();
388
389 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
390 ocp_sys_info.opb_bus_freq = clocks.opb;
391
392 /* Setup TODC access */
393 TODC_INIT(TODC_TYPE_DS1743,
394 0,
395 0,
396 ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
397 8);
398
399 /* init to some ~sane value until calibrate_delay() runs */
400 loops_per_jiffy = 50000000/HZ;
401
402 /* Setup PCI host bridge */
403 bamboo_setup_hose();
404
405#ifdef CONFIG_BLK_DEV_INITRD
406 if (initrd_start)
407 ROOT_DEV = Root_RAM0;
408 else
409#endif
410#ifdef CONFIG_ROOT_NFS
411 ROOT_DEV = Root_NFS;
412#else
413 ROOT_DEV = Root_HDA1;
414#endif
415
416 bamboo_early_serial_map();
417
418 /* Identify the system */
419 printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
420}
421
422void __init platform_init(unsigned long r3, unsigned long r4,
423 unsigned long r5, unsigned long r6, unsigned long r7)
424{
425 ibm44x_platform_init(r3, r4, r5, r6, r7);
426
427 ppc_md.setup_arch = bamboo_setup_arch;
428 ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
429 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
430
431 ppc_md.calibrate_decr = bamboo_calibrate_decr;
432 ppc_md.time_init = todc_time_init;
433 ppc_md.set_rtc_time = todc_set_rtc_time;
434 ppc_md.get_rtc_time = todc_get_rtc_time;
435
436 ppc_md.nvram_read_val = todc_direct_read_val;
437 ppc_md.nvram_write_val = todc_direct_write_val;
438#ifdef CONFIG_KGDB
439 ppc_md.early_serial_map = bamboo_early_serial_map;
440#endif
441}
442
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
deleted file mode 100644
index dcd3d09a0a71..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.h
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Bamboo board definitions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 *
6 * Copyright 2004 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_BAMBOO_H__
16#define __ASM_BAMBOO_H__
17
18#include <platforms/4xx/ibm440ep.h>
19
20/* F/W TLB mapping used in bootloader glue to reset EMAC */
21#define PPC44x_EMAC0_MR0 0x0EF600E00
22
23/* Location of MAC addresses in PIBS image */
24#define PIBS_FLASH_BASE 0xfff00000
25#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
26#define PIBS_MAC_SIZE 0x200
27#define PIBS_MAC_OFFSET 0x100
28
29/* Default clock rate */
30#define BAMBOO_TMRCLK 25000000
31
32/* RTC/NVRAM location */
33#define BAMBOO_RTC_ADDR 0x080000000ULL
34#define BAMBOO_RTC_SIZE 0x2000
35
36/* FPGA Registers */
37#define BAMBOO_FPGA_ADDR 0x080002000ULL
38
39#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
40#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
41#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
42#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
43
44#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
45#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
46#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
47#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
48
49#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
50#define BAMBOO_SEL_MII(x) (x & 0x80)
51#define BAMBOO_SEL_RMII(x) (x & 0x40)
52#define BAMBOO_SEL_SMII(x) (x & 0x20)
53
54/* Flash */
55#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
56#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
57#define BAMBOO_SMALL_FLASH_SIZE 0x100000
58#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
59#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
60#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
61#define BAMBOO_LARGE_FLASH_SIZE 0x400000
62#define BAMBOO_SRAM_LOW 0x087f00000ULL
63#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
64#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
65#define BAMBOO_SRAM_SIZE 0x100000
66#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
67#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
68
69/*
70 * Serial port defines
71 */
72#define RS_TABLE_SIZE 4
73
74#define UART0_IO_BASE 0xEF600300
75#define UART1_IO_BASE 0xEF600400
76#define UART2_IO_BASE 0xEF600500
77#define UART3_IO_BASE 0xEF600600
78
79#define BASE_BAUD 33177600/3/16
80#define UART0_INT 0
81#define UART1_INT 1
82#define UART2_INT 3
83#define UART3_INT 4
84
85#define STD_UART_OP(num) \
86 { 0, BASE_BAUD, 0, UART##num##_INT, \
87 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
88 iomem_base: (void*)UART##num##_IO_BASE, \
89 io_type: SERIAL_IO_MEM},
90
91#define SERIAL_PORT_DFNS \
92 STD_UART_OP(0) \
93 STD_UART_OP(1) \
94 STD_UART_OP(2) \
95 STD_UART_OP(3)
96
97/* PCI support */
98#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
99#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
100
101#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
102#define BAMBOO_PCI_IO_SIZE 0x00010000
103#define BAMBOO_PCI_MEM_OFFSET 0x00000000
104#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
105
106#define BAMBOO_PCI_LOWER_IO 0x00000000
107#define BAMBOO_PCI_UPPER_IO 0x0000ffff
108#define BAMBOO_PCI_LOWER_MEM 0xa0000000
109#define BAMBOO_PCI_UPPER_MEM 0xafffffff
110#define BAMBOO_PCI_MEM_BASE 0xa0000000
111
112#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
113#define BAMBOO_PCIL0_SIZE 0x40
114
115#define BAMBOO_PCIL0_PMM0LA 0x000
116#define BAMBOO_PCIL0_PMM0MA 0x004
117#define BAMBOO_PCIL0_PMM0PCILA 0x008
118#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
119#define BAMBOO_PCIL0_PMM1LA 0x010
120#define BAMBOO_PCIL0_PMM1MA 0x014
121#define BAMBOO_PCIL0_PMM1PCILA 0x018
122#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
123#define BAMBOO_PCIL0_PMM2LA 0x020
124#define BAMBOO_PCIL0_PMM2MA 0x024
125#define BAMBOO_PCIL0_PMM2PCILA 0x028
126#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
127#define BAMBOO_PCIL0_PTM1MS 0x030
128#define BAMBOO_PCIL0_PTM1LA 0x034
129#define BAMBOO_PCIL0_PTM2MS 0x038
130#define BAMBOO_PCIL0_PTM2LA 0x03C
131
132#endif /* __ASM_BAMBOO_H__ */
133#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
deleted file mode 100644
index cd696be55aca..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ /dev/null
@@ -1,265 +0,0 @@
1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga).
3 *
4 * Author: SAW (IBM), derived from walnut.c.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/threads.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/blkdev.h>
19#include <linux/pci.h>
20#include <linux/rtc.h>
21#include <linux/tty.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/serial_8250.h>
25
26#include <asm/system.h>
27#include <asm/pci-bridge.h>
28#include <asm/processor.h>
29#include <asm/machdep.h>
30#include <asm/page.h>
31#include <asm/time.h>
32#include <asm/io.h>
33#include <asm/todc.h>
34#include <asm/kgdb.h>
35#include <asm/ocp.h>
36#include <asm/ibm_ocp_pci.h>
37
38#include <platforms/4xx/ibm405ep.h>
39
40#undef DEBUG
41
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48extern bd_t __res;
49
50void *bubinga_rtc_base;
51
52/* Some IRQs unique to the board
53 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
54 */
55int __init
56ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57{
58 static char pci_irq_table[][4] =
59 /*
60 * PCI IDSEL/INTPIN->INTLINE
61 * A B C D
62 */
63 {
64 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
65 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
66 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
67 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
68 };
69
70 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
71 return PCI_IRQ_TABLE_LOOKUP;
72};
73
74/* The serial clock for the chip is an internal clock determined by
75 * different clock speeds/dividers.
76 * Calculate the proper input baud rate and setup the serial driver.
77 */
78static void __init
79bubinga_early_serial_map(void)
80{
81 u32 uart_div;
82 int uart_clock;
83 struct uart_port port;
84
85 /* Calculate the serial clock input frequency
86 *
87 * The base baud is the PLL OUTA (provided in the board info
88 * structure) divided by the external UART Divisor, divided
89 * by 16.
90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_procfreq / uart_div;
93
94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port));
96 port.membase = (void*)ACTING_UART0_IO_BASE;
97 port.irq = ACTING_UART0_INT;
98 port.uartclk = uart_clock;
99 port.regshift = 0;
100 port.iotype = UPIO_MEM;
101 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
102 port.line = 0;
103
104 if (early_serial_setup(&port) != 0) {
105 printk("Early serial init of port 0 failed\n");
106 }
107
108 port.membase = (void*)ACTING_UART1_IO_BASE;
109 port.irq = ACTING_UART1_INT;
110 port.line = 1;
111
112 if (early_serial_setup(&port) != 0) {
113 printk("Early serial init of port 1 failed\n");
114 }
115}
116
117void __init
118bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
119{
120#ifdef CONFIG_PCI
121
122 unsigned int bar_response, bar;
123 /*
124 * Expected PCI mapping:
125 *
126 * PLB addr PCI memory addr
127 * --------------------- ---------------------
128 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
129 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
130 *
131 * PLB addr PCI io addr
132 * --------------------- ---------------------
133 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
134 *
135 * The following code is simplified by assuming that the bootrom
136 * has been well behaved in following this mapping.
137 */
138
139#ifdef DEBUG
140 int i;
141
142 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
143 printk("PCI bridge regs before fixup \n");
144 for (i = 0; i <= 3; i++) {
145 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
146 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
147 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
148 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
149 }
150 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
151 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
152 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
153 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
154
155#endif
156
157 /* added for IBM boot rom version 1.15 bios bar changes -AK */
158
159 /* Disable region first */
160 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
161 /* PLB starting addr, PCI: 0x80000000 */
162 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
163 /* PCI start addr, 0x80000000 */
164 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
165 /* 512MB range of PLB to PCI */
166 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
167 /* Enable no pre-fetch, enable region */
168 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
169 (PPC405_PCI_UPPER_MEM -
170 PPC405_PCI_MEM_BASE)) | 0x01));
171
172 /* Disable region one */
173 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
174 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
175 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
176 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
177 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
178 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
179
180 /* Disable region two */
181 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
182 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
183 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
184 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
185 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
186 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
187 out_le32((void *) &(pcip->ptm2la), 0x00000000);
188
189 /* Zero config bars */
190 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
191 early_write_config_dword(hose, hose->first_busno,
192 PCI_FUNC(hose->first_busno), bar,
193 0x00000000);
194 early_read_config_dword(hose, hose->first_busno,
195 PCI_FUNC(hose->first_busno), bar,
196 &bar_response);
197 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
198 hose->first_busno, PCI_SLOT(hose->first_busno),
199 PCI_FUNC(hose->first_busno), bar, bar_response);
200 }
201 /* end workaround */
202
203#ifdef DEBUG
204 printk("PCI bridge regs after fixup \n");
205 for (i = 0; i <= 3; i++) {
206 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
207 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
208 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
209 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
210 }
211 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
212 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
213 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
214 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
215
216#endif
217#endif
218}
219
220void __init
221bubinga_setup_arch(void)
222{
223 ppc4xx_setup_arch();
224
225 ibm_ocp_set_emac(0, 1);
226
227 bubinga_early_serial_map();
228
229 /* RTC step for the evb405ep */
230 bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
231 TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
232 bubinga_rtc_base, 8);
233 /* Identify the system */
234 printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
235}
236
237void __init
238bubinga_map_io(void)
239{
240 ppc4xx_map_io();
241 io_block_mapping(BUBINGA_RTC_VADDR,
242 BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
243}
244
245void __init
246platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
247 unsigned long r6, unsigned long r7)
248{
249 ppc4xx_init(r3, r4, r5, r6, r7);
250
251 ppc_md.setup_arch = bubinga_setup_arch;
252 ppc_md.setup_io_mappings = bubinga_map_io;
253
254#ifdef CONFIG_GEN_RTC
255 ppc_md.time_init = todc_time_init;
256 ppc_md.set_rtc_time = todc_set_rtc_time;
257 ppc_md.get_rtc_time = todc_get_rtc_time;
258 ppc_md.nvram_read_val = todc_direct_read_val;
259 ppc_md.nvram_write_val = todc_direct_write_val;
260#endif
261#ifdef CONFIG_KGDB
262 ppc_md.early_serial_map = bubinga_early_serial_map;
263#endif
264}
265
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
deleted file mode 100644
index 5c408060eb35..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Bubinga board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * SAW (IBM)
9 * 2003 (c) MontaVista Softare Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __BUBINGA_H__
20#define __BUBINGA_H__
21
22#include <platforms/4xx/ibm405ep.h>
23#include <asm/ppcboot.h>
24
25/* Memory map for the Bubinga board.
26 * Generic 4xx plus RTC.
27 */
28
29#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
30#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
31#define BUBINGA_RTC_SIZE ((uint)8*1024)
32
33/* The UART clock is based off an internal clock -
34 * define BASE_BAUD based on the internal clock and divider(s).
35 * Since BASE_BAUD must be a constant, we will initialize it
36 * using clock/divider values which OpenBIOS initializes
37 * for typical configurations at various CPU speeds.
38 * The base baud is calculated as (FWDA / EXT UART DIV / 16)
39 */
40#define BASE_BAUD 0
41
42/* Flash */
43#define PPC40x_FPGA_BASE 0xF0300000
44#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
45#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
46#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
47#define PPC40x_FLASH_LOW 0xFFF00000
48#define PPC40x_FLASH_HIGH 0xFFF80000
49#define PPC40x_FLASH_SIZE 0x80000
50
51#define PPC4xx_MACHINE_NAME "IBM Bubinga"
52
53#endif /* __BUBINGA_H__ */
54#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
deleted file mode 100644
index 2e7e25dd84cb..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Board setup routines for the esd CPCI-405 cPCI Board.
3 *
4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <asm/system.h>
21#include <asm/pci-bridge.h>
22#include <asm/machdep.h>
23#include <asm/todc.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <asm/ocp.h>
28#include <asm/ibm_ocp_pci.h>
29#include <platforms/4xx/ibm405gp.h>
30
31#ifdef CONFIG_GEN_RTC
32void *cpci405_nvram;
33#endif
34
35extern bd_t __res;
36
37/*
38 * Some IRQs unique to CPCI-405.
39 */
40int __init
41ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
42{
43 static char pci_irq_table[][4] =
44 /*
45 * PCI IDSEL/INTPIN->INTLINE
46 * A B C D
47 */
48 {
49 {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
50 {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
51 {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
52 {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
53 {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
54 {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
55 {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
56 };
57 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
58 return PCI_IRQ_TABLE_LOOKUP;
59};
60
61/* The serial clock for the chip is an internal clock determined by
62 * different clock speeds/dividers.
63 * Calculate the proper input baud rate and setup the serial driver.
64 */
65static void __init
66cpci405_early_serial_map(void)
67{
68 u32 uart_div;
69 int uart_clock;
70 struct uart_port port;
71
72 /* Calculate the serial clock input frequency
73 *
74 * The uart clock is the cpu frequency (provided in the board info
75 * structure) divided by the external UART Divisor.
76 */
77 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
78 uart_clock = __res.bi_procfreq / uart_div;
79
80 /* Setup serial port access */
81 memset(&port, 0, sizeof(port));
82#if defined(CONFIG_UART0_TTYS0)
83 port.membase = (void*)UART0_IO_BASE;
84 port.irq = UART0_INT;
85#else
86 port.membase = (void*)UART1_IO_BASE;
87 port.irq = UART1_INT;
88#endif
89 port.uartclk = uart_clock;
90 port.regshift = 0;
91 port.iotype = UPIO_MEM;
92 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
93 port.line = 0;
94
95 if (early_serial_setup(&port) != 0) {
96 printk("Early serial init of port 0 failed\n");
97 }
98#if defined(CONFIG_UART0_TTYS0)
99 port.membase = (void*)UART1_IO_BASE;
100 port.irq = UART1_INT;
101#else
102 port.membase = (void*)UART0_IO_BASE;
103 port.irq = UART0_INT;
104#endif
105 port.line = 1;
106
107 if (early_serial_setup(&port) != 0) {
108 printk("Early serial init of port 1 failed\n");
109 }
110}
111
112void __init
113cpci405_setup_arch(void)
114{
115 ppc4xx_setup_arch();
116
117 ibm_ocp_set_emac(0, 0);
118
119 cpci405_early_serial_map();
120
121#ifdef CONFIG_GEN_RTC
122 TODC_INIT(TODC_TYPE_MK48T35,
123 cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
124#endif
125}
126
127void __init
128bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
129{
130#ifdef CONFIG_PCI
131 unsigned int bar_response, bar;
132
133 /* Disable region first */
134 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
135 /* PLB starting addr, PCI: 0x80000000 */
136 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
137 /* PCI start addr, 0x80000000 */
138 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
139 /* 512MB range of PLB to PCI */
140 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
141 /* Enable no pre-fetch, enable region */
142 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
143 (PPC405_PCI_UPPER_MEM -
144 PPC405_PCI_MEM_BASE)) | 0x01));
145
146 /* Disable region one */
147 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
148 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
149 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
150 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
151 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
152 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
153
154 /* Disable region two */
155 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
156 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
157 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
158 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
159 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
160 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
161 out_le32((void *) &(pcip->ptm2la), 0x00000000);
162
163 /* Zero config bars */
164 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
165 early_write_config_dword(hose, hose->first_busno,
166 PCI_FUNC(hose->first_busno), bar,
167 0x00000000);
168 early_read_config_dword(hose, hose->first_busno,
169 PCI_FUNC(hose->first_busno), bar,
170 &bar_response);
171 }
172#endif
173}
174
175void __init
176cpci405_map_io(void)
177{
178 ppc4xx_map_io();
179
180#ifdef CONFIG_GEN_RTC
181 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
182#endif
183}
184
185void __init
186platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
187 unsigned long r6, unsigned long r7)
188{
189 ppc4xx_init(r3, r4, r5, r6, r7);
190
191 ppc_md.setup_arch = cpci405_setup_arch;
192 ppc_md.setup_io_mappings = cpci405_map_io;
193
194#ifdef CONFIG_GEN_RTC
195 ppc_md.time_init = todc_time_init;
196 ppc_md.set_rtc_time = todc_set_rtc_time;
197 ppc_md.get_rtc_time = todc_get_rtc_time;
198 ppc_md.nvram_read_val = todc_direct_read_val;
199 ppc_md.nvram_write_val = todc_direct_write_val;
200#endif
201}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
deleted file mode 100644
index a6c0a138b0d7..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * CPCI-405 board specific definitions
3 *
4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
10 */
11
12#ifdef __KERNEL__
13#ifndef __CPCI405_H__
14#define __CPCI405_H__
15
16#include <platforms/4xx/ibm405gp.h>
17#include <asm/ppcboot.h>
18
19/* Map for the NVRAM space */
20#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
21#define CPCI405_NVRAM_SIZE ((uint)32*1024)
22
23#define BASE_BAUD 0
24
25#define PPC4xx_MACHINE_NAME "esd CPCI-405"
26
27#endif /* __CPCI405_H__ */
28#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
deleted file mode 100644
index 8027a36fc5bb..000000000000
--- a/arch/ppc/platforms/4xx/ebony.c
+++ /dev/null
@@ -1,334 +0,0 @@
1/*
2 * Ebony board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 * Copyright 2002-2005 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003-2005 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/types.h>
24#include <linux/major.h>
25#include <linux/blkdev.h>
26#include <linux/console.h>
27#include <linux/delay.h>
28#include <linux/initrd.h>
29#include <linux/seq_file.h>
30#include <linux/root_dev.h>
31#include <linux/tty.h>
32#include <linux/serial.h>
33#include <linux/serial_core.h>
34#include <linux/serial_8250.h>
35
36#include <asm/system.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/dma.h>
40#include <asm/io.h>
41#include <asm/machdep.h>
42#include <asm/ocp.h>
43#include <asm/pci-bridge.h>
44#include <asm/time.h>
45#include <asm/todc.h>
46#include <asm/bootinfo.h>
47#include <asm/ppc4xx_pic.h>
48#include <asm/ppcboot.h>
49#include <asm/tlbflush.h>
50
51#include <syslib/gen550.h>
52#include <syslib/ibm440gp_common.h>
53
54extern bd_t __res;
55
56static struct ibm44x_clocks clocks __initdata;
57
58/*
59 * Ebony external IRQ triggering/polarity settings
60 */
61unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
67 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
75};
76
77static void __init
78ebony_calibrate_decr(void)
79{
80 unsigned int freq;
81
82 /*
83 * Determine system clock speed
84 *
85 * If we are on Rev. B silicon, then use
86 * default external system clock. If we are
87 * on Rev. C silicon then errata forces us to
88 * use the internal clock.
89 */
90 if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
91 freq = EBONY_440GP_RB_SYSCLK;
92 else
93 freq = EBONY_440GP_RC_SYSCLK;
94
95 ibm44x_calibrate_decr(freq);
96}
97
98static int
99ebony_show_cpuinfo(struct seq_file *m)
100{
101 seq_printf(m, "vendor\t\t: IBM\n");
102 seq_printf(m, "machine\t\t: Ebony\n");
103
104 return 0;
105}
106
107static inline int
108ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
109{
110 static char pci_irq_table[][4] =
111 /*
112 * PCI IDSEL/INTPIN->INTLINE
113 * A B C D
114 */
115 {
116 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
117 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
118 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
119 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
120 };
121
122 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
123 return PCI_IRQ_TABLE_LOOKUP;
124}
125
126#define PCIX_WRITEL(value, offset) \
127 (writel(value, pcix_reg_base + offset))
128
129/*
130 * FIXME: This is only here to "make it work". This will move
131 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
132 * configuration library. -Matt
133 */
134static void __init
135ebony_setup_pcix(void)
136{
137 void __iomem *pcix_reg_base;
138
139 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
140
141 /* Disable all windows */
142 PCIX_WRITEL(0, PCIX0_POM0SA);
143 PCIX_WRITEL(0, PCIX0_POM1SA);
144 PCIX_WRITEL(0, PCIX0_POM2SA);
145 PCIX_WRITEL(0, PCIX0_PIM0SA);
146 PCIX_WRITEL(0, PCIX0_PIM1SA);
147 PCIX_WRITEL(0, PCIX0_PIM2SA);
148
149 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
150 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
151 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
152 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
153 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
154 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
155
156 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
157 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
158 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
159 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
160
161 eieio();
162}
163
164static void __init
165ebony_setup_hose(void)
166{
167 struct pci_controller *hose;
168
169 /* Configure windows on the PCI-X host bridge */
170 ebony_setup_pcix();
171
172 hose = pcibios_alloc_controller();
173
174 if (!hose)
175 return;
176
177 hose->first_busno = 0;
178 hose->last_busno = 0xff;
179
180 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
181
182 pci_init_resource(&hose->io_resource,
183 EBONY_PCI_LOWER_IO,
184 EBONY_PCI_UPPER_IO,
185 IORESOURCE_IO,
186 "PCI host bridge");
187
188 pci_init_resource(&hose->mem_resources[0],
189 EBONY_PCI_LOWER_MEM,
190 EBONY_PCI_UPPER_MEM,
191 IORESOURCE_MEM,
192 "PCI host bridge");
193
194 hose->io_space.start = EBONY_PCI_LOWER_IO;
195 hose->io_space.end = EBONY_PCI_UPPER_IO;
196 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
197 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
198 hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
199 isa_io_base = (unsigned long)hose->io_base_virt;
200
201 setup_indirect_pci(hose,
202 EBONY_PCI_CFGA_PLB32,
203 EBONY_PCI_CFGD_PLB32);
204 hose->set_cfg_type = 1;
205
206 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
207
208 ppc_md.pci_swizzle = common_swizzle;
209 ppc_md.pci_map_irq = ebony_map_irq;
210}
211
212TODC_ALLOC();
213
214static void __init
215ebony_early_serial_map(void)
216{
217 struct uart_port port;
218
219 /* Setup ioremapped serial port access */
220 memset(&port, 0, sizeof(port));
221 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
222 port.irq = 0;
223 port.uartclk = clocks.uart0;
224 port.regshift = 0;
225 port.iotype = UPIO_MEM;
226 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
227 port.line = 0;
228
229 if (early_serial_setup(&port) != 0) {
230 printk("Early serial init of port 0 failed\n");
231 }
232
233#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
234 /* Configure debug serial access */
235 gen550_init(0, &port);
236
237 /* Purge TLB entry added in head_44x.S for early serial access */
238 _tlbie(UART0_IO_BASE, 0);
239#endif
240
241 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
242 port.irq = 1;
243 port.uartclk = clocks.uart1;
244 port.line = 1;
245
246 if (early_serial_setup(&port) != 0) {
247 printk("Early serial init of port 1 failed\n");
248 }
249
250#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
251 /* Configure debug serial access */
252 gen550_init(1, &port);
253#endif
254}
255
256static void __init
257ebony_setup_arch(void)
258{
259 struct ocp_def *def;
260 struct ocp_func_emac_data *emacdata;
261
262 /* Set mac_addr for each EMAC */
263 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
264 emacdata = def->additions;
265 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
266 emacdata->phy_mode = PHY_MODE_RMII;
267 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
268
269 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
270 emacdata = def->additions;
271 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
272 emacdata->phy_mode = PHY_MODE_RMII;
273 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
274
275 /*
276 * Determine various clocks.
277 * To be completely correct we should get SysClk
278 * from FPGA, because it can be changed by on-board switches
279 * --ebs
280 */
281 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
282 ocp_sys_info.opb_bus_freq = clocks.opb;
283
284 /* Setup TODC access */
285 TODC_INIT(TODC_TYPE_DS1743,
286 0,
287 0,
288 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
289 8);
290
291 /* init to some ~sane value until calibrate_delay() runs */
292 loops_per_jiffy = 50000000/HZ;
293
294 /* Setup PCI host bridge */
295 ebony_setup_hose();
296
297#ifdef CONFIG_BLK_DEV_INITRD
298 if (initrd_start)
299 ROOT_DEV = Root_RAM0;
300 else
301#endif
302#ifdef CONFIG_ROOT_NFS
303 ROOT_DEV = Root_NFS;
304#else
305 ROOT_DEV = Root_HDA1;
306#endif
307
308 ebony_early_serial_map();
309
310 /* Identify the system */
311 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
312}
313
314void __init platform_init(unsigned long r3, unsigned long r4,
315 unsigned long r5, unsigned long r6, unsigned long r7)
316{
317 ibm44x_platform_init(r3, r4, r5, r6, r7);
318
319 ppc_md.setup_arch = ebony_setup_arch;
320 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
321 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
322
323 ppc_md.calibrate_decr = ebony_calibrate_decr;
324 ppc_md.time_init = todc_time_init;
325 ppc_md.set_rtc_time = todc_set_rtc_time;
326 ppc_md.get_rtc_time = todc_get_rtc_time;
327
328 ppc_md.nvram_read_val = todc_direct_read_val;
329 ppc_md.nvram_write_val = todc_direct_write_val;
330#ifdef CONFIG_KGDB
331 ppc_md.early_serial_map = ebony_early_serial_map;
332#endif
333}
334
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
deleted file mode 100644
index f40e33d39d76..000000000000
--- a/arch/ppc/platforms/4xx/ebony.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Ebony board definitions
3 *
4 * Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2002 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_EBONY_H__
16#define __ASM_EBONY_H__
17
18#include <platforms/4xx/ibm440gp.h>
19
20/* F/W TLB mapping used in bootloader glue to reset EMAC */
21#define PPC44x_EMAC0_MR0 0xE0000800
22
23/* Where to find the MAC info */
24#define OPENBIOS_MAC_BASE 0xfffffe0c
25#define OPENBIOS_MAC_OFFSET 0x0c
26
27/* Default clock rates for Rev. B and Rev. C silicon */
28#define EBONY_440GP_RB_SYSCLK 33000000
29#define EBONY_440GP_RC_SYSCLK 400000000
30
31/* RTC/NVRAM location */
32#define EBONY_RTC_ADDR 0x0000000148000000ULL
33#define EBONY_RTC_SIZE 0x2000
34
35/* Flash */
36#define EBONY_FPGA_ADDR 0x0000000148300000ULL
37#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20)
38#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02)
39#define EBONY_FLASH_SEL(x) (x & 0x01)
40#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL
41#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL
42#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL
43#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL
44#define EBONY_SMALL_FLASH_SIZE 0x80000
45#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL
46#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
47#define EBONY_LARGE_FLASH_SIZE 0x400000
48
49#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL
50#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL
51
52/*
53 * Serial port defines
54 */
55
56#if defined(__BOOTER__)
57/* OpenBIOS defined UART mappings, used by bootloader shim */
58#define UART0_IO_BASE 0xE0000200
59#define UART1_IO_BASE 0xE0000300
60#else
61/* head_44x.S created UART mapping, used before early_serial_setup.
62 * We cannot use default OpenBIOS UART mappings because they
63 * don't work for configurations with more than 512M RAM. --ebs
64 */
65#define UART0_IO_BASE 0xF0000200
66#define UART1_IO_BASE 0xF0000300
67#endif
68
69/* external Epson SG-615P */
70#define BASE_BAUD 691200
71
72#define STD_UART_OP(num) \
73 { 0, BASE_BAUD, 0, UART##num##_INT, \
74 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
75 iomem_base: (void*)UART##num##_IO_BASE, \
76 io_type: SERIAL_IO_MEM},
77
78#define SERIAL_PORT_DFNS \
79 STD_UART_OP(0) \
80 STD_UART_OP(1)
81
82/* PCI support */
83#define EBONY_PCI_LOWER_IO 0x00000000
84#define EBONY_PCI_UPPER_IO 0x0000ffff
85#define EBONY_PCI_LOWER_MEM 0x80002000
86#define EBONY_PCI_UPPER_MEM 0xffffefff
87
88#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000
89#define EBONY_PCI_CFGA_PLB32 0x0ec00000
90#define EBONY_PCI_CFGD_PLB32 0x0ec00004
91
92#define EBONY_PCI_IO_BASE 0x0000000208000000ULL
93#define EBONY_PCI_IO_SIZE 0x00010000
94#define EBONY_PCI_MEM_OFFSET 0x00000000
95
96#endif /* __ASM_EBONY_H__ */
97#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c
deleted file mode 100644
index 5aa295022804..000000000000
--- a/arch/ppc/platforms/4xx/ep405.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * Embedded Planet 405GP board
3 * http://www.embeddedplanet.com
4 *
5 * Author: Matthew Locke <mlocke@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <asm/system.h>
15#include <asm/pci-bridge.h>
16#include <asm/machdep.h>
17#include <asm/todc.h>
18#include <asm/ocp.h>
19#include <asm/ibm_ocp_pci.h>
20
21#undef DEBUG
22#ifdef DEBUG
23#define DBG(x...) printk(x)
24#else
25#define DBG(x...)
26#endif
27
28u8 *ep405_bcsr;
29u8 *ep405_nvram;
30
31static struct {
32 u8 cpld_xirq_select;
33 int pci_idsel;
34 int irq;
35} ep405_devtable[] = {
36#ifdef CONFIG_EP405PC
37 {0x07, 0x0E, 25}, /* EP405PC: USB */
38#endif
39};
40
41int __init
42ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
43{
44 int i;
45
46 /* AFAICT this is only called a few times during PCI setup, so
47 performance is not critical */
48 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
49 if (idsel == ep405_devtable[i].pci_idsel)
50 return ep405_devtable[i].irq;
51 }
52 return -1;
53};
54
55void __init
56ep405_setup_arch(void)
57{
58 ppc4xx_setup_arch();
59
60 ibm_ocp_set_emac(0, 0);
61
62 if (__res.bi_nvramsize == 512*1024) {
63 /* FIXME: we should properly handle NVRTCs of different sizes */
64 TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
65 }
66}
67
68void __init
69bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
70{
71#ifdef CONFIG_PCI
72 unsigned int bar_response, bar;
73 /*
74 * Expected PCI mapping:
75 *
76 * PLB addr PCI memory addr
77 * --------------------- ---------------------
78 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
79 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
80 *
81 * PLB addr PCI io addr
82 * --------------------- ---------------------
83 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
84 *
85 */
86
87 /* Disable region zero first */
88 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
89 /* PLB starting addr, PCI: 0x80000000 */
90 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
91 /* PCI start addr, 0x80000000 */
92 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
93 /* 512MB range of PLB to PCI */
94 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
95 /* Enable no pre-fetch, enable region */
96 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
97 (PPC405_PCI_UPPER_MEM -
98 PPC405_PCI_MEM_BASE)) | 0x01));
99
100 /* Disable region one */
101 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
102 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
103 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
104 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
105 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
106 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
107
108 /* Disable region two */
109 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
110 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
111 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
112 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
113 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
114 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
115
116 /* Configure PTM (PCI->PLB) region 1 */
117 out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
118 /* Disable PTM region 2 */
119 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
120
121 /* Zero config bars */
122 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
123 early_write_config_dword(hose, hose->first_busno,
124 PCI_FUNC(hose->first_busno), bar,
125 0x00000000);
126 early_read_config_dword(hose, hose->first_busno,
127 PCI_FUNC(hose->first_busno), bar,
128 &bar_response);
129 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
130 hose->first_busno, PCI_SLOT(hose->first_busno),
131 PCI_FUNC(hose->first_busno), bar, bar_response);
132 }
133 /* end workaround */
134#endif
135}
136
137void __init
138ep405_map_io(void)
139{
140 bd_t *bip = &__res;
141
142 ppc4xx_map_io();
143
144 ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
145
146 if (bip->bi_nvramsize > 0) {
147 ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
148 }
149}
150
151void __init
152ep405_init_IRQ(void)
153{
154 int i;
155
156 ppc4xx_init_IRQ();
157
158 /* Workaround for a bug in the firmware it incorrectly sets
159 the IRQ polarities for XIRQ0 and XIRQ1 */
160 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
161 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
162
163 /* Activate the XIRQs from the CPLD */
164 writeb(0xf0, ep405_bcsr+10);
165
166 /* Set up IRQ routing */
167 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
168 if ( (ep405_devtable[i].irq >= 25)
169 && (ep405_devtable[i].irq) <= 31) {
170 writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
171 writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
172 }
173 }
174}
175
176void __init
177platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
178 unsigned long r6, unsigned long r7)
179{
180 ppc4xx_init(r3, r4, r5, r6, r7);
181
182 ppc_md.setup_arch = ep405_setup_arch;
183 ppc_md.setup_io_mappings = ep405_map_io;
184 ppc_md.init_IRQ = ep405_init_IRQ;
185
186 ppc_md.nvram_read_val = todc_direct_read_val;
187 ppc_md.nvram_write_val = todc_direct_write_val;
188
189 if (__res.bi_nvramsize == 512*1024) {
190 ppc_md.time_init = todc_time_init;
191 ppc_md.set_rtc_time = todc_set_rtc_time;
192 ppc_md.get_rtc_time = todc_get_rtc_time;
193 } else {
194 printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
195 }
196}
diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h
deleted file mode 100644
index 9814fc431725..000000000000
--- a/arch/ppc/platforms/4xx/ep405.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Embedded Planet 405GP board
3 * http://www.embeddedplanet.com
4 *
5 * Author: Matthew Locke <mlocke@mvista.com>
6 *
7 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_EP405_H__
15#define __ASM_EP405_H__
16
17/* We have a 405GP core */
18#include <platforms/4xx/ibm405gp.h>
19
20#ifndef __ASSEMBLY__
21
22#include <linux/types.h>
23
24typedef struct board_info {
25 unsigned int bi_memsize; /* DRAM installed, in bytes */
26 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
29 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
30 unsigned int bi_nvramsize; /* Size of the NVRAM/RTC */
31} bd_t;
32
33/* Some 4xx parts use a different timebase frequency from the internal clock.
34*/
35#define bi_tbfreq bi_intfreq
36
37extern u8 *ep405_bcsr;
38extern u8 *ep405_nvram;
39
40/* Map for the BCSR and NVRAM space */
41#define EP405_BCSR_PADDR ((uint)0xf4000000)
42#define EP405_BCSR_SIZE ((uint)16)
43#define EP405_NVRAM_PADDR ((uint)0xf4200000)
44
45/* serial defines */
46#define BASE_BAUD 399193
47
48#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP"
49
50#endif /* !__ASSEMBLY__ */
51#endif /* __ASM_EP405_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
deleted file mode 100644
index fb3630a1608d..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Support for IBM PPC 405EP processors.
3 *
4 * Author: SAW (IBM), derived from ibmnp405l.c.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/threads.h>
16#include <linux/param.h>
17#include <linux/string.h>
18
19#include <asm/ibm4xx.h>
20#include <asm/ocp.h>
21#include <asm/ppc4xx_pic.h>
22
23#include <platforms/4xx/ibm405ep.h>
24
25static struct ocp_func_mal_data ibm405ep_mal0_def = {
26 .num_tx_chans = 4, /* Number of TX channels */
27 .num_rx_chans = 2, /* Number of RX channels */
28 .txeob_irq = 11, /* TX End Of Buffer IRQ */
29 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
30 .txde_irq = 13, /* TX Descriptor Error IRQ */
31 .rxde_irq = 14, /* RX Descriptor Error IRQ */
32 .serr_irq = 10, /* MAL System Error IRQ */
33 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
34};
35OCP_SYSFS_MAL_DATA()
36
37static struct ocp_func_emac_data ibm405ep_emac0_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = -1, /* ZMII device index */
41 .zmii_mux = 0, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 0, /* MAL rx channel number */
44 .mal_tx_chan = 0, /* MAL tx channel number */
45 .wol_irq = 9, /* WOL interrupt number */
46 .mdio_idx = 0, /* MDIO via EMAC0 */
47 .tah_idx = -1, /* No TAH */
48};
49
50static struct ocp_func_emac_data ibm405ep_emac1_def = {
51 .rgmii_idx = -1, /* No RGMII */
52 .rgmii_mux = -1, /* No RGMII */
53 .zmii_idx = -1, /* ZMII device index */
54 .zmii_mux = 0, /* ZMII input of this EMAC */
55 .mal_idx = 0, /* MAL device index */
56 .mal_rx_chan = 1, /* MAL rx channel number */
57 .mal_tx_chan = 2, /* MAL tx channel number */
58 .wol_irq = 9, /* WOL interrupt number */
59 .mdio_idx = 0, /* MDIO via EMAC0 */
60 .tah_idx = -1, /* No TAH */
61};
62OCP_SYSFS_EMAC_DATA()
63
64static struct ocp_func_iic_data ibm405ep_iic0_def = {
65 .fast_mode = 0, /* Use standad mode (100Khz) */
66};
67OCP_SYSFS_IIC_DATA()
68
69struct ocp_def core_ocp[] = {
70 { .vendor = OCP_VENDOR_IBM,
71 .function = OCP_FUNC_OPB,
72 .index = 0,
73 .paddr = 0xEF600000,
74 .irq = OCP_IRQ_NA,
75 .pm = OCP_CPM_NA,
76 },
77 { .vendor = OCP_VENDOR_IBM,
78 .function = OCP_FUNC_16550,
79 .index = 0,
80 .paddr = UART0_IO_BASE,
81 .irq = UART0_INT,
82 .pm = IBM_CPM_UART0
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_16550,
86 .index = 1,
87 .paddr = UART1_IO_BASE,
88 .irq = UART1_INT,
89 .pm = IBM_CPM_UART1
90 },
91 { .vendor = OCP_VENDOR_IBM,
92 .function = OCP_FUNC_IIC,
93 .paddr = 0xEF600500,
94 .irq = 2,
95 .pm = IBM_CPM_IIC0,
96 .additions = &ibm405ep_iic0_def,
97 .show = &ocp_show_iic_data
98 },
99 { .vendor = OCP_VENDOR_IBM,
100 .function = OCP_FUNC_GPIO,
101 .paddr = 0xEF600700,
102 .irq = OCP_IRQ_NA,
103 .pm = IBM_CPM_GPIO0
104 },
105 { .vendor = OCP_VENDOR_IBM,
106 .function = OCP_FUNC_MAL,
107 .paddr = OCP_PADDR_NA,
108 .irq = OCP_IRQ_NA,
109 .pm = OCP_CPM_NA,
110 .additions = &ibm405ep_mal0_def,
111 .show = &ocp_show_mal_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_EMAC,
115 .index = 0,
116 .paddr = EMAC0_BASE,
117 .irq = 15,
118 .pm = OCP_CPM_NA,
119 .additions = &ibm405ep_emac0_def,
120 .show = &ocp_show_emac_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_EMAC,
124 .index = 1,
125 .paddr = 0xEF600900,
126 .irq = 17,
127 .pm = OCP_CPM_NA,
128 .additions = &ibm405ep_emac1_def,
129 .show = &ocp_show_emac_data
130 },
131 { .vendor = OCP_VENDOR_INVALID
132 }
133};
134
135/* Polarity and triggering settings for internal interrupt sources */
136struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
137 { .polarity = 0xffff7f80,
138 .triggering = 0x00000000,
139 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
140 }
141};
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
deleted file mode 100644
index 3ef20a547080..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * IBM PPC 405EP processor defines.
3 *
4 * Author: SAW (IBM), derived from ibm405gp.h.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_IBM405EP_H__
15#define __ASM_IBM405EP_H__
16
17
18/* ibm405.h at bottom of this file */
19
20/* PCI
21 * PCI Bridge config reg definitions
22 * see 17-19 of manual
23 */
24
25#define PPC405_PCI_CONFIG_ADDR 0xeec00000
26#define PPC405_PCI_CONFIG_DATA 0xeec00004
27
28#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
29 /* setbat */
30#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
31#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
32#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
33
34#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
35#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
36#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
37#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
38
39#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
40
41#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
42#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
43#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
44#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
45#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
46#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
47#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
48#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
49#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
50#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
51#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
52#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
53
54/* serial port defines */
55#define RS_TABLE_SIZE 2
56
57#define UART0_INT 0
58#define UART1_INT 1
59
60#define PCIL0_BASE 0xEF400000
61#define UART0_IO_BASE 0xEF600300
62#define UART1_IO_BASE 0xEF600400
63#define EMAC0_BASE 0xEF600800
64
65#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
66
67#if defined(CONFIG_UART0_TTYS0)
68#define ACTING_UART0_IO_BASE UART0_IO_BASE
69#define ACTING_UART1_IO_BASE UART1_IO_BASE
70#define ACTING_UART0_INT UART0_INT
71#define ACTING_UART1_INT UART1_INT
72#else
73#define ACTING_UART0_IO_BASE UART1_IO_BASE
74#define ACTING_UART1_IO_BASE UART0_IO_BASE
75#define ACTING_UART0_INT UART1_INT
76#define ACTING_UART1_INT UART0_INT
77#endif
78
79#define STD_UART_OP(num) \
80 { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \
81 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
82 iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \
83 io_type: SERIAL_IO_MEM},
84
85#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE
86#define SERIAL_PORT_DFNS \
87 STD_UART_OP(0) \
88 STD_UART_OP(1)
89
90/* DCR defines */
91#define DCRN_CPMSR_BASE 0x0BA
92#define DCRN_CPMFR_BASE 0x0B9
93
94#define DCRN_CPC0_PLLMR0_BASE 0x0F0
95#define DCRN_CPC0_BOOT_BASE 0x0F1
96#define DCRN_CPC0_CR1_BASE 0x0F2
97#define DCRN_CPC0_EPRCSR_BASE 0x0F3
98#define DCRN_CPC0_PLLMR1_BASE 0x0F4
99#define DCRN_CPC0_UCR_BASE 0x0F5
100#define DCRN_CPC0_UCR_U0DIV 0x07F
101#define DCRN_CPC0_SRR_BASE 0x0F6
102#define DCRN_CPC0_JTAGID_BASE 0x0F7
103#define DCRN_CPC0_SPARE_BASE 0x0F8
104#define DCRN_CPC0_PCI_BASE 0x0F9
105
106
107#define IBM_CPM_GPT 0x80000000 /* GPT interface */
108#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
109#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
110#define IBM_CPM_CPU 0x00008000 /* processor core */
111#define IBM_CPM_EBC 0x00002000 /* EBC controller */
112#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
113#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
114#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
115#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
116#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
117#define IBM_CPM_DMA 0x00000040 /* DMA controller */
118#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
119#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
120#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
121#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
122 | IBM_CPM_OPB | IBM_CPM_EBC \
123 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
124 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
125#define DCRN_DMA0_BASE 0x100
126#define DCRN_DMA1_BASE 0x108
127#define DCRN_DMA2_BASE 0x110
128#define DCRN_DMA3_BASE 0x118
129#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
130#define DCRN_DMASR_BASE 0x120
131#define DCRN_EBC_BASE 0x012
132#define DCRN_DCP0_BASE 0x014
133#define DCRN_MAL_BASE 0x180
134#define DCRN_OCM0_BASE 0x018
135#define DCRN_PLB0_BASE 0x084
136#define DCRN_PLLMR_BASE 0x0B0
137#define DCRN_POB0_BASE 0x0A0
138#define DCRN_SDRAM0_BASE 0x010
139#define DCRN_UIC0_BASE 0x0C0
140#define UIC0 DCRN_UIC0_BASE
141
142#include <asm/ibm405.h>
143
144#endif /* __ASM_IBM405EP_H__ */
145#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
deleted file mode 100644
index 2ac67a2f0ba6..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 *
3 * Copyright 2000-2001 MontaVista Software Inc.
4 * Original author: Armin Kuster akuster@mvista.com
5 *
6 * Module name: ibm405gp.c
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <platforms/4xx/ibm405gp.h>
22#include <asm/ibm4xx.h>
23#include <asm/ocp.h>
24#include <asm/ppc4xx_pic.h>
25
26static struct ocp_func_emac_data ibm405gp_emac0_def = {
27 .rgmii_idx = -1, /* No RGMII */
28 .rgmii_mux = -1, /* No RGMII */
29 .zmii_idx = -1, /* ZMII device index */
30 .zmii_mux = 0, /* ZMII input of this EMAC */
31 .mal_idx = 0, /* MAL device index */
32 .mal_rx_chan = 0, /* MAL rx channel number */
33 .mal_tx_chan = 0, /* MAL tx channel number */
34 .wol_irq = 9, /* WOL interrupt number */
35 .mdio_idx = -1, /* No shared MDIO */
36 .tah_idx = -1, /* No TAH */
37};
38OCP_SYSFS_EMAC_DATA()
39
40static struct ocp_func_mal_data ibm405gp_mal0_def = {
41 .num_tx_chans = 1, /* Number of TX channels */
42 .num_rx_chans = 1, /* Number of RX channels */
43 .txeob_irq = 11, /* TX End Of Buffer IRQ */
44 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
45 .txde_irq = 13, /* TX Descriptor Error IRQ */
46 .rxde_irq = 14, /* RX Descriptor Error IRQ */
47 .serr_irq = 10, /* MAL System Error IRQ */
48 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
49};
50OCP_SYSFS_MAL_DATA()
51
52static struct ocp_func_iic_data ibm405gp_iic0_def = {
53 .fast_mode = 0, /* Use standad mode (100Khz) */
54};
55OCP_SYSFS_IIC_DATA()
56
57struct ocp_def core_ocp[] = {
58 { .vendor = OCP_VENDOR_IBM,
59 .function = OCP_FUNC_OPB,
60 .index = 0,
61 .paddr = 0xEF600000,
62 .irq = OCP_IRQ_NA,
63 .pm = OCP_CPM_NA,
64 },
65 { .vendor = OCP_VENDOR_IBM,
66 .function = OCP_FUNC_16550,
67 .index = 0,
68 .paddr = UART0_IO_BASE,
69 .irq = UART0_INT,
70 .pm = IBM_CPM_UART0
71 },
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_16550,
74 .index = 1,
75 .paddr = UART1_IO_BASE,
76 .irq = UART1_INT,
77 .pm = IBM_CPM_UART1
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_IIC,
81 .paddr = 0xEF600500,
82 .irq = 2,
83 .pm = IBM_CPM_IIC0,
84 .additions = &ibm405gp_iic0_def,
85 .show = &ocp_show_iic_data,
86 },
87 { .vendor = OCP_VENDOR_IBM,
88 .function = OCP_FUNC_GPIO,
89 .paddr = 0xEF600700,
90 .irq = OCP_IRQ_NA,
91 .pm = IBM_CPM_GPIO0
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_MAL,
95 .paddr = OCP_PADDR_NA,
96 .irq = OCP_IRQ_NA,
97 .pm = OCP_CPM_NA,
98 .additions = &ibm405gp_mal0_def,
99 .show = &ocp_show_mal_data,
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_EMAC,
103 .index = 0,
104 .paddr = EMAC0_BASE,
105 .irq = 15,
106 .pm = IBM_CPM_EMAC0,
107 .additions = &ibm405gp_emac0_def,
108 .show = &ocp_show_emac_data,
109 },
110 { .vendor = OCP_VENDOR_INVALID
111 }
112};
113
114/* Polarity and triggering settings for internal interrupt sources */
115struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
116 { .polarity = 0xffffff80,
117 .triggering = 0x10000000,
118 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
119 }
120};
diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h
deleted file mode 100644
index 9f15e5518719..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Author: Armin Kuster akuster@mvista.com
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBM405GP_H__
12#define __ASM_IBM405GP_H__
13
14
15/* ibm405.h at bottom of this file */
16
17/* PCI
18 * PCI Bridge config reg definitions
19 * see 17-19 of manual
20 */
21
22#define PPC405_PCI_CONFIG_ADDR 0xeec00000
23#define PPC405_PCI_CONFIG_DATA 0xeec00004
24
25#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
26 /* setbat */
27#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
28#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
29#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
30
31#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
32#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
33#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
34#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
35
36#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
37
38#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
39#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
40#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
41#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
42#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
43#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
44#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
45#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
46#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
47#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
48#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
49#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
50
51/* serial port defines */
52#define RS_TABLE_SIZE 2
53
54#define UART0_INT 0
55#define UART1_INT 1
56
57#define PCIL0_BASE 0xEF400000
58#define UART0_IO_BASE 0xEF600300
59#define UART1_IO_BASE 0xEF600400
60#define EMAC0_BASE 0xEF600800
61
62#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
63
64#define STD_UART_OP(num) \
65 { 0, BASE_BAUD, 0, UART##num##_INT, \
66 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
67 iomem_base: (u8 *)UART##num##_IO_BASE, \
68 io_type: SERIAL_IO_MEM},
69
70#if defined(CONFIG_UART0_TTYS0)
71#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(0) \
74 STD_UART_OP(1)
75#endif
76
77#if defined(CONFIG_UART0_TTYS1)
78#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
79#define SERIAL_PORT_DFNS \
80 STD_UART_OP(1) \
81 STD_UART_OP(0)
82#endif
83
84/* DCR defines */
85#define DCRN_CHCR_BASE 0x0B1
86#define DCRN_CHPSR_BASE 0x0B4
87#define DCRN_CPMSR_BASE 0x0B8
88#define DCRN_CPMFR_BASE 0x0BA
89
90#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
91#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
92#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
93#define CHR1_CETE 0x00800000 /* CPU external timer enable */
94
95#define DCRN_CHPSR_BASE 0x0B4
96#define PSR_PLL_FWD_MASK 0xC0000000
97#define PSR_PLL_FDBACK_MASK 0x30000000
98#define PSR_PLL_TUNING_MASK 0x0E000000
99#define PSR_PLB_CPU_MASK 0x01800000
100#define PSR_OPB_PLB_MASK 0x00600000
101#define PSR_PCI_PLB_MASK 0x00180000
102#define PSR_EB_PLB_MASK 0x00060000
103#define PSR_ROM_WIDTH_MASK 0x00018000
104#define PSR_ROM_LOC 0x00004000
105#define PSR_PCI_ASYNC_EN 0x00001000
106#define PSR_PCI_ARBIT_EN 0x00000400
107
108#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
109#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
110#define IBM_CPM_CPU 0x20000000 /* processor core */
111#define IBM_CPM_DMA 0x10000000 /* DMA controller */
112#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
113#define IBM_CPM_DCP 0x04000000 /* CodePack */
114#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
115#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
116#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
117#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
118#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
119#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
120#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
121#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
122#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
123#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
124 | IBM_CPM_OPB | IBM_CPM_EBC \
125 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
126 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
127
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405GP_H__ */
148#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
deleted file mode 100644
index 9f4dacffdbb3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/smp.h>
12#include <linux/threads.h>
13#include <linux/param.h>
14#include <linux/string.h>
15#include <platforms/4xx/ibm405gpr.h>
16#include <asm/ibm4xx.h>
17#include <asm/ocp.h>
18#include <asm/ppc4xx_pic.h>
19
20static struct ocp_func_emac_data ibm405gpr_emac0_def = {
21 .rgmii_idx = -1, /* No RGMII */
22 .rgmii_mux = -1, /* No RGMII */
23 .zmii_idx = -1, /* ZMII device index */
24 .zmii_mux = 0, /* ZMII input of this EMAC */
25 .mal_idx = 0, /* MAL device index */
26 .mal_rx_chan = 0, /* MAL rx channel number */
27 .mal_tx_chan = 0, /* MAL tx channel number */
28 .wol_irq = 9, /* WOL interrupt number */
29 .mdio_idx = -1, /* No shared MDIO */
30 .tah_idx = -1, /* No TAH */
31};
32OCP_SYSFS_EMAC_DATA()
33
34static struct ocp_func_mal_data ibm405gpr_mal0_def = {
35 .num_tx_chans = 1, /* Number of TX channels */
36 .num_rx_chans = 1, /* Number of RX channels */
37 .txeob_irq = 11, /* TX End Of Buffer IRQ */
38 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
39 .txde_irq = 13, /* TX Descriptor Error IRQ */
40 .rxde_irq = 14, /* RX Descriptor Error IRQ */
41 .serr_irq = 10, /* MAL System Error IRQ */
42 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
43};
44OCP_SYSFS_MAL_DATA()
45
46static struct ocp_func_iic_data ibm405gpr_iic0_def = {
47 .fast_mode = 0, /* Use standad mode (100Khz) */
48};
49
50OCP_SYSFS_IIC_DATA()
51
52struct ocp_def core_ocp[] = {
53 { .vendor = OCP_VENDOR_IBM,
54 .function = OCP_FUNC_OPB,
55 .index = 0,
56 .paddr = 0xEF600000,
57 .irq = OCP_IRQ_NA,
58 .pm = OCP_CPM_NA,
59 },
60 { .vendor = OCP_VENDOR_IBM,
61 .function = OCP_FUNC_16550,
62 .index = 0,
63 .paddr = UART0_IO_BASE,
64 .irq = UART0_INT,
65 .pm = IBM_CPM_UART0
66 },
67 { .vendor = OCP_VENDOR_IBM,
68 .function = OCP_FUNC_16550,
69 .index = 1,
70 .paddr = UART1_IO_BASE,
71 .irq = UART1_INT,
72 .pm = IBM_CPM_UART1
73 },
74 { .vendor = OCP_VENDOR_IBM,
75 .function = OCP_FUNC_IIC,
76 .paddr = 0xEF600500,
77 .irq = 2,
78 .pm = IBM_CPM_IIC0,
79 .additions = &ibm405gpr_iic0_def,
80 .show = &ocp_show_iic_data,
81 },
82 { .vendor = OCP_VENDOR_IBM,
83 .function = OCP_FUNC_GPIO,
84 .paddr = 0xEF600700,
85 .irq = OCP_IRQ_NA,
86 .pm = IBM_CPM_GPIO0
87 },
88 { .vendor = OCP_VENDOR_IBM,
89 .function = OCP_FUNC_MAL,
90 .paddr = OCP_PADDR_NA,
91 .irq = OCP_IRQ_NA,
92 .pm = OCP_CPM_NA,
93 .additions = &ibm405gpr_mal0_def,
94 .show = &ocp_show_mal_data,
95 },
96 { .vendor = OCP_VENDOR_IBM,
97 .function = OCP_FUNC_EMAC,
98 .index = 0,
99 .paddr = EMAC0_BASE,
100 .irq = 15,
101 .pm = IBM_CPM_EMAC0,
102 .additions = &ibm405gpr_emac0_def,
103 .show = &ocp_show_emac_data,
104 },
105 { .vendor = OCP_VENDOR_INVALID
106 }
107};
108
109/* Polarity and triggering settings for internal interrupt sources */
110struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
111 { .polarity = 0xffffe000,
112 .triggering = 0x10000000,
113 .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
114 }
115};
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h
deleted file mode 100644
index 9e01f1515de3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBM405GPR_H__
12#define __ASM_IBM405GPR_H__
13
14
15/* ibm405.h at bottom of this file */
16
17/* PCI
18 * PCI Bridge config reg definitions
19 * see 17-19 of manual
20 */
21
22#define PPC405_PCI_CONFIG_ADDR 0xeec00000
23#define PPC405_PCI_CONFIG_DATA 0xeec00004
24
25#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
26 /* setbat */
27#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
28#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
29#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
30
31#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
32#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
33#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
34#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
35
36#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
37
38#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
39#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
40#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
41#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
42#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
43#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
44#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
45#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
46#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
47#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
48#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
49#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
50
51/* serial port defines */
52#define RS_TABLE_SIZE 2
53
54#define UART0_INT 0
55#define UART1_INT 1
56
57#define PCIL0_BASE 0xEF400000
58#define UART0_IO_BASE 0xEF600300
59#define UART1_IO_BASE 0xEF600400
60#define EMAC0_BASE 0xEF600800
61
62#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
63
64#define STD_UART_OP(num) \
65 { 0, BASE_BAUD, 0, UART##num##_INT, \
66 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
67 iomem_base: (u8 *)UART##num##_IO_BASE, \
68 io_type: SERIAL_IO_MEM},
69
70#if defined(CONFIG_UART0_TTYS0)
71#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(0) \
74 STD_UART_OP(1)
75#endif
76
77#if defined(CONFIG_UART0_TTYS1)
78#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
79#define SERIAL_PORT_DFNS \
80 STD_UART_OP(1) \
81 STD_UART_OP(0)
82#endif
83
84/* DCR defines */
85#define DCRN_CHCR_BASE 0x0B1
86#define DCRN_CHPSR_BASE 0x0B4
87#define DCRN_CPMSR_BASE 0x0B8
88#define DCRN_CPMFR_BASE 0x0BA
89
90#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
91#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
92#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
93#define CHR1_CETE 0x00800000 /* CPU external timer enable */
94
95#define DCRN_CHPSR_BASE 0x0B4
96#define PSR_PLL_FWD_MASK 0xC0000000
97#define PSR_PLL_FDBACK_MASK 0x30000000
98#define PSR_PLL_TUNING_MASK 0x0E000000
99#define PSR_PLB_CPU_MASK 0x01800000
100#define PSR_OPB_PLB_MASK 0x00600000
101#define PSR_PCI_PLB_MASK 0x00180000
102#define PSR_EB_PLB_MASK 0x00060000
103#define PSR_ROM_WIDTH_MASK 0x00018000
104#define PSR_ROM_LOC 0x00004000
105#define PSR_PCI_ASYNC_EN 0x00001000
106#define PSR_PCI_ARBIT_EN 0x00000400
107
108#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
109#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
110#define IBM_CPM_CPU 0x20000000 /* processor core */
111#define IBM_CPM_DMA 0x10000000 /* DMA controller */
112#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
113#define IBM_CPM_DCP 0x04000000 /* CodePack */
114#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
115#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
116#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
117#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
118#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
119#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
120#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
121#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
122#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
123#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
124 | IBM_CPM_OPB | IBM_CPM_EBC \
125 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
126 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
127
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405GPR_H__ */
148#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
deleted file mode 100644
index 0de91532aabb..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * PPC440EP I/O descriptions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 * Copyright 2004 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <platforms/4xx/ibm440ep.h>
17#include <asm/ocp.h>
18#include <asm/ppc4xx_pic.h>
19
20static struct ocp_func_emac_data ibm440ep_emac0_def = {
21 .rgmii_idx = -1, /* No RGMII */
22 .rgmii_mux = -1, /* No RGMII */
23 .zmii_idx = 0, /* ZMII device index */
24 .zmii_mux = 0, /* ZMII input of this EMAC */
25 .mal_idx = 0, /* MAL device index */
26 .mal_rx_chan = 0, /* MAL rx channel number */
27 .mal_tx_chan = 0, /* MAL tx channel number */
28 .wol_irq = 61, /* WOL interrupt number */
29 .mdio_idx = -1, /* No shared MDIO */
30 .tah_idx = -1, /* No TAH */
31};
32
33static struct ocp_func_emac_data ibm440ep_emac1_def = {
34 .rgmii_idx = -1, /* No RGMII */
35 .rgmii_mux = -1, /* No RGMII */
36 .zmii_idx = 0, /* ZMII device index */
37 .zmii_mux = 1, /* ZMII input of this EMAC */
38 .mal_idx = 0, /* MAL device index */
39 .mal_rx_chan = 1, /* MAL rx channel number */
40 .mal_tx_chan = 2, /* MAL tx channel number */
41 .wol_irq = 63, /* WOL interrupt number */
42 .mdio_idx = -1, /* No shared MDIO */
43 .tah_idx = -1, /* No TAH */
44};
45OCP_SYSFS_EMAC_DATA()
46
47static struct ocp_func_mal_data ibm440ep_mal0_def = {
48 .num_tx_chans = 4, /* Number of TX channels */
49 .num_rx_chans = 2, /* Number of RX channels */
50 .txeob_irq = 10, /* TX End Of Buffer IRQ */
51 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
52 .txde_irq = 33, /* TX Descriptor Error IRQ */
53 .rxde_irq = 34, /* RX Descriptor Error IRQ */
54 .serr_irq = 32, /* MAL System Error IRQ */
55 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
56};
57OCP_SYSFS_MAL_DATA()
58
59static struct ocp_func_iic_data ibm440ep_iic0_def = {
60 .fast_mode = 0, /* Use standad mode (100Khz) */
61};
62
63static struct ocp_func_iic_data ibm440ep_iic1_def = {
64 .fast_mode = 0, /* Use standad mode (100Khz) */
65};
66OCP_SYSFS_IIC_DATA()
67
68struct ocp_def core_ocp[] = {
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_OPB,
71 .index = 0,
72 .paddr = 0x0EF600000ULL,
73 .irq = OCP_IRQ_NA,
74 .pm = OCP_CPM_NA,
75 },
76 { .vendor = OCP_VENDOR_IBM,
77 .function = OCP_FUNC_16550,
78 .index = 0,
79 .paddr = PPC440EP_UART0_ADDR,
80 .irq = UART0_INT,
81 .pm = IBM_CPM_UART0,
82 },
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_16550,
85 .index = 1,
86 .paddr = PPC440EP_UART1_ADDR,
87 .irq = UART1_INT,
88 .pm = IBM_CPM_UART1,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 2,
93 .paddr = PPC440EP_UART2_ADDR,
94 .irq = UART2_INT,
95 .pm = IBM_CPM_UART2,
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 3,
100 .paddr = PPC440EP_UART3_ADDR,
101 .irq = UART3_INT,
102 .pm = IBM_CPM_UART3,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .index = 0,
107 .paddr = 0x0EF600700ULL,
108 .irq = 2,
109 .pm = IBM_CPM_IIC0,
110 .additions = &ibm440ep_iic0_def,
111 .show = &ocp_show_iic_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_IIC,
115 .index = 1,
116 .paddr = 0x0EF600800ULL,
117 .irq = 7,
118 .pm = IBM_CPM_IIC1,
119 .additions = &ibm440ep_iic1_def,
120 .show = &ocp_show_iic_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_GPIO,
124 .index = 0,
125 .paddr = 0x0EF600B00ULL,
126 .irq = OCP_IRQ_NA,
127 .pm = IBM_CPM_GPIO0,
128 },
129 { .vendor = OCP_VENDOR_IBM,
130 .function = OCP_FUNC_GPIO,
131 .index = 1,
132 .paddr = 0x0EF600C00ULL,
133 .irq = OCP_IRQ_NA,
134 .pm = OCP_CPM_NA,
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_MAL,
138 .paddr = OCP_PADDR_NA,
139 .irq = OCP_IRQ_NA,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440ep_mal0_def,
142 .show = &ocp_show_mal_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 0,
147 .paddr = 0x0EF600E00ULL,
148 .irq = 60,
149 .pm = OCP_CPM_NA,
150 .additions = &ibm440ep_emac0_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 1,
156 .paddr = 0x0EF600F00ULL,
157 .irq = 62,
158 .pm = OCP_CPM_NA,
159 .additions = &ibm440ep_emac1_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0x0EF600D00ULL,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
171
172/* Polarity and triggering settings for internal interrupt sources */
173struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
174 { .polarity = 0xffbffe03,
175 .triggering = 0x00000000,
176 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
177 },
178 { .polarity = 0xffffc6af,
179 .triggering = 0x06000140,
180 .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
181 },
182};
183
184static struct resource usb_gadget_resources[] = {
185 [0] = {
186 .start = 0x050000100ULL,
187 .end = 0x05000017FULL,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = 55,
192 .end = 55,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static u64 dma_mask = 0xffffffffULL;
198
199static struct platform_device usb_gadget_device = {
200 .name = "musbhsfc",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(usb_gadget_resources),
203 .resource = usb_gadget_resources,
204 .dev = {
205 .dma_mask = &dma_mask,
206 .coherent_dma_mask = 0xffffffffULL,
207 }
208};
209
210static struct platform_device *ibm440ep_devs[] __initdata = {
211 &usb_gadget_device,
212};
213
214static int __init
215ibm440ep_platform_add_devices(void)
216{
217 return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
218}
219arch_initcall(ibm440ep_platform_add_devices);
220
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
deleted file mode 100644
index d92572727d20..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * PPC440EP definitions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 *
6 * Copyright 2002 Roland Dreier
7 * Copyright 2004 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_IBM440EP_H
18#define __PPC_PLATFORMS_IBM440EP_H
19
20#include <asm/ibm44x.h>
21
22/* UART */
23#define PPC440EP_UART0_ADDR 0x0EF600300
24#define PPC440EP_UART1_ADDR 0x0EF600400
25#define PPC440EP_UART2_ADDR 0x0EF600500
26#define PPC440EP_UART3_ADDR 0x0EF600600
27#define UART0_INT 0
28#define UART1_INT 1
29#define UART2_INT 3
30#define UART3_INT 4
31
32/* Clock and Power Management */
33#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
34#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
35#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
36#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
37#define IBM_CPM_FPU 0x04000000 /* floating point unit */
38#define IBM_CPM_CPU 0x02000000 /* processor core */
39#define IBM_CPM_DMA 0x01000000 /* DMA controller */
40#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
41#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
42#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
43#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
44#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
45#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
46#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
47#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
48#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
49#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
50#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
51#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
52#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
53#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
54#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
55#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
56#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
57#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
58#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
59#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
60#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
61#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
62#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
63
64#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
65 | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
66 | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
67 | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
68 | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
69 | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
70
71
72#endif /* __PPC_PLATFORMS_IBM440EP_H */
73#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
deleted file mode 100644
index b67a72e5c6fe..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.c
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * PPC440GP I/O descriptions
3 *
4 * Matt Porter <mporter@mvista.com>
5 * Copyright 2002-2004 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440gp.h>
19#include <asm/ocp.h>
20#include <asm/ppc4xx_pic.h>
21
22static struct ocp_func_emac_data ibm440gp_emac0_def = {
23 .rgmii_idx = -1, /* No RGMII */
24 .rgmii_mux = -1, /* No RGMII */
25 .zmii_idx = 0, /* ZMII device index */
26 .zmii_mux = 0, /* ZMII input of this EMAC */
27 .mal_idx = 0, /* MAL device index */
28 .mal_rx_chan = 0, /* MAL rx channel number */
29 .mal_tx_chan = 0, /* MAL tx channel number */
30 .wol_irq = 61, /* WOL interrupt number */
31 .mdio_idx = -1, /* No shared MDIO */
32 .tah_idx = -1, /* No TAH */
33};
34
35static struct ocp_func_emac_data ibm440gp_emac1_def = {
36 .rgmii_idx = -1, /* No RGMII */
37 .rgmii_mux = -1, /* No RGMII */
38 .zmii_idx = 0, /* ZMII device index */
39 .zmii_mux = 1, /* ZMII input of this EMAC */
40 .mal_idx = 0, /* MAL device index */
41 .mal_rx_chan = 1, /* MAL rx channel number */
42 .mal_tx_chan = 2, /* MAL tx channel number */
43 .wol_irq = 63, /* WOL interrupt number */
44 .mdio_idx = -1, /* No shared MDIO */
45 .tah_idx = -1, /* No TAH */
46};
47OCP_SYSFS_EMAC_DATA()
48
49static struct ocp_func_mal_data ibm440gp_mal0_def = {
50 .num_tx_chans = 4, /* Number of TX channels */
51 .num_rx_chans = 2, /* Number of RX channels */
52 .txeob_irq = 10, /* TX End Of Buffer IRQ */
53 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
54 .txde_irq = 33, /* TX Descriptor Error IRQ */
55 .rxde_irq = 34, /* RX Descriptor Error IRQ */
56 .serr_irq = 32, /* MAL System Error IRQ */
57 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
58};
59OCP_SYSFS_MAL_DATA()
60
61static struct ocp_func_iic_data ibm440gp_iic0_def = {
62 .fast_mode = 0, /* Use standad mode (100Khz) */
63};
64
65static struct ocp_func_iic_data ibm440gp_iic1_def = {
66 .fast_mode = 0, /* Use standad mode (100Khz) */
67};
68OCP_SYSFS_IIC_DATA()
69
70struct ocp_def core_ocp[] = {
71 { .vendor = OCP_VENDOR_IBM,
72 .function = OCP_FUNC_OPB,
73 .index = 0,
74 .paddr = 0x0000000140000000ULL,
75 .irq = OCP_IRQ_NA,
76 .pm = OCP_CPM_NA,
77 },
78 { .vendor = OCP_VENDOR_IBM,
79 .function = OCP_FUNC_16550,
80 .index = 0,
81 .paddr = PPC440GP_UART0_ADDR,
82 .irq = UART0_INT,
83 .pm = IBM_CPM_UART0,
84 },
85 { .vendor = OCP_VENDOR_IBM,
86 .function = OCP_FUNC_16550,
87 .index = 1,
88 .paddr = PPC440GP_UART1_ADDR,
89 .irq = UART1_INT,
90 .pm = IBM_CPM_UART1,
91 },
92 { .vendor = OCP_VENDOR_IBM,
93 .function = OCP_FUNC_IIC,
94 .index = 0,
95 .paddr = 0x0000000140000400ULL,
96 .irq = 2,
97 .pm = IBM_CPM_IIC0,
98 .additions = &ibm440gp_iic0_def,
99 .show = &ocp_show_iic_data
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_IIC,
103 .index = 1,
104 .paddr = 0x0000000140000500ULL,
105 .irq = 3,
106 .pm = IBM_CPM_IIC1,
107 .additions = &ibm440gp_iic1_def,
108 .show = &ocp_show_iic_data
109 },
110 { .vendor = OCP_VENDOR_IBM,
111 .function = OCP_FUNC_GPIO,
112 .index = 0,
113 .paddr = 0x0000000140000700ULL,
114 .irq = OCP_IRQ_NA,
115 .pm = IBM_CPM_GPIO0,
116 },
117 { .vendor = OCP_VENDOR_IBM,
118 .function = OCP_FUNC_MAL,
119 .paddr = OCP_PADDR_NA,
120 .irq = OCP_IRQ_NA,
121 .pm = OCP_CPM_NA,
122 .additions = &ibm440gp_mal0_def,
123 .show = &ocp_show_mal_data,
124 },
125 { .vendor = OCP_VENDOR_IBM,
126 .function = OCP_FUNC_EMAC,
127 .index = 0,
128 .paddr = 0x0000000140000800ULL,
129 .irq = 60,
130 .pm = OCP_CPM_NA,
131 .additions = &ibm440gp_emac0_def,
132 .show = &ocp_show_emac_data,
133 },
134 { .vendor = OCP_VENDOR_IBM,
135 .function = OCP_FUNC_EMAC,
136 .index = 1,
137 .paddr = 0x0000000140000900ULL,
138 .irq = 62,
139 .pm = OCP_CPM_NA,
140 .additions = &ibm440gp_emac1_def,
141 .show = &ocp_show_emac_data,
142 },
143 { .vendor = OCP_VENDOR_IBM,
144 .function = OCP_FUNC_ZMII,
145 .paddr = 0x0000000140000780ULL,
146 .irq = OCP_IRQ_NA,
147 .pm = OCP_CPM_NA,
148 },
149 { .vendor = OCP_VENDOR_INVALID
150 }
151};
152
153/* Polarity and triggering settings for internal interrupt sources */
154struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
155 { .polarity = 0xfffffe03,
156 .triggering = 0x01c00000,
157 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
158 },
159 { .polarity = 0xffffc0ff,
160 .triggering = 0x00ff8000,
161 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
162 },
163};
diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h
deleted file mode 100644
index 391c90e1f5ea..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * PPC440GP definitions
3 *
4 * Roland Dreier <roland@digitalvampire.org>
5 *
6 * Copyright 2002 Roland Dreier
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This file contains code that was originally in the files ibm44x.h
14 * and ebony.h, which were written by Matt Porter of MontaVista Software Inc.
15 */
16
17#ifdef __KERNEL__
18#ifndef __PPC_PLATFORMS_IBM440GP_H
19#define __PPC_PLATFORMS_IBM440GP_H
20
21
22/* UART */
23#define PPC440GP_UART0_ADDR 0x0000000140000200ULL
24#define PPC440GP_UART1_ADDR 0x0000000140000300ULL
25#define UART0_INT 0
26#define UART1_INT 1
27
28/* Clock and Power Management */
29#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
30#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
31#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
32#define IBM_CPM_CPU 0x02000000 /* processor core */
33#define IBM_CPM_DMA 0x01000000 /* DMA controller */
34#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
35#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
36#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
37#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
38#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
39#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
40#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
41#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
42#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
43#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
44#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
45#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
46#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
47#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
48#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
49
50#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
51 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
52 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
53 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI)
54/*
55 * Serial port defines
56 */
57#define RS_TABLE_SIZE 2
58
59#include <asm/ibm44x.h>
60#include <syslib/ibm440gp_common.h>
61
62#endif /* __PPC_PLATFORMS_IBM440GP_H */
63#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
deleted file mode 100644
index 685abffcb6ce..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * PPC440GX I/O descriptions
3 *
4 * Matt Porter <mporter@mvista.com>
5 * Copyright 2002-2004 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440gx.h>
19#include <asm/ocp.h>
20#include <asm/ppc4xx_pic.h>
21
22static struct ocp_func_emac_data ibm440gx_emac0_def = {
23 .rgmii_idx = -1, /* No RGMII */
24 .rgmii_mux = -1, /* No RGMII */
25 .zmii_idx = 0, /* ZMII device index */
26 .zmii_mux = 0, /* ZMII input of this EMAC */
27 .mal_idx = 0, /* MAL device index */
28 .mal_rx_chan = 0, /* MAL rx channel number */
29 .mal_tx_chan = 0, /* MAL tx channel number */
30 .wol_irq = 61, /* WOL interrupt number */
31 .mdio_idx = -1, /* No shared MDIO */
32 .tah_idx = -1, /* No TAH */
33};
34
35static struct ocp_func_emac_data ibm440gx_emac1_def = {
36 .rgmii_idx = -1, /* No RGMII */
37 .rgmii_mux = -1, /* No RGMII */
38 .zmii_idx = 0, /* ZMII device index */
39 .zmii_mux = 1, /* ZMII input of this EMAC */
40 .mal_idx = 0, /* MAL device index */
41 .mal_rx_chan = 1, /* MAL rx channel number */
42 .mal_tx_chan = 1, /* MAL tx channel number */
43 .wol_irq = 63, /* WOL interrupt number */
44 .mdio_idx = -1, /* No shared MDIO */
45 .tah_idx = -1, /* No TAH */
46};
47
48static struct ocp_func_emac_data ibm440gx_emac2_def = {
49 .rgmii_idx = 0, /* RGMII device index */
50 .rgmii_mux = 0, /* RGMII input of this EMAC */
51 .zmii_idx = 0, /* ZMII device index */
52 .zmii_mux = 2, /* ZMII input of this EMAC */
53 .mal_idx = 0, /* MAL device index */
54 .mal_rx_chan = 2, /* MAL rx channel number */
55 .mal_tx_chan = 2, /* MAL tx channel number */
56 .wol_irq = 65, /* WOL interrupt number */
57 .mdio_idx = -1, /* No shared MDIO */
58 .tah_idx = 0, /* TAH device index */
59};
60
61static struct ocp_func_emac_data ibm440gx_emac3_def = {
62 .rgmii_idx = 0, /* RGMII device index */
63 .rgmii_mux = 1, /* RGMII input of this EMAC */
64 .zmii_idx = 0, /* ZMII device index */
65 .zmii_mux = 3, /* ZMII input of this EMAC */
66 .mal_idx = 0, /* MAL device index */
67 .mal_rx_chan = 3, /* MAL rx channel number */
68 .mal_tx_chan = 3, /* MAL tx channel number */
69 .wol_irq = 67, /* WOL interrupt number */
70 .mdio_idx = -1, /* No shared MDIO */
71 .tah_idx = 1, /* TAH device index */
72};
73OCP_SYSFS_EMAC_DATA()
74
75static struct ocp_func_mal_data ibm440gx_mal0_def = {
76 .num_tx_chans = 4, /* Number of TX channels */
77 .num_rx_chans = 4, /* Number of RX channels */
78 .txeob_irq = 10, /* TX End Of Buffer IRQ */
79 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
80 .txde_irq = 33, /* TX Descriptor Error IRQ */
81 .rxde_irq = 34, /* RX Descriptor Error IRQ */
82 .serr_irq = 32, /* MAL System Error IRQ */
83 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
84};
85OCP_SYSFS_MAL_DATA()
86
87static struct ocp_func_iic_data ibm440gx_iic0_def = {
88 .fast_mode = 0, /* Use standad mode (100Khz) */
89};
90
91static struct ocp_func_iic_data ibm440gx_iic1_def = {
92 .fast_mode = 0, /* Use standad mode (100Khz) */
93};
94OCP_SYSFS_IIC_DATA()
95
96struct ocp_def core_ocp[] = {
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_OPB,
99 .index = 0,
100 .paddr = 0x0000000140000000ULL,
101 .irq = OCP_IRQ_NA,
102 .pm = OCP_CPM_NA,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_16550,
106 .index = 0,
107 .paddr = PPC440GX_UART0_ADDR,
108 .irq = UART0_INT,
109 .pm = IBM_CPM_UART0,
110 },
111 { .vendor = OCP_VENDOR_IBM,
112 .function = OCP_FUNC_16550,
113 .index = 1,
114 .paddr = PPC440GX_UART1_ADDR,
115 .irq = UART1_INT,
116 .pm = IBM_CPM_UART1,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_IIC,
120 .index = 0,
121 .paddr = 0x0000000140000400ULL,
122 .irq = 2,
123 .pm = IBM_CPM_IIC0,
124 .additions = &ibm440gx_iic0_def,
125 .show = &ocp_show_iic_data
126 },
127 { .vendor = OCP_VENDOR_IBM,
128 .function = OCP_FUNC_IIC,
129 .index = 1,
130 .paddr = 0x0000000140000500ULL,
131 .irq = 3,
132 .pm = IBM_CPM_IIC1,
133 .additions = &ibm440gx_iic1_def,
134 .show = &ocp_show_iic_data
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_GPIO,
138 .index = 0,
139 .paddr = 0x0000000140000700ULL,
140 .irq = OCP_IRQ_NA,
141 .pm = IBM_CPM_GPIO0,
142 },
143 { .vendor = OCP_VENDOR_IBM,
144 .function = OCP_FUNC_MAL,
145 .paddr = OCP_PADDR_NA,
146 .irq = OCP_IRQ_NA,
147 .pm = OCP_CPM_NA,
148 .additions = &ibm440gx_mal0_def,
149 .show = &ocp_show_mal_data,
150 },
151 { .vendor = OCP_VENDOR_IBM,
152 .function = OCP_FUNC_EMAC,
153 .index = 0,
154 .paddr = 0x0000000140000800ULL,
155 .irq = 60,
156 .pm = OCP_CPM_NA,
157 .additions = &ibm440gx_emac0_def,
158 .show = &ocp_show_emac_data,
159 },
160 { .vendor = OCP_VENDOR_IBM,
161 .function = OCP_FUNC_EMAC,
162 .index = 1,
163 .paddr = 0x0000000140000900ULL,
164 .irq = 62,
165 .pm = OCP_CPM_NA,
166 .additions = &ibm440gx_emac1_def,
167 .show = &ocp_show_emac_data,
168 },
169 { .vendor = OCP_VENDOR_IBM,
170 .function = OCP_FUNC_EMAC,
171 .index = 2,
172 .paddr = 0x0000000140000C00ULL,
173 .irq = 64,
174 .pm = OCP_CPM_NA,
175 .additions = &ibm440gx_emac2_def,
176 .show = &ocp_show_emac_data,
177 },
178 { .vendor = OCP_VENDOR_IBM,
179 .function = OCP_FUNC_EMAC,
180 .index = 3,
181 .paddr = 0x0000000140000E00ULL,
182 .irq = 66,
183 .pm = OCP_CPM_NA,
184 .additions = &ibm440gx_emac3_def,
185 .show = &ocp_show_emac_data,
186 },
187 { .vendor = OCP_VENDOR_IBM,
188 .function = OCP_FUNC_RGMII,
189 .paddr = 0x0000000140000790ULL,
190 .irq = OCP_IRQ_NA,
191 .pm = OCP_CPM_NA,
192 },
193 { .vendor = OCP_VENDOR_IBM,
194 .function = OCP_FUNC_ZMII,
195 .paddr = 0x0000000140000780ULL,
196 .irq = OCP_IRQ_NA,
197 .pm = OCP_CPM_NA,
198 },
199 { .vendor = OCP_VENDOR_IBM,
200 .function = OCP_FUNC_TAH,
201 .index = 0,
202 .paddr = 0x0000000140000b50ULL,
203 .irq = 68,
204 .pm = OCP_CPM_NA,
205 },
206 { .vendor = OCP_VENDOR_IBM,
207 .function = OCP_FUNC_TAH,
208 .index = 1,
209 .paddr = 0x0000000140000d50ULL,
210 .irq = 69,
211 .pm = OCP_CPM_NA,
212 },
213 { .vendor = OCP_VENDOR_INVALID
214 }
215};
216
217/* Polarity and triggering settings for internal interrupt sources */
218struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
219 { .polarity = 0xfffffe03,
220 .triggering = 0x01c00000,
221 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
222 },
223 { .polarity = 0xffffc0ff,
224 .triggering = 0x00ff8000,
225 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
226 },
227 { .polarity = 0xffff83ff,
228 .triggering = 0x000f83c0,
229 .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
230 },
231};
diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h
deleted file mode 100644
index 599c4289b9c2..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * PPC440GX definitions
3 *
4 * Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2002 Roland Dreier
7 * Copyright 2003 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_IBM440GX_H
18#define __PPC_PLATFORMS_IBM440GX_H
19
20
21#include <asm/ibm44x.h>
22
23/* UART */
24#define PPC440GX_UART0_ADDR 0x0000000140000200ULL
25#define PPC440GX_UART1_ADDR 0x0000000140000300ULL
26#define UART0_INT 0
27#define UART1_INT 1
28
29/* Clock and Power Management */
30#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
31#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
32#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
33#define IBM_CPM_RGMII 0x10000000 /* RGMII */
34#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */
35#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */
36#define IBM_CPM_CPU 0x02000000 /* processor core */
37#define IBM_CPM_DMA 0x01000000 /* DMA controller */
38#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
39#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
40#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
41#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
42#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
43#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
44#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
45#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
46#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
47#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
48#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
49#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
50#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
51#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
52#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
53#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
54#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */
55#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */
56#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */
57
58#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
59 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
60 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
61 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
62 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
63 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
64 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
65/*
66 * Serial port defines
67 */
68#define RS_TABLE_SIZE 2
69
70#endif /* __PPC_PLATFORMS_IBM440GX_H */
71#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
deleted file mode 100644
index de8f7ac5623c..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * PPC440SP I/O descriptions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 * Copyright 2002-2005 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440sp.h>
19#include <asm/ocp.h>
20
21static struct ocp_func_emac_data ibm440sp_emac0_def = {
22 .rgmii_idx = -1, /* No RGMII */
23 .rgmii_mux = -1, /* No RGMII */
24 .zmii_idx = -1, /* No ZMII */
25 .zmii_mux = -1, /* No ZMII */
26 .mal_idx = 0, /* MAL device index */
27 .mal_rx_chan = 0, /* MAL rx channel number */
28 .mal_tx_chan = 0, /* MAL tx channel number */
29 .wol_irq = 61, /* WOL interrupt number */
30 .mdio_idx = -1, /* No shared MDIO */
31 .tah_idx = -1, /* No TAH */
32};
33OCP_SYSFS_EMAC_DATA()
34
35static struct ocp_func_mal_data ibm440sp_mal0_def = {
36 .num_tx_chans = 1, /* Number of TX channels */
37 .num_rx_chans = 1, /* Number of RX channels */
38 .txeob_irq = 38, /* TX End Of Buffer IRQ */
39 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
40 .txde_irq = 34, /* TX Descriptor Error IRQ */
41 .rxde_irq = 35, /* RX Descriptor Error IRQ */
42 .serr_irq = 33, /* MAL System Error IRQ */
43 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
44};
45OCP_SYSFS_MAL_DATA()
46
47static struct ocp_func_iic_data ibm440sp_iic0_def = {
48 .fast_mode = 0, /* Use standad mode (100Khz) */
49};
50
51static struct ocp_func_iic_data ibm440sp_iic1_def = {
52 .fast_mode = 0, /* Use standad mode (100Khz) */
53};
54OCP_SYSFS_IIC_DATA()
55
56struct ocp_def core_ocp[] = {
57 { .vendor = OCP_VENDOR_IBM,
58 .function = OCP_FUNC_OPB,
59 .index = 0,
60 .paddr = 0x0000000140000000ULL,
61 .irq = OCP_IRQ_NA,
62 .pm = OCP_CPM_NA,
63 },
64 { .vendor = OCP_VENDOR_IBM,
65 .function = OCP_FUNC_16550,
66 .index = 0,
67 .paddr = PPC440SP_UART0_ADDR,
68 .irq = UART0_INT,
69 .pm = IBM_CPM_UART0,
70 },
71 { .vendor = OCP_VENDOR_IBM,
72 .function = OCP_FUNC_16550,
73 .index = 1,
74 .paddr = PPC440SP_UART1_ADDR,
75 .irq = UART1_INT,
76 .pm = IBM_CPM_UART1,
77 },
78 { .vendor = OCP_VENDOR_IBM,
79 .function = OCP_FUNC_16550,
80 .index = 2,
81 .paddr = PPC440SP_UART2_ADDR,
82 .irq = UART2_INT,
83 .pm = IBM_CPM_UART2,
84 },
85 { .vendor = OCP_VENDOR_IBM,
86 .function = OCP_FUNC_IIC,
87 .index = 0,
88 .paddr = 0x00000001f0000400ULL,
89 .irq = 2,
90 .pm = IBM_CPM_IIC0,
91 .additions = &ibm440sp_iic0_def,
92 .show = &ocp_show_iic_data
93 },
94 { .vendor = OCP_VENDOR_IBM,
95 .function = OCP_FUNC_IIC,
96 .index = 1,
97 .paddr = 0x00000001f0000500ULL,
98 .irq = 3,
99 .pm = IBM_CPM_IIC1,
100 .additions = &ibm440sp_iic1_def,
101 .show = &ocp_show_iic_data
102 },
103 { .vendor = OCP_VENDOR_IBM,
104 .function = OCP_FUNC_GPIO,
105 .index = 0,
106 .paddr = 0x00000001f0000700ULL,
107 .irq = OCP_IRQ_NA,
108 .pm = IBM_CPM_GPIO0,
109 },
110 { .vendor = OCP_VENDOR_IBM,
111 .function = OCP_FUNC_MAL,
112 .paddr = OCP_PADDR_NA,
113 .irq = OCP_IRQ_NA,
114 .pm = OCP_CPM_NA,
115 .additions = &ibm440sp_mal0_def,
116 .show = &ocp_show_mal_data,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_EMAC,
120 .index = 0,
121 .paddr = 0x00000001f0000800ULL,
122 .irq = 60,
123 .pm = OCP_CPM_NA,
124 .additions = &ibm440sp_emac0_def,
125 .show = &ocp_show_emac_data,
126 },
127 { .vendor = OCP_VENDOR_INVALID
128 }
129};
diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
deleted file mode 100644
index 2978682f1720..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * PPC440SP definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __PPC_PLATFORMS_IBM440SP_H
16#define __PPC_PLATFORMS_IBM440SP_H
17
18
19#include <asm/ibm44x.h>
20
21/* UART */
22#define PPC440SP_UART0_ADDR 0x00000001f0000200ULL
23#define PPC440SP_UART1_ADDR 0x00000001f0000300ULL
24#define PPC440SP_UART2_ADDR 0x00000001f0000600ULL
25#define UART0_INT 0
26#define UART1_INT 1
27#define UART2_INT 2
28
29/* Clock and Power Management */
30#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
31#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
32#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
33#define IBM_CPM_CPU 0x02000000 /* processor core */
34#define IBM_CPM_DMA 0x01000000 /* DMA controller */
35#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
36#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
37#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
38#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
39#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
40#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
41#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
42#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
43#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
44#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
45#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
46#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
47#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
48#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
49#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
50#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
51#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
52
53#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
54 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
55 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
56 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
57 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
58 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
59 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
60#endif /* __PPC_PLATFORMS_IBM440SP_H */
61#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
deleted file mode 100644
index 1afc3642e5b1..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <asm/ocp.h>
12#include <platforms/4xx/ibmnp405h.h>
13
14static struct ocp_func_emac_data ibmnp405h_emac0_def = {
15 .rgmii_idx = -1, /* No RGMII */
16 .rgmii_mux = -1, /* No RGMII */
17 .zmii_idx = 0, /* ZMII device index */
18 .zmii_mux = 0, /* ZMII input of this EMAC */
19 .mal_idx = 0, /* MAL device index */
20 .mal_rx_chan = 0, /* MAL rx channel number */
21 .mal_tx_chan = 0, /* MAL tx channel number */
22 .wol_irq = 41, /* WOL interrupt number */
23 .mdio_idx = -1, /* No shared MDIO */
24 .tah_idx = -1, /* No TAH */
25};
26
27static struct ocp_func_emac_data ibmnp405h_emac1_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = 0, /* ZMII device index */
31 .zmii_mux = 1, /* ZMII input of this EMAC */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 1, /* MAL rx channel number */
34 .mal_tx_chan = 2, /* MAL tx channel number */
35 .wol_irq = 41, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39static struct ocp_func_emac_data ibmnp405h_emac2_def = {
40 .rgmii_idx = -1, /* No RGMII */
41 .rgmii_mux = -1, /* No RGMII */
42 .zmii_idx = 0, /* ZMII device index */
43 .zmii_mux = 2, /* ZMII input of this EMAC */
44 .mal_idx = 0, /* MAL device index */
45 .mal_rx_chan = 2, /* MAL rx channel number */
46 .mal_tx_chan = 4, /* MAL tx channel number */
47 .wol_irq = 41, /* WOL interrupt number */
48 .mdio_idx = -1, /* No shared MDIO */
49 .tah_idx = -1, /* No TAH */
50};
51static struct ocp_func_emac_data ibmnp405h_emac3_def = {
52 .rgmii_idx = -1, /* No RGMII */
53 .rgmii_mux = -1, /* No RGMII */
54 .zmii_idx = 0, /* ZMII device index */
55 .zmii_mux = 3, /* ZMII input of this EMAC */
56 .mal_idx = 0, /* MAL device index */
57 .mal_rx_chan = 3, /* MAL rx channel number */
58 .mal_tx_chan = 6, /* MAL tx channel number */
59 .wol_irq = 41, /* WOL interrupt number */
60 .mdio_idx = -1, /* No shared MDIO */
61 .tah_idx = -1, /* No TAH */
62};
63OCP_SYSFS_EMAC_DATA()
64
65static struct ocp_func_mal_data ibmnp405h_mal0_def = {
66 .num_tx_chans = 8, /* Number of TX channels */
67 .num_rx_chans = 4, /* Number of RX channels */
68 .txeob_irq = 17, /* TX End Of Buffer IRQ */
69 .rxeob_irq = 18, /* RX End Of Buffer IRQ */
70 .txde_irq = 46, /* TX Descriptor Error IRQ */
71 .rxde_irq = 47, /* RX Descriptor Error IRQ */
72 .serr_irq = 45, /* MAL System Error IRQ */
73 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
74};
75OCP_SYSFS_MAL_DATA()
76
77static struct ocp_func_iic_data ibmnp405h_iic0_def = {
78 .fast_mode = 0, /* Use standad mode (100Khz) */
79};
80OCP_SYSFS_IIC_DATA()
81
82struct ocp_def core_ocp[] = {
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_OPB,
85 .index = 0,
86 .paddr = 0xEF600000,
87 .irq = OCP_IRQ_NA,
88 .pm = OCP_CPM_NA,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 0,
93 .paddr = UART0_IO_BASE,
94 .irq = UART0_INT,
95 .pm = IBM_CPM_UART0
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 1,
100 .paddr = UART1_IO_BASE,
101 .irq = UART1_INT,
102 .pm = IBM_CPM_UART1
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .paddr = 0xEF600500,
107 .irq = 2,
108 .pm = IBM_CPM_IIC0,
109 .additions = &ibmnp405h_iic0_def,
110 .show = &ocp_show_iic_data
111 },
112 { .vendor = OCP_VENDOR_IBM,
113 .function = OCP_FUNC_GPIO,
114 .paddr = 0xEF600700,
115 .irq = OCP_IRQ_NA,
116 .pm = IBM_CPM_GPIO0
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_MAL,
120 .paddr = OCP_PADDR_NA,
121 .irq = OCP_IRQ_NA,
122 .pm = OCP_CPM_NA,
123 .additions = &ibmnp405h_mal0_def,
124 .show = &ocp_show_mal_data,
125 },
126 { .vendor = OCP_VENDOR_IBM,
127 .function = OCP_FUNC_EMAC,
128 .index = 0,
129 .paddr = EMAC0_BASE,
130 .irq = 37,
131 .pm = IBM_CPM_EMAC0,
132 .additions = &ibmnp405h_emac0_def,
133 .show = &ocp_show_emac_data,
134 },
135 { .vendor = OCP_VENDOR_IBM,
136 .function = OCP_FUNC_EMAC,
137 .index = 1,
138 .paddr = 0xEF600900,
139 .irq = 38,
140 .pm = IBM_CPM_EMAC1,
141 .additions = &ibmnp405h_emac1_def,
142 .show = &ocp_show_emac_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 2,
147 .paddr = 0xEF600a00,
148 .irq = 39,
149 .pm = IBM_CPM_EMAC2,
150 .additions = &ibmnp405h_emac2_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 3,
156 .paddr = 0xEF600b00,
157 .irq = 40,
158 .pm = IBM_CPM_EMAC3,
159 .additions = &ibmnp405h_emac3_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0xEF600C10,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
deleted file mode 100644
index 08a6a7791903..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.h
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMNP405H_H__
12#define __ASM_IBMNP405H_H__
13
14
15/* ibm405.h at bottom of this file */
16
17#define PPC405_PCI_CONFIG_ADDR 0xeec00000
18#define PPC405_PCI_CONFIG_DATA 0xeec00004
19#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
20 /* setbat */
21#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
22#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
23#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
24
25#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
26#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
27#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
28#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
29
30#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
31
32#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
33#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
34#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
35#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
36#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
37#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
38#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
39#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
40
41/* serial port defines */
42#define RS_TABLE_SIZE 4
43
44#define UART0_INT 0
45#define UART1_INT 1
46#define PCIL0_BASE 0xEF400000
47#define UART0_IO_BASE 0xEF600300
48#define UART1_IO_BASE 0xEF600400
49#define OPB0_BASE 0xEF600600
50#define EMAC0_BASE 0xEF600800
51
52#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
53
54#define STD_UART_OP(num) \
55 { 0, BASE_BAUD, 0, UART##num##_INT, \
56 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
57 iomem_base:(u8 *) UART##num##_IO_BASE, \
58 io_type: SERIAL_IO_MEM},
59
60#if defined(CONFIG_UART0_TTYS0)
61#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
62#define SERIAL_PORT_DFNS \
63 STD_UART_OP(0) \
64 STD_UART_OP(1)
65#endif
66
67#if defined(CONFIG_UART0_TTYS1)
68#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
69#define SERIAL_PORT_DFNS \
70 STD_UART_OP(1) \
71 STD_UART_OP(0)
72#endif
73
74/* DCR defines */
75/* ------------------------------------------------------------------------- */
76
77#define DCRN_CHCR_BASE 0x0F1
78#define DCRN_CHPSR_BASE 0x0B4
79#define DCRN_CPMSR_BASE 0x0BA
80#define DCRN_CPMFR_BASE 0x0B9
81#define DCRN_CPMER_BASE 0x0B8
82
83/* CPM Clocking & Power Management defines */
84#define IBM_CPM_PCI 0x40000000 /* PCI */
85#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
86#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
87#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
88#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
89#define IBM_CPM_EMMII 0 /* Shift value for MII */
90#define IBM_CPM_EMRX 1 /* Shift value for recv */
91#define IBM_CPM_EMTX 2 /* Shift value for MAC */
92#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
93#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
94#define IBM_CPM_CPU 0x00008000 /* processor core */
95#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
96#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
97#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
98#define IBM_CPM_HDLC 0x00000800 /* HDCL */
99#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
100#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
101#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
102#define IBM_CPM_DMA 0x00000040 /* DMA controller */
103#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
104#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
105#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
106/* this is the default setting for devices put to sleep when booting */
107
108#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
109 | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
110 | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
111 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
112 | IBM_CPM_EMAC3 | IBM_CPM_PCI)
113
114#define DCRN_DMA0_BASE 0x100
115#define DCRN_DMA1_BASE 0x108
116#define DCRN_DMA2_BASE 0x110
117#define DCRN_DMA3_BASE 0x118
118#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
119#define DCRN_DMASR_BASE 0x120
120#define DCRN_EBC_BASE 0x012
121#define DCRN_DCP0_BASE 0x014
122#define DCRN_MAL_BASE 0x180
123#define DCRN_OCM0_BASE 0x018
124#define DCRN_PLB0_BASE 0x084
125#define DCRN_PLLMR_BASE 0x0B0
126#define DCRN_POB0_BASE 0x0A0
127#define DCRN_SDRAM0_BASE 0x010
128#define DCRN_UIC0_BASE 0x0C0
129#define DCRN_UIC1_BASE 0x0D0
130#define DCRN_CPC0_EPRCSR 0x0F3
131
132#define UIC0_UIC1NC 0x00000002
133
134#define CHR1_CETE 0x00000004 /* CPU external timer enable */
135#define UIC0 DCRN_UIC0_BASE
136#define UIC1 DCRN_UIC1_BASE
137
138#undef NR_UICS
139#define NR_UICS 2
140
141/* EMAC DCRN's FIXME: armin */
142#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
143#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
144#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
145#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
146#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
147#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
148#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
149#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
150
151#include <asm/ibm405.h>
152
153#endif /* __ASM_IBMNP405H_H__ */
154#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
deleted file mode 100644
index 799a2eccccc3..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <asm/ocp.h>
13#include <asm/ppc4xx_pic.h>
14#include <platforms/4xx/ibmstb4.h>
15
16static struct ocp_func_iic_data ibmstb4_iic0_def = {
17 .fast_mode = 0, /* Use standad mode (100Khz) */
18};
19
20static struct ocp_func_iic_data ibmstb4_iic1_def = {
21 .fast_mode = 0, /* Use standad mode (100Khz) */
22};
23OCP_SYSFS_IIC_DATA()
24
25struct ocp_def core_ocp[] __initdata = {
26 { .vendor = OCP_VENDOR_IBM,
27 .function = OCP_FUNC_16550,
28 .index = 0,
29 .paddr = UART0_IO_BASE,
30 .irq = UART0_INT,
31 .pm = IBM_CPM_UART0,
32 },
33 { .vendor = OCP_VENDOR_IBM,
34 .function = OCP_FUNC_16550,
35 .index = 1,
36 .paddr = UART1_IO_BASE,
37 .irq = UART1_INT,
38 .pm = IBM_CPM_UART1,
39 },
40 { .vendor = OCP_VENDOR_IBM,
41 .function = OCP_FUNC_16550,
42 .index = 2,
43 .paddr = UART2_IO_BASE,
44 .irq = UART2_INT,
45 .pm = IBM_CPM_UART2,
46 },
47 { .vendor = OCP_VENDOR_IBM,
48 .function = OCP_FUNC_IIC,
49 .paddr = IIC0_BASE,
50 .irq = IIC0_IRQ,
51 .pm = IBM_CPM_IIC0,
52 .additions = &ibmstb4_iic0_def,
53 .show = &ocp_show_iic_data
54 },
55 { .vendor = OCP_VENDOR_IBM,
56 .function = OCP_FUNC_IIC,
57 .paddr = IIC1_BASE,
58 .irq = IIC1_IRQ,
59 .pm = IBM_CPM_IIC1,
60 .additions = &ibmstb4_iic1_def,
61 .show = &ocp_show_iic_data
62 },
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_GPIO,
65 .paddr = GPIO0_BASE,
66 .irq = OCP_IRQ_NA,
67 .pm = IBM_CPM_GPIO0,
68 },
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_IDE,
71 .paddr = IDE0_BASE,
72 .irq = IDE0_IRQ,
73 .pm = OCP_CPM_NA,
74 },
75 { .vendor = OCP_VENDOR_INVALID,
76 }
77};
78
79/* Polarity and triggering settings for internal interrupt sources */
80struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
81 { .polarity = 0x7fffff01,
82 .triggering = 0x00000000,
83 .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */
84 }
85};
86
87static struct resource ohci_usb_resources[] = {
88 [0] = {
89 .start = USB0_BASE,
90 .end = USB0_BASE + USB0_SIZE - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = USB0_IRQ,
95 .end = USB0_IRQ,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static u64 dma_mask = 0xffffffffULL;
101
102static struct platform_device ohci_usb_device = {
103 .name = "ppc-soc-ohci",
104 .id = 0,
105 .num_resources = ARRAY_SIZE(ohci_usb_resources),
106 .resource = ohci_usb_resources,
107 .dev = {
108 .dma_mask = &dma_mask,
109 .coherent_dma_mask = 0xffffffffULL,
110 }
111};
112
113static struct platform_device *ibmstb4_devs[] __initdata = {
114 &ohci_usb_device,
115};
116
117static int __init
118ibmstb4_platform_add_devices(void)
119{
120 return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs));
121}
122arch_initcall(ibmstb4_platform_add_devices);
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
deleted file mode 100644
index 31a08abaa4a2..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.h
+++ /dev/null
@@ -1,235 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMSTB4_H__
12#define __ASM_IBMSTB4_H__
13
14
15/* serial port defines */
16#define STB04xxx_IO_BASE ((uint)0xe0000000)
17#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
18#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
19#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
20#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
21
22/*
23 * map STB04xxx internal i/o address (0x400x00xx) to an address
24 * which is below the 2GB limit...
25 *
26 * 4000 000x uart1 -> 0xe000 000x
27 * 4001 00xx ppu
28 * 4002 00xx smart card
29 * 4003 000x iic
30 * 4004 000x uart0
31 * 4005 0xxx timer
32 * 4006 00xx gpio
33 * 4007 00xx smart card
34 * 400b 000x iic
35 * 400c 000x scp
36 * 400d 000x modem
37 * 400e 000x uart2
38*/
39#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
40
41#define RS_TABLE_SIZE 3
42#define UART0_INT 20
43
44#ifdef __BOOTER__
45#define UART0_IO_BASE 0x40040000
46#else
47#define UART0_IO_BASE 0xe0040000
48#endif
49
50#define UART1_INT 21
51
52#ifdef __BOOTER__
53#define UART1_IO_BASE 0x40000000
54#else
55#define UART1_IO_BASE 0xe0000000
56#endif
57
58#define UART2_INT 31
59#ifdef __BOOTER__
60#define UART2_IO_BASE 0x400e0000
61#else
62#define UART2_IO_BASE 0xe00e0000
63#endif
64
65#define IDE0_BASE 0x400F0000
66#define IDE0_SIZE 0x200
67#define IDE0_IRQ 25
68#define IIC0_BASE 0x40030000
69#define IIC1_BASE 0x400b0000
70#define OPB0_BASE 0x40000000
71#define GPIO0_BASE 0x40060000
72
73#define USB0_BASE 0x40010000
74#define USB0_SIZE 0xA0
75#define USB0_IRQ 18
76
77#define IIC_NUMS 2
78#define UART_NUMS 3
79#define IIC0_IRQ 9
80#define IIC1_IRQ 10
81#define IIC_OWN 0x55
82#define IIC_CLOCK 50
83
84#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
85
86#define STD_UART_OP(num) \
87 { 0, BASE_BAUD, 0, UART##num##_INT, \
88 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
89 iomem_base: (u8 *)UART##num##_IO_BASE, \
90 io_type: SERIAL_IO_MEM},
91
92#if defined(CONFIG_UART0_TTYS0)
93#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
94#define SERIAL_PORT_DFNS \
95 STD_UART_OP(0) \
96 STD_UART_OP(1) \
97 STD_UART_OP(2)
98#endif
99
100#if defined(CONFIG_UART0_TTYS1)
101#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
102#define SERIAL_PORT_DFNS \
103 STD_UART_OP(1) \
104 STD_UART_OP(0) \
105 STD_UART_OP(2)
106#endif
107
108#if defined(CONFIG_UART0_TTYS2)
109#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
110#define SERIAL_PORT_DFNS \
111 STD_UART_OP(2) \
112 STD_UART_OP(0) \
113 STD_UART_OP(1)
114#endif
115
116#define DCRN_BE_BASE 0x090
117#define DCRN_DMA0_BASE 0x0C0
118#define DCRN_DMA1_BASE 0x0C8
119#define DCRN_DMA2_BASE 0x0D0
120#define DCRN_DMA3_BASE 0x0D8
121#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
122#define DCRN_DMASR_BASE 0x0E0
123#define DCRN_PLB0_BASE 0x054
124#define DCRN_PLB1_BASE 0x064
125#define DCRN_POB0_BASE 0x0B0
126#define DCRN_SCCR_BASE 0x120
127#define DCRN_UIC0_BASE 0x040
128#define DCRN_BE_BASE 0x090
129#define DCRN_DMA0_BASE 0x0C0
130#define DCRN_DMA1_BASE 0x0C8
131#define DCRN_DMA2_BASE 0x0D0
132#define DCRN_DMA3_BASE 0x0D8
133#define DCRN_CIC_BASE 0x030
134#define DCRN_DMASR_BASE 0x0E0
135#define DCRN_EBIMC_BASE 0x070
136#define DCRN_DCRX_BASE 0x020
137#define DCRN_CPMFR_BASE 0x102
138#define DCRN_SCCR_BASE 0x120
139#define UIC0 DCRN_UIC0_BASE
140
141#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
142#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
143#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
144#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
145#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
146#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
147#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
148#define IBM_CPM_DMA 0x01000000 /* DMA controller */
149#define IBM_CPM_DMA1 0x00800000 /* reserved */
150#define IBM_CPM_XPT1 0x00400000 /* reserved */
151#define IBM_CPM_XPT2 0x00200000 /* reserved */
152#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
153#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
154#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
155#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
156#define IBM_CPM_VID 0x00010000 /* reserved */
157#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
158#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
159#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
160#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
161#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
162#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
163#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
164#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
165#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
166#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
167#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
168#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
169#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
170#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
171
172#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
173 | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
174 | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
175 | IBM_CPM_XPT27 | IBM_CPM_UIC )
176
177#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
178#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
179/* DCRN_BESR */
180#define BESR_DSES 0x80000000 /* Data-Side Error Status */
181#define BESR_DMES 0x40000000 /* DMA Error Status */
182#define BESR_RWS 0x20000000 /* Read/Write Status */
183#define BESR_ETMASK 0x1C000000 /* Error Type */
184#define ET_PROT 0
185#define ET_PARITY 1
186#define ET_NCFG 2
187#define ET_BUSERR 4
188#define ET_BUSTO 6
189
190#define CHR1_CETE 0x00800000 /* CPU external timer enable */
191#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
192
193#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
194#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
195#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
196#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
197#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
198#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
199#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
200#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
201#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
202
203#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
204#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
205#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
206#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
207#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
208#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
209#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
210#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
211
212#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
213#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
214#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
215#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
216#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
217#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
218#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
219#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
220#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
221#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
222#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
223#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
224#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
225#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
226#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
227#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
228#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
229#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
230#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
231
232#include <asm/ibm405.h>
233
234#endif /* __ASM_IBMSTB4_H__ */
235#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
deleted file mode 100644
index 090ddcbecc5e..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <asm/ocp.h>
12#include <platforms/4xx/ibmstbx25.h>
13#include <asm/ppc4xx_pic.h>
14
15static struct ocp_func_iic_data ibmstbx25_iic0_def = {
16 .fast_mode = 0, /* Use standad mode (100Khz) */
17};
18OCP_SYSFS_IIC_DATA()
19
20struct ocp_def core_ocp[] __initdata = {
21 { .vendor = OCP_VENDOR_IBM,
22 .function = OCP_FUNC_16550,
23 .index = 0,
24 .paddr = UART0_IO_BASE,
25 .irq = UART0_INT,
26 .pm = IBM_CPM_UART0,
27 },
28 { .vendor = OCP_VENDOR_IBM,
29 .function = OCP_FUNC_16550,
30 .index = 1,
31 .paddr = UART1_IO_BASE,
32 .irq = UART1_INT,
33 .pm = IBM_CPM_UART1,
34 },
35 { .vendor = OCP_VENDOR_IBM,
36 .function = OCP_FUNC_16550,
37 .index = 2,
38 .paddr = UART2_IO_BASE,
39 .irq = UART2_INT,
40 .pm = IBM_CPM_UART2,
41 },
42 { .vendor = OCP_VENDOR_IBM,
43 .function = OCP_FUNC_IIC,
44 .paddr = IIC0_BASE,
45 .irq = IIC0_IRQ,
46 .pm = IBM_CPM_IIC0,
47 .additions = &ibmstbx25_iic0_def,
48 .show = &ocp_show_iic_data
49 },
50 { .vendor = OCP_VENDOR_IBM,
51 .function = OCP_FUNC_GPIO,
52 .paddr = GPIO0_BASE,
53 .irq = OCP_IRQ_NA,
54 .pm = IBM_CPM_GPIO0,
55 },
56 { .vendor = OCP_VENDOR_INVALID
57 }
58};
59
60/* Polarity and triggering settings for internal interrupt sources */
61struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
62 { .polarity = 0xffff8f80,
63 .triggering = 0x00000000,
64 .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */
65 }
66};
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h
deleted file mode 100644
index 31b63343e641..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMSTBX25_H__
12#define __ASM_IBMSTBX25_H__
13
14
15/* serial port defines */
16#define STBx25xx_IO_BASE ((uint)0xe0000000)
17#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE
18#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
19#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
20
21/*
22 * map STBxxxx internal i/o address (0x400x00xx) to an address
23 * which is below the 2GB limit...
24 *
25 * 4000 000x uart1 -> 0xe000 000x
26 * 4001 00xx uart2
27 * 4002 00xx smart card
28 * 4003 000x iic
29 * 4004 000x uart0
30 * 4005 0xxx timer
31 * 4006 00xx gpio
32 * 4007 00xx smart card
33 * 400b 000x iic
34 * 400c 000x scp
35 * 400d 000x modem
36 * 400e 000x uart2
37*/
38#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
39
40#define RS_TABLE_SIZE 3
41
42#define OPB_BASE_START 0x40000000
43#define EBIU_BASE_START 0xF0100000
44#define DCR_BASE_START 0x0000
45
46#ifdef __BOOTER__
47#define UART1_IO_BASE 0x40000000
48#define UART2_IO_BASE 0x40010000
49#else
50#define UART1_IO_BASE 0xe0000000
51#define UART2_IO_BASE 0xe0010000
52#endif
53#define SC0_BASE 0x40020000 /* smart card #0 */
54#define IIC0_BASE 0x40030000
55#ifdef __BOOTER__
56#define UART0_IO_BASE 0x40040000
57#else
58#define UART0_IO_BASE 0xe0040000
59#endif
60#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */
61#define GPT0_BASE 0x40050000 /* General purpose timers */
62#define GPIO0_BASE 0x40060000
63#define SC1_BASE 0x40070000 /* smart card #1 */
64#define SCP0_BASE 0x400C0000 /* Serial Controller Port */
65#define SSP0_BASE 0x400D0000 /* Sync serial port */
66
67#define IDE0_BASE 0xf0100000
68#define REDWOOD_IDE_CTRL 0xf1100000
69
70#define RTCFPC_IRQ 0
71#define XPORT_IRQ 1
72#define AUD_IRQ 2
73#define AID_IRQ 3
74#define DMA0 4
75#define DMA1_IRQ 5
76#define DMA2_IRQ 6
77#define DMA3_IRQ 7
78#define SC0_IRQ 8
79#define IIC0_IRQ 9
80#define IIR0_IRQ 10
81#define GPT0_IRQ 11
82#define GPT1_IRQ 12
83#define SCP0_IRQ 13
84#define SSP0_IRQ 14
85#define GPT2_IRQ 15 /* count down timer */
86#define SC1_IRQ 16
87/* IRQ 17 - 19 external */
88#define UART0_INT 20
89#define UART1_INT 21
90#define UART2_INT 22
91#define XPTDMA_IRQ 23
92#define DCRIDE_IRQ 24
93/* IRQ 25 - 30 external */
94#define IDE0_IRQ 26
95
96#define IIC_NUMS 1
97#define UART_NUMS 3
98#define IIC_OWN 0x55
99#define IIC_CLOCK 50
100
101#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
102
103#define STD_UART_OP(num) \
104 { 0, BASE_BAUD, 0, UART##num##_INT, \
105 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
106 iomem_base: (u8 *)UART##num##_IO_BASE, \
107 io_type: SERIAL_IO_MEM},
108
109#if defined(CONFIG_UART0_TTYS0)
110#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
111#define SERIAL_PORT_DFNS \
112 STD_UART_OP(0) \
113 STD_UART_OP(1) \
114 STD_UART_OP(2)
115#endif
116
117#if defined(CONFIG_UART0_TTYS1)
118#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
119#define SERIAL_PORT_DFNS \
120 STD_UART_OP(1) \
121 STD_UART_OP(0) \
122 STD_UART_OP(2)
123#endif
124
125#if defined(CONFIG_UART0_TTYS2)
126#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
127#define SERIAL_PORT_DFNS \
128 STD_UART_OP(2) \
129 STD_UART_OP(0) \
130 STD_UART_OP(1)
131#endif
132
133#define DCRN_BE_BASE 0x090
134#define DCRN_DMA0_BASE 0x0C0
135#define DCRN_DMA1_BASE 0x0C8
136#define DCRN_DMA2_BASE 0x0D0
137#define DCRN_DMA3_BASE 0x0D8
138#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
139#define DCRN_DMASR_BASE 0x0E0
140#define DCRN_PLB0_BASE 0x054
141#define DCRN_PLB1_BASE 0x064
142#define DCRN_POB0_BASE 0x0B0
143#define DCRN_SCCR_BASE 0x120
144#define DCRN_UIC0_BASE 0x040
145#define DCRN_BE_BASE 0x090
146#define DCRN_DMA0_BASE 0x0C0
147#define DCRN_DMA1_BASE 0x0C8
148#define DCRN_DMA2_BASE 0x0D0
149#define DCRN_DMA3_BASE 0x0D8
150#define DCRN_CIC_BASE 0x030
151#define DCRN_DMASR_BASE 0x0E0
152#define DCRN_EBIMC_BASE 0x070
153#define DCRN_DCRX_BASE 0x020
154#define DCRN_CPMFR_BASE 0x102
155#define DCRN_SCCR_BASE 0x120
156#define DCRN_RTCFP_BASE 0x310
157
158#define UIC0 DCRN_UIC0_BASE
159
160#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
161#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
162#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
163#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
164#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */
165#define IBM_CPM_DMA 0x01000000 /* DMA controller */
166#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */
167#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
168#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
169#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */
170#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
171#define IBM_CPM_VID 0x00010000 /* reserved */
172#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */
173#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
174#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
175#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
176#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
177#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
178#define IBM_CPM_C405T 0x00000100 /* CPU timers */
179#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
180#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
181#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */
182#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
183#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
184#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \
185 | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \
186 | IBM_CPM_XPT27 | IBM_CPM_UIC)
187
188#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
189#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
190/* DCRN_BESR */
191#define BESR_DSES 0x80000000 /* Data-Side Error Status */
192#define BESR_DMES 0x40000000 /* DMA Error Status */
193#define BESR_RWS 0x20000000 /* Read/Write Status */
194#define BESR_ETMASK 0x1C000000 /* Error Type */
195#define ET_PROT 0
196#define ET_PARITY 1
197#define ET_NCFG 2
198#define ET_BUSERR 4
199#define ET_BUSTO 6
200
201#define CHR1_CETE 0x00800000 /* CPU external timer enable */
202#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
203
204#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
205#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
206#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
207#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
208#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
209#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
210#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
211#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
212#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
213
214#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
215#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
216#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
217#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
218#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
219#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
220#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
221#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
222
223#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
224#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
225#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
226#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
227#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
228#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
229#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
230#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
231#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
232#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
233#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
234#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
235#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
236#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
237#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
238#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
239#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
240#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
241#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
242
243#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */
244#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */
245#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */
246#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */
247#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */
248#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */
249#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */
250#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */
251#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */
252#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */
253#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */
254
255#include <asm/ibm405.h>
256
257#endif /* __ASM_IBMSTBX25_H__ */
258#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
deleted file mode 100644
index f6d8c2e8b6b7..000000000000
--- a/arch/ppc/platforms/4xx/luan.c
+++ /dev/null
@@ -1,371 +0,0 @@
1/*
2 * Luan board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47
48#include <syslib/ibm44x_common.h>
49#include <syslib/ibm440gx_common.h>
50#include <syslib/ibm440sp_common.h>
51
52extern bd_t __res;
53
54static struct ibm44x_clocks clocks __initdata;
55
56static void __init
57luan_calibrate_decr(void)
58{
59 unsigned int freq;
60
61 if (mfspr(SPRN_CCR1) & CCR1_TCS)
62 freq = LUAN_TMR_CLK;
63 else
64 freq = clocks.cpu;
65
66 ibm44x_calibrate_decr(freq);
67}
68
69static int
70luan_show_cpuinfo(struct seq_file *m)
71{
72 seq_printf(m, "vendor\t\t: IBM\n");
73 seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
74
75 return 0;
76}
77
78static inline int
79luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
80{
81 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
82
83 /* PCIX0 in adapter mode, no host interrupt routing */
84
85 /* PCIX1 */
86 if (hose->index == 0) {
87 static char pci_irq_table[][4] =
88 /*
89 * PCI IDSEL/INTPIN->INTLINE
90 * A B C D
91 */
92 {
93 { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */
94 { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */
95 { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */
96 { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */
97 };
98 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
99 return PCI_IRQ_TABLE_LOOKUP;
100 /* PCIX2 */
101 } else if (hose->index == 1) {
102 static char pci_irq_table[][4] =
103 /*
104 * PCI IDSEL/INTPIN->INTLINE
105 * A B C D
106 */
107 {
108 { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */
109 { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */
110 { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */
111 { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */
112 };
113 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
114 return PCI_IRQ_TABLE_LOOKUP;
115 }
116 return -1;
117}
118
119static void __init luan_set_emacdata(void)
120{
121 struct ocp_def *def;
122 struct ocp_func_emac_data *emacdata;
123
124 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
125 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
126 emacdata = def->additions;
127 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
128 emacdata->phy_mode = PHY_MODE_GMII;
129 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
130}
131
132#define PCIX_READW(offset) \
133 (readw((void *)((u32)pcix_reg_base+offset)))
134
135#define PCIX_WRITEW(value, offset) \
136 (writew(value, (void *)((u32)pcix_reg_base+offset)))
137
138#define PCIX_WRITEL(value, offset) \
139 (writel(value, (void *)((u32)pcix_reg_base+offset)))
140
141static void __init
142luan_setup_pcix(void)
143{
144 int i;
145 void *pcix_reg_base;
146
147 for (i=0;i<3;i++) {
148 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
149
150 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
151 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
152
153 /* Disable all windows */
154 PCIX_WRITEL(0, PCIX0_POM0SA);
155 PCIX_WRITEL(0, PCIX0_POM1SA);
156 PCIX_WRITEL(0, PCIX0_POM2SA);
157 PCIX_WRITEL(0, PCIX0_PIM0SA);
158 PCIX_WRITEL(0, PCIX0_PIM0SAH);
159 PCIX_WRITEL(0, PCIX0_PIM1SA);
160 PCIX_WRITEL(0, PCIX0_PIM2SA);
161 PCIX_WRITEL(0, PCIX0_PIM2SAH);
162
163 /*
164 * Setup 512MB PLB->PCI outbound mem window
165 * (a_n000_0000->0_n000_0000)
166 * */
167 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
168 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
169 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
170 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
171 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
172
173 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
174 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
175 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
176 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
177 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
178
179 iounmap(pcix_reg_base);
180 }
181
182 eieio();
183}
184
185static void __init
186luan_setup_hose(struct pci_controller *hose,
187 int lower_mem,
188 int upper_mem,
189 int cfga,
190 int cfgd,
191 u64 pcix_io_base)
192{
193 char name[20];
194
195 sprintf(name, "PCIX%d host bridge", hose->index);
196
197 hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
198
199 pci_init_resource(&hose->io_resource,
200 LUAN_PCIX_LOWER_IO,
201 LUAN_PCIX_UPPER_IO,
202 IORESOURCE_IO,
203 name);
204
205 pci_init_resource(&hose->mem_resources[0],
206 lower_mem,
207 upper_mem,
208 IORESOURCE_MEM,
209 name);
210
211 hose->io_space.start = LUAN_PCIX_LOWER_IO;
212 hose->io_space.end = LUAN_PCIX_UPPER_IO;
213 hose->mem_space.start = lower_mem;
214 hose->mem_space.end = upper_mem;
215 hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
216 isa_io_base = (unsigned long) hose->io_base_virt;
217
218 setup_indirect_pci(hose, cfga, cfgd);
219 hose->set_cfg_type = 1;
220}
221
222static void __init
223luan_setup_hoses(void)
224{
225 struct pci_controller *hose1, *hose2;
226
227 /* Configure windows on the PCI-X host bridge */
228 luan_setup_pcix();
229
230 /* Allocate hoses for PCIX1 and PCIX2 */
231 hose1 = pcibios_alloc_controller();
232 if (!hose1)
233 return;
234
235 hose2 = pcibios_alloc_controller();
236 if (!hose2) {
237 pcibios_free_controller(hose1);
238 return;
239 }
240
241 /* Setup PCIX1 */
242 hose1->first_busno = 0;
243 hose1->last_busno = 0xff;
244
245 luan_setup_hose(hose1,
246 LUAN_PCIX1_LOWER_MEM,
247 LUAN_PCIX1_UPPER_MEM,
248 PCIX1_CFGA,
249 PCIX1_CFGD,
250 PCIX1_IO_BASE);
251
252 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
253
254 /* Setup PCIX2 */
255 hose2->first_busno = hose1->last_busno + 1;
256 hose2->last_busno = 0xff;
257
258 luan_setup_hose(hose2,
259 LUAN_PCIX2_LOWER_MEM,
260 LUAN_PCIX2_UPPER_MEM,
261 PCIX2_CFGA,
262 PCIX2_CFGD,
263 PCIX2_IO_BASE);
264
265 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
266
267 ppc_md.pci_swizzle = common_swizzle;
268 ppc_md.pci_map_irq = luan_map_irq;
269}
270
271TODC_ALLOC();
272
273static void __init
274luan_early_serial_map(void)
275{
276 struct uart_port port;
277
278 /* Setup ioremapped serial port access */
279 memset(&port, 0, sizeof(port));
280 port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
281 port.irq = UART0_INT;
282 port.uartclk = clocks.uart0;
283 port.regshift = 0;
284 port.iotype = UPIO_MEM;
285 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
286 port.line = 0;
287
288 if (early_serial_setup(&port) != 0) {
289 printk("Early serial init of port 0 failed\n");
290 }
291
292 port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
293 port.irq = UART1_INT;
294 port.uartclk = clocks.uart1;
295 port.line = 1;
296
297 if (early_serial_setup(&port) != 0) {
298 printk("Early serial init of port 1 failed\n");
299 }
300
301 port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
302 port.irq = UART2_INT;
303 port.uartclk = BASE_BAUD;
304 port.line = 2;
305
306 if (early_serial_setup(&port) != 0) {
307 printk("Early serial init of port 2 failed\n");
308 }
309}
310
311static void __init
312luan_setup_arch(void)
313{
314 luan_set_emacdata();
315
316#if !defined(CONFIG_BDI_SWITCH)
317 /*
318 * The Abatron BDI JTAG debugger does not tolerate others
319 * mucking with the debug registers.
320 */
321 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
322#endif
323
324 /*
325 * Determine various clocks.
326 * To be completely correct we should get SysClk
327 * from FPGA, because it can be changed by on-board switches
328 * --ebs
329 */
330 /* 440GX and 440SP clocking is the same -mdp */
331 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
332 ocp_sys_info.opb_bus_freq = clocks.opb;
333
334 /* init to some ~sane value until calibrate_delay() runs */
335 loops_per_jiffy = 50000000/HZ;
336
337 /* Setup PCIXn host bridges */
338 luan_setup_hoses();
339
340#ifdef CONFIG_BLK_DEV_INITRD
341 if (initrd_start)
342 ROOT_DEV = Root_RAM0;
343 else
344#endif
345#ifdef CONFIG_ROOT_NFS
346 ROOT_DEV = Root_NFS;
347#else
348 ROOT_DEV = Root_HDA1;
349#endif
350
351 luan_early_serial_map();
352
353 /* Identify the system */
354 printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
355}
356
357void __init platform_init(unsigned long r3, unsigned long r4,
358 unsigned long r5, unsigned long r6, unsigned long r7)
359{
360 ibm44x_platform_init(r3, r4, r5, r6, r7);
361
362 ppc_md.setup_arch = luan_setup_arch;
363 ppc_md.show_cpuinfo = luan_show_cpuinfo;
364 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
365 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
366
367 ppc_md.calibrate_decr = luan_calibrate_decr;
368#ifdef CONFIG_KGDB
369 ppc_md.early_serial_map = luan_early_serial_map;
370#endif
371}
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
deleted file mode 100644
index 68dd46b0a5c4..000000000000
--- a/arch/ppc/platforms/4xx/luan.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Luan board definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_LUAN_H__
17#define __ASM_LUAN_H__
18
19#include <platforms/4xx/ibm440sp.h>
20
21/* F/W TLB mapping used in bootloader glue to reset EMAC */
22#define PPC44x_EMAC0_MR0 0xa0000800
23
24/* Location of MAC addresses in PIBS image */
25#define PIBS_FLASH_BASE 0xffe00000
26#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
27
28/* External timer clock frequency */
29#define LUAN_TMR_CLK 25000000
30
31/* Flash */
32#define LUAN_FPGA_REG_0 0x0000000148300000ULL
33#define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40)
34#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL
35#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL
36#define LUAN_SMALL_FLASH_SIZE 0x100000
37#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL
38#define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
39#define LUAN_LARGE_FLASH_SIZE 0x400000
40
41/*
42 * Serial port defines
43 */
44#define RS_TABLE_SIZE 3
45
46/* PIBS defined UART mappings, used before early_serial_setup */
47#define UART0_IO_BASE 0xa0000200
48#define UART1_IO_BASE 0xa0000300
49#define UART2_IO_BASE 0xa0000600
50
51#define BASE_BAUD 11059200
52#define STD_UART_OP(num) \
53 { 0, BASE_BAUD, 0, UART##num##_INT, \
54 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
55 iomem_base: (void*)UART##num##_IO_BASE, \
56 io_type: SERIAL_IO_MEM},
57
58#define SERIAL_PORT_DFNS \
59 STD_UART_OP(0) \
60 STD_UART_OP(1) \
61 STD_UART_OP(2)
62
63/* PCI support */
64#define LUAN_PCIX_LOWER_IO 0x00000000
65#define LUAN_PCIX_UPPER_IO 0x0000ffff
66#define LUAN_PCIX0_LOWER_MEM 0x80000000
67#define LUAN_PCIX0_UPPER_MEM 0x9fffffff
68#define LUAN_PCIX1_LOWER_MEM 0xa0000000
69#define LUAN_PCIX1_UPPER_MEM 0xbfffffff
70#define LUAN_PCIX2_LOWER_MEM 0xc0000000
71#define LUAN_PCIX2_UPPER_MEM 0xdfffffff
72
73#define LUAN_PCIX_MEM_SIZE 0x20000000
74#define LUAN_PCIX_MEM_OFFSET 0x00000000
75
76#endif /* __ASM_LUAN_H__ */
77#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
deleted file mode 100644
index 308386ef6f77..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ /dev/null
@@ -1,350 +0,0 @@
1/*
2 * Ocotea board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2003-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47#include <asm/tlbflush.h>
48
49#include <syslib/gen550.h>
50#include <syslib/ibm440gx_common.h>
51
52extern bd_t __res;
53
54static struct ibm44x_clocks clocks __initdata;
55
56static void __init
57ocotea_calibrate_decr(void)
58{
59 unsigned int freq;
60
61 if (mfspr(SPRN_CCR1) & CCR1_TCS)
62 freq = OCOTEA_TMR_CLK;
63 else
64 freq = clocks.cpu;
65
66 ibm44x_calibrate_decr(freq);
67}
68
69static int
70ocotea_show_cpuinfo(struct seq_file *m)
71{
72 seq_printf(m, "vendor\t\t: IBM\n");
73 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
74 ibm440gx_show_cpuinfo(m);
75 return 0;
76}
77
78static inline int
79ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
80{
81 static char pci_irq_table[][4] =
82 /*
83 * PCI IDSEL/INTPIN->INTLINE
84 * A B C D
85 */
86 {
87 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
88 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
89 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
90 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
91 };
92
93 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
94 return PCI_IRQ_TABLE_LOOKUP;
95}
96
97static void __init ocotea_set_emacdata(void)
98{
99 struct ocp_def *def;
100 struct ocp_func_emac_data *emacdata;
101 int i;
102
103 /*
104 * Note: Current rev. board only operates in Group 4a
105 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
106 * for RGMII (though these could run in RTBI just the same).
107 *
108 * The FPGA reg 3 information isn't even suitable for
109 * determining the phy_mode, so if the board becomes
110 * usable in !4a, it will be necessary to parse an environment
111 * variable from the firmware or similar to properly configure
112 * the phy_map/phy_mode.
113 */
114 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
115 for (i=0; i<4; i++) {
116 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
117 emacdata = def->additions;
118 if (i < 2) {
119 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
120 emacdata->phy_mode = PHY_MODE_SMII;
121 }
122 else {
123 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
124 emacdata->phy_mode = PHY_MODE_RGMII;
125 }
126 if (i == 0)
127 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
128 else if (i == 1)
129 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
130 else if (i == 2)
131 memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
132 else if (i == 3)
133 memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
134 }
135}
136
137#define PCIX_READW(offset) \
138 (readw(pcix_reg_base+offset))
139
140#define PCIX_WRITEW(value, offset) \
141 (writew(value, pcix_reg_base+offset))
142
143#define PCIX_WRITEL(value, offset) \
144 (writel(value, pcix_reg_base+offset))
145
146/*
147 * FIXME: This is only here to "make it work". This will move
148 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
149 * configuration library. -Matt
150 */
151static void __init
152ocotea_setup_pcix(void)
153{
154 void *pcix_reg_base;
155
156 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
157
158 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
159 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
160
161 /* Disable all windows */
162 PCIX_WRITEL(0, PCIX0_POM0SA);
163 PCIX_WRITEL(0, PCIX0_POM1SA);
164 PCIX_WRITEL(0, PCIX0_POM2SA);
165 PCIX_WRITEL(0, PCIX0_PIM0SA);
166 PCIX_WRITEL(0, PCIX0_PIM0SAH);
167 PCIX_WRITEL(0, PCIX0_PIM1SA);
168 PCIX_WRITEL(0, PCIX0_PIM2SA);
169 PCIX_WRITEL(0, PCIX0_PIM2SAH);
170
171 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
172 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
173 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
174 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
175 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
176 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
177
178 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
179 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
180 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
181 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
182
183 eieio();
184}
185
186static void __init
187ocotea_setup_hose(void)
188{
189 struct pci_controller *hose;
190
191 /* Configure windows on the PCI-X host bridge */
192 ocotea_setup_pcix();
193
194 hose = pcibios_alloc_controller();
195
196 if (!hose)
197 return;
198
199 hose->first_busno = 0;
200 hose->last_busno = 0xff;
201
202 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
203
204 pci_init_resource(&hose->io_resource,
205 OCOTEA_PCI_LOWER_IO,
206 OCOTEA_PCI_UPPER_IO,
207 IORESOURCE_IO,
208 "PCI host bridge");
209
210 pci_init_resource(&hose->mem_resources[0],
211 OCOTEA_PCI_LOWER_MEM,
212 OCOTEA_PCI_UPPER_MEM,
213 IORESOURCE_MEM,
214 "PCI host bridge");
215
216 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
217 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
218 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
219 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
220 hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
221 isa_io_base = (unsigned long) hose->io_base_virt;
222
223 setup_indirect_pci(hose,
224 OCOTEA_PCI_CFGA_PLB32,
225 OCOTEA_PCI_CFGD_PLB32);
226 hose->set_cfg_type = 1;
227
228 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
229
230 ppc_md.pci_swizzle = common_swizzle;
231 ppc_md.pci_map_irq = ocotea_map_irq;
232}
233
234
235TODC_ALLOC();
236
237static void __init
238ocotea_early_serial_map(void)
239{
240 struct uart_port port;
241
242 /* Setup ioremapped serial port access */
243 memset(&port, 0, sizeof(port));
244 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
245 port.irq = UART0_INT;
246 port.uartclk = clocks.uart0;
247 port.regshift = 0;
248 port.iotype = UPIO_MEM;
249 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
250 port.line = 0;
251
252 if (early_serial_setup(&port) != 0) {
253 printk("Early serial init of port 0 failed\n");
254 }
255
256#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
257 /* Configure debug serial access */
258 gen550_init(0, &port);
259
260 /* Purge TLB entry added in head_44x.S for early serial access */
261 _tlbie(UART0_IO_BASE, 0);
262#endif
263
264 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
265 port.irq = UART1_INT;
266 port.uartclk = clocks.uart1;
267 port.line = 1;
268
269 if (early_serial_setup(&port) != 0) {
270 printk("Early serial init of port 1 failed\n");
271 }
272
273#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
274 /* Configure debug serial access */
275 gen550_init(1, &port);
276#endif
277}
278
279static void __init
280ocotea_setup_arch(void)
281{
282 ocotea_set_emacdata();
283
284 ibm440gx_tah_enable();
285
286 /*
287 * Determine various clocks.
288 * To be completely correct we should get SysClk
289 * from FPGA, because it can be changed by on-board switches
290 * --ebs
291 */
292 ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
293 ocp_sys_info.opb_bus_freq = clocks.opb;
294
295 /* Setup TODC access */
296 TODC_INIT(TODC_TYPE_DS1743,
297 0,
298 0,
299 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
300 8);
301
302 /* init to some ~sane value until calibrate_delay() runs */
303 loops_per_jiffy = 50000000/HZ;
304
305 /* Setup PCI host bridge */
306 ocotea_setup_hose();
307
308#ifdef CONFIG_BLK_DEV_INITRD
309 if (initrd_start)
310 ROOT_DEV = Root_RAM0;
311 else
312#endif
313#ifdef CONFIG_ROOT_NFS
314 ROOT_DEV = Root_NFS;
315#else
316 ROOT_DEV = Root_HDA1;
317#endif
318
319 ocotea_early_serial_map();
320
321 /* Identify the system */
322 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
323}
324
325static void __init ocotea_init(void)
326{
327 ibm440gx_l2c_setup(&clocks);
328}
329
330void __init platform_init(unsigned long r3, unsigned long r4,
331 unsigned long r5, unsigned long r6, unsigned long r7)
332{
333 ibm440gx_platform_init(r3, r4, r5, r6, r7);
334
335 ppc_md.setup_arch = ocotea_setup_arch;
336 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
337 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
338
339 ppc_md.calibrate_decr = ocotea_calibrate_decr;
340 ppc_md.time_init = todc_time_init;
341 ppc_md.set_rtc_time = todc_set_rtc_time;
342 ppc_md.get_rtc_time = todc_get_rtc_time;
343
344 ppc_md.nvram_read_val = todc_direct_read_val;
345 ppc_md.nvram_write_val = todc_direct_write_val;
346#ifdef CONFIG_KGDB
347 ppc_md.early_serial_map = ocotea_early_serial_map;
348#endif
349 ppc_md.init = ocotea_init;
350}
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
deleted file mode 100644
index 89730ce2322c..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Ocotea board definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2003-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_OCOTEA_H__
17#define __ASM_OCOTEA_H__
18
19#include <platforms/4xx/ibm440gx.h>
20
21/* F/W TLB mapping used in bootloader glue to reset EMAC */
22#define PPC44x_EMAC0_MR0 0xe0000800
23
24/* Location of MAC addresses in PIBS image */
25#define PIBS_FLASH_BASE 0xfff00000
26#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
27#define PIBS_MAC_SIZE 0x200
28#define PIBS_MAC_OFFSET 0x100
29
30/* External timer clock frequency */
31#define OCOTEA_TMR_CLK 25000000
32
33/* RTC/NVRAM location */
34#define OCOTEA_RTC_ADDR 0x0000000148000000ULL
35#define OCOTEA_RTC_SIZE 0x2000
36
37/* Flash */
38#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
39#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
40#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
41#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
42#define OCOTEA_SMALL_FLASH_SIZE 0x100000
43#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
44#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
45#define OCOTEA_LARGE_FLASH_SIZE 0x400000
46
47/* FPGA_REG_3 (Ethernet Groups) */
48#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
49
50/*
51 * Serial port defines
52 */
53#define RS_TABLE_SIZE 2
54
55#if defined(__BOOTER__)
56/* OpenBIOS defined UART mappings, used by bootloader shim */
57#define UART0_IO_BASE 0xE0000200
58#define UART1_IO_BASE 0xE0000300
59#else
60/* head_44x.S created UART mapping, used before early_serial_setup.
61 * We cannot use default OpenBIOS UART mappings because they
62 * don't work for configurations with more than 512M RAM. --ebs
63 */
64#define UART0_IO_BASE 0xF0000200
65#define UART1_IO_BASE 0xF0000300
66#endif
67
68#define BASE_BAUD 11059200/16
69#define STD_UART_OP(num) \
70 { 0, BASE_BAUD, 0, UART##num##_INT, \
71 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
72 iomem_base: (void*)UART##num##_IO_BASE, \
73 io_type: SERIAL_IO_MEM},
74
75#define SERIAL_PORT_DFNS \
76 STD_UART_OP(0) \
77 STD_UART_OP(1)
78
79/* PCI support */
80#define OCOTEA_PCI_LOWER_IO 0x00000000
81#define OCOTEA_PCI_UPPER_IO 0x0000ffff
82#define OCOTEA_PCI_LOWER_MEM 0x80000000
83#define OCOTEA_PCI_UPPER_MEM 0xffffefff
84
85#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
86#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
87#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
88
89#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
90#define OCOTEA_PCI_IO_SIZE 0x00010000
91#define OCOTEA_PCI_MEM_OFFSET 0x00000000
92
93#endif /* __ASM_OCOTEA_H__ */
94#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
deleted file mode 100644
index 1be5d1c8e266..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * PPC440SPe I/O descriptions
3 *
4 * Roland Dreier <rolandd@cisco.com>
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/init.h>
20#include <linux/module.h>
21#include <platforms/4xx/ppc440spe.h>
22#include <asm/ocp.h>
23#include <asm/ppc4xx_pic.h>
24
25static struct ocp_func_emac_data ppc440spe_emac0_def = {
26 .rgmii_idx = -1, /* No RGMII */
27 .rgmii_mux = -1, /* No RGMII */
28 .zmii_idx = -1, /* No ZMII */
29 .zmii_mux = -1, /* No ZMII */
30 .mal_idx = 0, /* MAL device index */
31 .mal_rx_chan = 0, /* MAL rx channel number */
32 .mal_tx_chan = 0, /* MAL tx channel number */
33 .wol_irq = 61, /* WOL interrupt number */
34 .mdio_idx = -1, /* No shared MDIO */
35 .tah_idx = -1, /* No TAH */
36};
37OCP_SYSFS_EMAC_DATA()
38
39static struct ocp_func_mal_data ppc440spe_mal0_def = {
40 .num_tx_chans = 1, /* Number of TX channels */
41 .num_rx_chans = 1, /* Number of RX channels */
42 .txeob_irq = 38, /* TX End Of Buffer IRQ */
43 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
44 .txde_irq = 34, /* TX Descriptor Error IRQ */
45 .rxde_irq = 35, /* RX Descriptor Error IRQ */
46 .serr_irq = 33, /* MAL System Error IRQ */
47 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
48};
49OCP_SYSFS_MAL_DATA()
50
51static struct ocp_func_iic_data ppc440spe_iic0_def = {
52 .fast_mode = 0, /* Use standad mode (100Khz) */
53};
54
55static struct ocp_func_iic_data ppc440spe_iic1_def = {
56 .fast_mode = 0, /* Use standad mode (100Khz) */
57};
58OCP_SYSFS_IIC_DATA()
59
60struct ocp_def core_ocp[] = {
61 { .vendor = OCP_VENDOR_IBM,
62 .function = OCP_FUNC_16550,
63 .index = 0,
64 .paddr = PPC440SPE_UART0_ADDR,
65 .irq = UART0_INT,
66 .pm = IBM_CPM_UART0,
67 },
68 { .vendor = OCP_VENDOR_IBM,
69 .function = OCP_FUNC_16550,
70 .index = 1,
71 .paddr = PPC440SPE_UART1_ADDR,
72 .irq = UART1_INT,
73 .pm = IBM_CPM_UART1,
74 },
75 { .vendor = OCP_VENDOR_IBM,
76 .function = OCP_FUNC_16550,
77 .index = 2,
78 .paddr = PPC440SPE_UART2_ADDR,
79 .irq = UART2_INT,
80 .pm = IBM_CPM_UART2,
81 },
82 { .vendor = OCP_VENDOR_IBM,
83 .function = OCP_FUNC_IIC,
84 .index = 0,
85 .paddr = 0x00000004f0000400ULL,
86 .irq = 2,
87 .pm = IBM_CPM_IIC0,
88 .additions = &ppc440spe_iic0_def,
89 .show = &ocp_show_iic_data
90 },
91 { .vendor = OCP_VENDOR_IBM,
92 .function = OCP_FUNC_IIC,
93 .index = 1,
94 .paddr = 0x00000004f0000500ULL,
95 .irq = 3,
96 .pm = IBM_CPM_IIC1,
97 .additions = &ppc440spe_iic1_def,
98 .show = &ocp_show_iic_data
99 },
100 { .vendor = OCP_VENDOR_IBM,
101 .function = OCP_FUNC_GPIO,
102 .index = 0,
103 .paddr = 0x00000004f0000700ULL,
104 .irq = OCP_IRQ_NA,
105 .pm = IBM_CPM_GPIO0,
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_MAL,
109 .paddr = OCP_PADDR_NA,
110 .irq = OCP_IRQ_NA,
111 .pm = OCP_CPM_NA,
112 .additions = &ppc440spe_mal0_def,
113 .show = &ocp_show_mal_data,
114 },
115 { .vendor = OCP_VENDOR_IBM,
116 .function = OCP_FUNC_EMAC,
117 .index = 0,
118 .paddr = 0x00000004f0000800ULL,
119 .irq = 60,
120 .pm = OCP_CPM_NA,
121 .additions = &ppc440spe_emac0_def,
122 .show = &ocp_show_emac_data,
123 },
124 { .vendor = OCP_VENDOR_INVALID
125 }
126};
127
128/* Polarity and triggering settings for internal interrupt sources */
129struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
130 { .polarity = 0xffffffff,
131 .triggering = 0x010f0004,
132 .ext_irq_mask = 0x00000000,
133 },
134 { .polarity = 0xffffffff,
135 .triggering = 0x001f8040,
136 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
137 },
138 { .polarity = 0xffffffff,
139 .triggering = 0x00000000,
140 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
141 },
142 { .polarity = 0xffffffff,
143 .triggering = 0x00000000,
144 .ext_irq_mask = 0x00000000,
145 },
146};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
deleted file mode 100644
index f1e867c4c9fc..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * PPC440SPe definitions
3 *
4 * Roland Dreier <rolandd@cisco.com>
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2004-2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_PPC440SPE_H
18#define __PPC_PLATFORMS_PPC440SPE_H
19
20
21#include <asm/ibm44x.h>
22
23/* UART */
24#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
25#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
26#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
27#define UART0_INT 0
28#define UART1_INT 1
29#define UART2_INT 37
30
31/* Clock and Power Management */
32#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
33#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
34#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
35#define IBM_CPM_CPU 0x02000000 /* processor core */
36#define IBM_CPM_DMA 0x01000000 /* DMA controller */
37#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
38#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
39#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
40#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
41#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
42#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
43#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
44#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
45#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
46#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
47#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
48#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
49#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
50#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
51#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
52#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
53#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
54
55#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
56 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
57 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
58 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
59 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
60 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
61 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
62#endif /* __PPC_PLATFORMS_PPC440SP_H */
63#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
deleted file mode 100644
index edf4d37d1a52..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Support for the IBM redwood5 eval board file
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/pagemap.h>
14#include <linux/platform_device.h>
15#include <linux/ioport.h>
16#include <asm/io.h>
17#include <asm/machdep.h>
18#include <asm/ppc4xx_pic.h>
19
20/*
21 * Define external IRQ senses and polarities.
22 */
23unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
24 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
25 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
26 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
30};
31
32static struct resource smc91x_resources[] = {
33 [0] = {
34 .start = SMC91111_BASE_ADDR,
35 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
36 .flags = IORESOURCE_MEM,
37 },
38 [1] = {
39 .start = SMC91111_IRQ,
40 .end = SMC91111_IRQ,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45static struct platform_device smc91x_device = {
46 .name = "smc91x",
47 .id = 0,
48 .num_resources = ARRAY_SIZE(smc91x_resources),
49 .resource = smc91x_resources,
50};
51
52static struct platform_device *redwood5_devs[] __initdata = {
53 &smc91x_device,
54};
55
56static int __init
57redwood5_platform_add_devices(void)
58{
59 return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs));
60}
61
62void __init
63redwood5_setup_arch(void)
64{
65 ppc4xx_setup_arch();
66
67#ifdef CONFIG_DEBUG_BRINGUP
68 printk("\n");
69 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
70 printk("\n");
71 printk("bi_s_version\t %s\n", bip->bi_s_version);
72 printk("bi_r_version\t %s\n", bip->bi_r_version);
73 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
74 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
75 bip->bi_enetaddr[0], bip->bi_enetaddr[1],
76 bip->bi_enetaddr[2], bip->bi_enetaddr[3],
77 bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
78
79 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
80 bip->bi_intfreq, bip->bi_intfreq/ 1000000);
81
82 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
83 bip->bi_busfreq, bip->bi_busfreq / 1000000 );
84 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
85 bip->bi_tbfreq, bip->bi_tbfreq/1000000);
86
87 printk("\n");
88#endif
89 device_initcall(redwood5_platform_add_devices);
90}
91
92void __init
93redwood5_map_io(void)
94{
95 int i;
96
97 ppc4xx_map_io();
98 for (i = 0; i < 16; i++) {
99 unsigned long v, p;
100
101 /* 0x400x0000 -> 0xe00x0000 */
102 p = 0x40000000 | (i << 16);
103 v = STB04xxx_IO_BASE | (i << 16);
104
105 io_block_mapping(v, p, PAGE_SIZE,
106 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED);
107 }
108
109
110}
111
112void __init
113platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
114 unsigned long r6, unsigned long r7)
115{
116 ppc4xx_init(r3, r4, r5, r6, r7);
117
118 ppc_md.setup_arch = redwood5_setup_arch;
119 ppc_md.setup_io_mappings = redwood5_map_io;
120}
diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h
deleted file mode 100644
index 49edd4818970..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Macros, definitions, and data structures specific to the IBM PowerPC
3 * STB03xxx "Redwood" evaluation board.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_REDWOOD5_H__
15#define __ASM_REDWOOD5_H__
16
17/* Redwood5 has an STB04xxx core */
18#include <platforms/4xx/ibmstb4.h>
19
20#ifndef __ASSEMBLY__
21typedef struct board_info {
22 unsigned char bi_s_version[4]; /* Version of this structure */
23 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
24 unsigned int bi_memsize; /* DRAM installed, in bytes */
25 unsigned int bi_dummy; /* field shouldn't exist */
26 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* Bus speed, in Hz */
29 unsigned int bi_tbfreq; /* Software timebase freq */
30} bd_t;
31#endif /* !__ASSEMBLY__ */
32
33
34#define SMC91111_BASE_ADDR 0xf2000300
35#define SMC91111_REG_SIZE 16
36#define SMC91111_IRQ 28
37
38#ifdef MAX_HWIFS
39#undef MAX_HWIFS
40#endif
41#define MAX_HWIFS 1
42
43#define _IO_BASE 0
44#define _ISA_MEM_BASE 0
45#define PCI_DRAM_OFFSET 0
46
47#define BASE_BAUD (378000000 / 18 / 16)
48
49#define PPC4xx_MACHINE_NAME "IBM Redwood5"
50
51#endif /* __ASM_REDWOOD5_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
deleted file mode 100644
index 006e29f83a1a..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/pagemap.h>
12#include <linux/platform_device.h>
13#include <linux/ioport.h>
14#include <asm/io.h>
15#include <asm/ppc4xx_pic.h>
16#include <linux/delay.h>
17#include <asm/machdep.h>
18
19/*
20 * Define external IRQ senses and polarities.
21 */
22unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
23 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
24 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
25 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
26 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
30 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
31 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
32 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
33};
34
35static struct resource smc91x_resources[] = {
36 [0] = {
37 .start = SMC91111_BASE_ADDR,
38 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .start = SMC91111_IRQ,
43 .end = SMC91111_IRQ,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48static struct platform_device smc91x_device = {
49 .name = "smc91x",
50 .id = 0,
51 .num_resources = ARRAY_SIZE(smc91x_resources),
52 .resource = smc91x_resources,
53};
54
55static struct platform_device *redwood6_devs[] __initdata = {
56 &smc91x_device,
57};
58
59static int __init
60redwood6_platform_add_devices(void)
61{
62 return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs));
63}
64
65
66void __init
67redwood6_setup_arch(void)
68{
69#ifdef CONFIG_IDE
70 void *xilinx, *xilinx_1, *xilinx_2;
71 unsigned short us_reg5;
72#endif
73
74 ppc4xx_setup_arch();
75
76#ifdef CONFIG_IDE
77 xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10);
78 /* init xilinx control registers - enable ide mux, clear reset bit */
79 if (!xilinx) {
80 printk(KERN_CRIT
81 "redwood6_setup_arch() xilinxi ioremap failed\n");
82 return;
83 }
84 xilinx_1 = xilinx + 0xa;
85 xilinx_2 = xilinx + 0xe;
86
87 us_reg5 = readb(xilinx_1);
88 writeb(0x01d1, xilinx_1);
89 writeb(0x0008, xilinx_2);
90
91 udelay(10 * 1000);
92
93 writeb(0x01d1, xilinx_1);
94 writeb(0x0008, xilinx_2);
95#endif
96
97#ifdef DEBUG_BRINGUP
98 bd_t *bip = (bd_t *) __res;
99 printk("\n");
100 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
101 printk("\n");
102 printk("bi_s_version\t %s\n", bip->bi_s_version);
103 printk("bi_r_version\t %s\n", bip->bi_r_version);
104 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
105 bip->bi_memsize / (1024 * 1000));
106 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
107 bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2],
108 bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
109
110 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
111 bip->bi_intfreq, bip->bi_intfreq / 1000000);
112
113 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
114 bip->bi_busfreq, bip->bi_busfreq / 1000000);
115 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
116 bip->bi_tbfreq, bip->bi_tbfreq / 1000000);
117
118 printk("\n");
119#endif
120
121 /* Identify the system */
122 printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
123 printk(KERN_INFO
124 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
125
126 device_initcall(redwood6_platform_add_devices);
127}
128
129void __init
130redwood6_map_io(void)
131{
132 int i;
133
134 ppc4xx_map_io();
135 for (i = 0; i < 16; i++) {
136 unsigned long v, p;
137
138 /* 0x400x0000 -> 0xe00x0000 */
139 p = 0x40000000 | (i << 16);
140 v = STBx25xx_IO_BASE | (i << 16);
141
142 io_block_mapping(v, p, PAGE_SIZE,
143 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
144 _PAGE_GUARDED);
145 }
146}
147
148void __init
149platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
150 unsigned long r6, unsigned long r7)
151{
152 ppc4xx_init(r3, r4, r5, r6, r7);
153
154 ppc_md.setup_arch = redwood6_setup_arch;
155 ppc_md.setup_io_mappings = redwood6_map_io;
156}
diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h
deleted file mode 100644
index 1edcbe5c51c7..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Macros, definitions, and data structures specific to the IBM PowerPC
3 * STBx25xx "Redwood6" evaluation board.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_REDWOOD5_H__
15#define __ASM_REDWOOD5_H__
16
17/* Redwood6 has an STBx25xx core */
18#include <platforms/4xx/ibmstbx25.h>
19
20#ifndef __ASSEMBLY__
21typedef struct board_info {
22 unsigned char bi_s_version[4]; /* Version of this structure */
23 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
24 unsigned int bi_memsize; /* DRAM installed, in bytes */
25 unsigned int bi_dummy; /* field shouldn't exist */
26 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* Bus speed, in Hz */
29 unsigned int bi_tbfreq; /* Software timebase freq */
30} bd_t;
31#endif /* !__ASSEMBLY__ */
32
33#define SMC91111_BASE_ADDR 0xf2030300
34#define SMC91111_REG_SIZE 16
35#define SMC91111_IRQ 27
36#define IDE_XLINUX_MUX_BASE 0xf2040000
37#define IDE_DMA_ADDR 0xfce00000
38
39#ifdef MAX_HWIFS
40#undef MAX_HWIFS
41#endif
42#define MAX_HWIFS 1
43
44#define _IO_BASE 0
45#define _ISA_MEM_BASE 0
46#define PCI_DRAM_OFFSET 0
47
48#define BASE_BAUD (378000000 / 18 / 16)
49
50#define PPC4xx_MACHINE_NAME "IBM Redwood6"
51
52#endif /* __ASM_REDWOOD5_H__ */
53#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
deleted file mode 100644
index 8689f3e8ef3a..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Architecture- / platform-specific boot-time initialization code for
3 * IBM PowerPC 4xx based boards.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/smp.h>
14#include <linux/threads.h>
15#include <linux/param.h>
16#include <linux/string.h>
17#include <linux/pci.h>
18#include <linux/rtc.h>
19
20#include <asm/ocp.h>
21#include <asm/ppc4xx_pic.h>
22#include <asm/system.h>
23#include <asm/pci-bridge.h>
24#include <asm/machdep.h>
25#include <asm/page.h>
26#include <asm/time.h>
27#include <asm/io.h>
28#include <asm/ibm_ocp_pci.h>
29#include <asm/todc.h>
30
31#undef DEBUG
32
33#ifdef DEBUG
34#define DBG(x...) printk(x)
35#else
36#define DBG(x...)
37#endif
38
39void *kb_cs;
40void *kb_data;
41void *sycamore_rtc_base;
42
43/*
44 * Define external IRQ senses and polarities.
45 */
46unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
47 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
48 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
49 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
60};
61
62
63/* Some IRQs unique to Sycamore.
64 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
65 */
66int __init
67ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
68{
69 static char pci_irq_table[][4] =
70 /*
71 * PCI IDSEL/INTPIN->INTLINE
72 * A B C D
73 */
74 {
75 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
76 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
77 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
78 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
79 };
80
81 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
82 return PCI_IRQ_TABLE_LOOKUP;
83};
84
85void __init
86sycamore_setup_arch(void)
87{
88 void *fpga_brdc;
89 unsigned char fpga_brdc_data;
90 void *fpga_enable;
91 void *fpga_polarity;
92 void *fpga_status;
93 void *fpga_trigger;
94
95 ppc4xx_setup_arch();
96
97 ibm_ocp_set_emac(0, 0);
98
99 kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
100 if (!kb_data) {
101 printk(KERN_CRIT
102 "sycamore_setup_arch() kb_data ioremap failed\n");
103 return;
104 }
105
106 kb_cs = kb_data + 1;
107
108 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
109 if (!fpga_status) {
110 printk(KERN_CRIT
111 "sycamore_setup_arch() fpga_status ioremap failed\n");
112 return;
113 }
114
115 fpga_enable = fpga_status + 1;
116 fpga_polarity = fpga_status + 2;
117 fpga_trigger = fpga_status + 3;
118 fpga_brdc = fpga_status + 4;
119
120 /* split the keyboard and mouse interrupts */
121 fpga_brdc_data = readb(fpga_brdc);
122 fpga_brdc_data |= 0x80;
123 writeb(fpga_brdc_data, fpga_brdc);
124
125 writeb(0x3, fpga_enable);
126
127 writeb(0x3, fpga_polarity);
128
129 writeb(0x3, fpga_trigger);
130
131 /* RTC step for the sycamore */
132 sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
133 TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
134 sycamore_rtc_base, 8);
135
136 /* Identify the system */
137 printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
138 printk(KERN_INFO
139 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
140}
141
142void __init
143bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
144{
145#ifdef CONFIG_PCI
146 unsigned int bar_response, bar;
147 /*
148 * Expected PCI mapping:
149 *
150 * PLB addr PCI memory addr
151 * --------------------- ---------------------
152 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
153 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
154 *
155 * PLB addr PCI io addr
156 * --------------------- ---------------------
157 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
158 *
159 * The following code is simplified by assuming that the bootrom
160 * has been well behaved in following this mapping.
161 */
162
163#ifdef DEBUG
164 int i;
165
166 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
167 printk("PCI bridge regs before fixup \n");
168 for (i = 0; i <= 3; i++) {
169 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
170 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
171 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
172 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
173 }
174 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
175 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
176 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
177 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
178
179#endif
180
181 /* added for IBM boot rom version 1.15 bios bar changes -AK */
182
183 /* Disable region first */
184 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
185 /* PLB starting addr, PCI: 0x80000000 */
186 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
187 /* PCI start addr, 0x80000000 */
188 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
189 /* 512MB range of PLB to PCI */
190 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
191 /* Enable no pre-fetch, enable region */
192 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
193 (PPC405_PCI_UPPER_MEM -
194 PPC405_PCI_MEM_BASE)) | 0x01));
195
196 /* Enable inbound region one - 1GB size */
197 out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
198
199 /* Disable outbound region one */
200 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
201 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
202 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
203 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
204 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
205
206 /* Disable inbound region two */
207 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
208
209 /* Disable outbound region two */
210 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
211 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
212 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
213 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
214 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
215
216 /* Zero config bars */
217 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
218 early_write_config_dword(hose, hose->first_busno,
219 PCI_FUNC(hose->first_busno), bar,
220 0x00000000);
221 early_read_config_dword(hose, hose->first_busno,
222 PCI_FUNC(hose->first_busno), bar,
223 &bar_response);
224 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
225 hose->first_busno, PCI_SLOT(hose->first_busno),
226 PCI_FUNC(hose->first_busno), bar, bar_response);
227 }
228 /* end workaround */
229
230#ifdef DEBUG
231 printk("PCI bridge regs after fixup \n");
232 for (i = 0; i <= 3; i++) {
233 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
234 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
235 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
236 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
237 }
238 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
239 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
240 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
241 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
242
243#endif
244#endif
245
246}
247
248void __init
249sycamore_map_io(void)
250{
251 ppc4xx_map_io();
252 io_block_mapping(SYCAMORE_RTC_VADDR,
253 SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
254}
255
256void __init
257platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
258 unsigned long r6, unsigned long r7)
259{
260 ppc4xx_init(r3, r4, r5, r6, r7);
261
262 ppc_md.setup_arch = sycamore_setup_arch;
263 ppc_md.setup_io_mappings = sycamore_map_io;
264
265#ifdef CONFIG_GEN_RTC
266 ppc_md.time_init = todc_time_init;
267 ppc_md.set_rtc_time = todc_set_rtc_time;
268 ppc_md.get_rtc_time = todc_get_rtc_time;
269 ppc_md.nvram_read_val = todc_direct_read_val;
270 ppc_md.nvram_write_val = todc_direct_write_val;
271#endif
272}
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
deleted file mode 100644
index 69b169eac053..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Sycamore board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Armin Kuster <akuster@mvista.com>
9 * 2000 (c) MontaVista, Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __ASM_SYCAMORE_H__
20#define __ASM_SYCAMORE_H__
21
22#include <platforms/4xx/ibm405gpr.h>
23#include <asm/ppcboot.h>
24
25/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
26 * Generic 4xx plus RTC.
27 */
28
29#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
30#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
31#define SYCAMORE_RTC_SIZE ((uint)8*1024)
32
33#define BASE_BAUD 691200
34
35#define SYCAMORE_PS2_BASE 0xF0100000
36
37/* Flash */
38#define PPC40x_FPGA_BASE 0xF0300000
39#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
40#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
41#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
42#define PPC40x_FLASH_LOW 0xFFF00000
43#define PPC40x_FLASH_HIGH 0xFFF80000
44#define PPC40x_FLASH_SIZE 0x80000
45
46#define PPC4xx_MACHINE_NAME "IBM Sycamore"
47
48#endif /* __ASM_SYCAMORE_H__ */
49#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
deleted file mode 100644
index 115694275083..000000000000
--- a/arch/ppc/platforms/4xx/taishan.c
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/taishan.c
3 *
4 * AMCC Taishan board specific routines
5 *
6 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/nand.h>
36#include <linux/mtd/ndfc.h>
37#include <linux/mtd/physmap.h>
38
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/bootinfo.h>
42#include <asm/ppcboot.h>
43
44#include <syslib/gen550.h>
45#include <syslib/ibm440gx_common.h>
46
47extern bd_t __res;
48
49static struct ibm44x_clocks clocks __initdata;
50
51/*
52 * NOR FLASH configuration (using mtd physmap driver)
53 */
54
55/* start will be added dynamically, end is always fixed */
56static struct resource taishan_nor_resource = {
57 .start = TAISHAN_FLASH_ADDR,
58 .end = 0x1ffffffffULL,
59 .flags = IORESOURCE_MEM,
60};
61
62#define RW_PART0_OF 0
63#define RW_PART0_SZ 0x180000
64#define RW_PART1_SZ 0x200000
65/* Partition 2 will be autosized dynamically... */
66#define RW_PART3_SZ 0x80000
67#define RW_PART4_SZ 0x40000
68
69static struct mtd_partition taishan_nor_parts[] = {
70 {
71 .name = "kernel",
72 .offset = 0,
73 .size = RW_PART0_SZ
74 },
75 {
76 .name = "root",
77 .offset = MTDPART_OFS_APPEND,
78 .size = RW_PART1_SZ,
79 },
80 {
81 .name = "user",
82 .offset = MTDPART_OFS_APPEND,
83/* .size = RW_PART2_SZ */ /* will be adjusted dynamically */
84 },
85 {
86 .name = "env",
87 .offset = MTDPART_OFS_APPEND,
88 .size = RW_PART3_SZ,
89 },
90 {
91 .name = "u-boot",
92 .offset = MTDPART_OFS_APPEND,
93 .size = RW_PART4_SZ,
94 }
95};
96
97static struct physmap_flash_data taishan_nor_data = {
98 .width = 4,
99 .parts = taishan_nor_parts,
100 .nr_parts = ARRAY_SIZE(taishan_nor_parts),
101};
102
103static struct platform_device taishan_nor_device = {
104 .name = "physmap-flash",
105 .id = 0,
106 .dev = {
107 .platform_data = &taishan_nor_data,
108 },
109 .num_resources = 1,
110 .resource = &taishan_nor_resource,
111};
112
113static int taishan_setup_flash(void)
114{
115 /*
116 * Adjust partition 2 to flash size
117 */
118 taishan_nor_parts[2].size = __res.bi_flashsize -
119 RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
120
121 platform_device_register(&taishan_nor_device);
122
123 return 0;
124}
125arch_initcall(taishan_setup_flash);
126
127static void __init
128taishan_calibrate_decr(void)
129{
130 unsigned int freq;
131
132 if (mfspr(SPRN_CCR1) & CCR1_TCS)
133 freq = TAISHAN_TMR_CLK;
134 else
135 freq = clocks.cpu;
136
137 ibm44x_calibrate_decr(freq);
138}
139
140static int
141taishan_show_cpuinfo(struct seq_file *m)
142{
143 seq_printf(m, "vendor\t\t: AMCC\n");
144 seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
145 ibm440gx_show_cpuinfo(m);
146 return 0;
147}
148
149static inline int
150taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
151{
152 static char pci_irq_table[][4] =
153 /*
154 * PCI IDSEL/INTPIN->INTLINE
155 * A B C D
156 */
157 {
158 { 23, 24, 25, 26 }, /* IDSEL 1 - PCI Slot 0 */
159 { 24, 25, 26, 23 }, /* IDSEL 2 - PCI Slot 1 */
160 };
161
162 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
163 return PCI_IRQ_TABLE_LOOKUP;
164}
165
166static void __init taishan_set_emacdata(void)
167{
168 struct ocp_def *def;
169 struct ocp_func_emac_data *emacdata;
170 int i;
171
172 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
173 for (i=2; i<4; i++) {
174 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
175 emacdata = def->additions;
176 if (i < 2) {
177 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
178 emacdata->phy_mode = PHY_MODE_SMII;
179 } else {
180 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
181 emacdata->phy_mode = PHY_MODE_RGMII;
182 }
183 if (i == 0)
184 memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
185 else if (i == 1)
186 memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
187 else if (i == 2)
188 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
189 else if (i == 3)
190 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
191 }
192}
193
194#define PCIX_READW(offset) \
195 (readw(pcix_reg_base+offset))
196
197#define PCIX_WRITEW(value, offset) \
198 (writew(value, pcix_reg_base+offset))
199
200#define PCIX_WRITEL(value, offset) \
201 (writel(value, pcix_reg_base+offset))
202
203/*
204 * FIXME: This is only here to "make it work". This will move
205 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
206 * configuration library. -Matt
207 */
208static void __init
209taishan_setup_pcix(void)
210{
211 void *pcix_reg_base;
212
213 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
214
215 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
216 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
217
218 /* Disable all windows */
219 PCIX_WRITEL(0, PCIX0_POM0SA);
220 PCIX_WRITEL(0, PCIX0_POM1SA);
221 PCIX_WRITEL(0, PCIX0_POM2SA);
222 PCIX_WRITEL(0, PCIX0_PIM0SA);
223 PCIX_WRITEL(0, PCIX0_PIM0SAH);
224 PCIX_WRITEL(0, PCIX0_PIM1SA);
225 PCIX_WRITEL(0, PCIX0_PIM2SA);
226 PCIX_WRITEL(0, PCIX0_PIM2SAH);
227
228 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
229 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
230 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
231 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
232 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
233 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
234
235 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
236 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
237 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
238 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
239 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
240
241 iounmap(pcix_reg_base);
242
243 eieio();
244}
245
246static void __init
247taishan_setup_hose(void)
248{
249 struct pci_controller *hose;
250
251 /* Configure windows on the PCI-X host bridge */
252 taishan_setup_pcix();
253
254 hose = pcibios_alloc_controller();
255
256 if (!hose)
257 return;
258
259 hose->first_busno = 0;
260 hose->last_busno = 0xff;
261
262 hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
263
264 pci_init_resource(&hose->io_resource,
265 TAISHAN_PCI_LOWER_IO,
266 TAISHAN_PCI_UPPER_IO,
267 IORESOURCE_IO,
268 "PCI host bridge");
269
270 pci_init_resource(&hose->mem_resources[0],
271 TAISHAN_PCI_LOWER_MEM,
272 TAISHAN_PCI_UPPER_MEM,
273 IORESOURCE_MEM,
274 "PCI host bridge");
275
276 hose->io_space.start = TAISHAN_PCI_LOWER_IO;
277 hose->io_space.end = TAISHAN_PCI_UPPER_IO;
278 hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
279 hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
280 hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
281 isa_io_base = (unsigned long) hose->io_base_virt;
282
283 setup_indirect_pci(hose,
284 TAISHAN_PCI_CFGA_PLB32,
285 TAISHAN_PCI_CFGD_PLB32);
286 hose->set_cfg_type = 1;
287
288 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
289
290 ppc_md.pci_swizzle = common_swizzle;
291 ppc_md.pci_map_irq = taishan_map_irq;
292}
293
294
295static void __init
296taishan_early_serial_map(void)
297{
298 struct uart_port port;
299
300 /* Setup ioremapped serial port access */
301 memset(&port, 0, sizeof(port));
302 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
303 port.irq = UART0_INT;
304 port.uartclk = clocks.uart0;
305 port.regshift = 0;
306 port.iotype = UPIO_MEM;
307 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
308 port.line = 0;
309
310 if (early_serial_setup(&port) != 0)
311 printk("Early serial init of port 0 failed\n");
312
313#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
314 /* Configure debug serial access */
315 gen550_init(0, &port);
316
317 /* Purge TLB entry added in head_44x.S for early serial access */
318 _tlbie(UART0_IO_BASE, 0);
319#endif
320
321 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
322 port.irq = UART1_INT;
323 port.uartclk = clocks.uart1;
324 port.line = 1;
325
326 if (early_serial_setup(&port) != 0)
327 printk("Early serial init of port 1 failed\n");
328
329#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
330 /* Configure debug serial access */
331 gen550_init(1, &port);
332#endif
333}
334
335static void __init
336taishan_setup_arch(void)
337{
338 taishan_set_emacdata();
339
340 ibm440gx_tah_enable();
341
342 /*
343 * Determine various clocks.
344 * To be completely correct we should get SysClk
345 * from FPGA, because it can be changed by on-board switches
346 * --ebs
347 */
348 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
349 ocp_sys_info.opb_bus_freq = clocks.opb;
350
351 /* init to some ~sane value until calibrate_delay() runs */
352 loops_per_jiffy = 50000000/HZ;
353
354 /* Setup PCI host bridge */
355 taishan_setup_hose();
356
357#ifdef CONFIG_BLK_DEV_INITRD
358 if (initrd_start)
359 ROOT_DEV = Root_RAM0;
360 else
361#endif
362#ifdef CONFIG_ROOT_NFS
363 ROOT_DEV = Root_NFS;
364#else
365 ROOT_DEV = Root_HDA1;
366#endif
367
368 taishan_early_serial_map();
369
370 /* Identify the system */
371 printk("AMCC PowerPC 440GX Taishan Platform\n");
372}
373
374static void __init taishan_init(void)
375{
376 ibm440gx_l2c_setup(&clocks);
377}
378
379void __init platform_init(unsigned long r3, unsigned long r4,
380 unsigned long r5, unsigned long r6, unsigned long r7)
381{
382 ibm44x_platform_init(r3, r4, r5, r6, r7);
383
384 ppc_md.setup_arch = taishan_setup_arch;
385 ppc_md.show_cpuinfo = taishan_show_cpuinfo;
386 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
387
388 ppc_md.calibrate_decr = taishan_calibrate_decr;
389
390#ifdef CONFIG_KGDB
391 ppc_md.early_serial_map = taishan_early_serial_map;
392#endif
393 ppc_md.init = taishan_init;
394}
395
diff --git a/arch/ppc/platforms/4xx/taishan.h b/arch/ppc/platforms/4xx/taishan.h
deleted file mode 100644
index ea7561a80457..000000000000
--- a/arch/ppc/platforms/4xx/taishan.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/taishan.h
3 *
4 * AMCC Taishan board definitions
5 *
6 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_TAISHAN_H__
17#define __ASM_TAISHAN_H__
18
19#include <platforms/4xx/ibm440gx.h>
20
21/* External timer clock frequency */
22#define TAISHAN_TMR_CLK 25000000
23
24/* Flash */
25#define TAISHAN_FPGA_ADDR 0x0000000141000000ULL
26#define TAISHAN_LCM_ADDR 0x0000000142000000ULL
27#define TAISHAN_FLASH_ADDR 0x00000001fc000000ULL
28#define TAISHAN_FLASH_SIZE 0x4000000
29
30/*
31 * Serial port defines
32 */
33#define RS_TABLE_SIZE 2
34
35/* head_44x.S created UART mapping, used before early_serial_setup.
36 * We cannot use default OpenBIOS UART mappings because they
37 * don't work for configurations with more than 512M RAM. --ebs
38 */
39#define UART0_IO_BASE 0xF0000200
40#define UART1_IO_BASE 0xF0000300
41
42#define BASE_BAUD 11059200/16
43#define STD_UART_OP(num) \
44 { 0, BASE_BAUD, 0, UART##num##_INT, \
45 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
46 iomem_base: (void*)UART##num##_IO_BASE, \
47 io_type: SERIAL_IO_MEM},
48
49#define SERIAL_PORT_DFNS \
50 STD_UART_OP(0) \
51 STD_UART_OP(1)
52
53/* PCI support */
54#define TAISHAN_PCI_LOWER_IO 0x00000000
55#define TAISHAN_PCI_UPPER_IO 0x0000ffff
56#define TAISHAN_PCI_LOWER_MEM 0x80000000
57#define TAISHAN_PCI_UPPER_MEM 0xffffefff
58
59#define TAISHAN_PCI_CFGA_PLB32 0x0ec00000
60#define TAISHAN_PCI_CFGD_PLB32 0x0ec00004
61
62#define TAISHAN_PCI_IO_BASE 0x0000000208000000ULL
63#define TAISHAN_PCI_IO_SIZE 0x00010000
64#define TAISHAN_PCI_MEM_OFFSET 0x00000000
65
66#endif /* __ASM_TAISHAN_H__ */
67#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
deleted file mode 100644
index 738280420be5..000000000000
--- a/arch/ppc/platforms/4xx/virtex.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Basic Virtex platform defines, included by <asm/ibm4xx.h>
3 *
4 * 2005-2007 (c) Secret Lab Technologies Ltd.
5 * 2002-2004 (c) MontaVista Software, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_VIRTEX_H__
14#define __ASM_VIRTEX_H__
15
16#include <asm/ibm405.h>
17#include <asm/ppcboot.h>
18
19/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
20#if !defined(BASE_BAUD)
21 #define BASE_BAUD (0) /* dummy value; not used */
22#endif
23
24#ifndef __ASSEMBLY__
25extern const char* virtex_machine_name;
26#define PPC4xx_MACHINE_NAME (virtex_machine_name)
27#endif /* !__ASSEMBLY__ */
28
29/* We don't need anything mapped. Size of zero will accomplish that. */
30#define PPC4xx_ONB_IO_PADDR 0u
31#define PPC4xx_ONB_IO_VADDR 0u
32#define PPC4xx_ONB_IO_SIZE 0u
33
34#endif /* __ASM_VIRTEX_H__ */
35#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
deleted file mode 100644
index 2f9772340854..000000000000
--- a/arch/ppc/platforms/4xx/walnut.c
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * Architecture- / platform-specific boot-time initialization code for
3 * IBM PowerPC 4xx based boards. Adapted from original
4 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
5 * <dan@net4x.com>.
6 *
7 * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
8 *
9 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/init.h>
15#include <linux/smp.h>
16#include <linux/threads.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/pci.h>
20#include <linux/rtc.h>
21
22#include <asm/system.h>
23#include <asm/pci-bridge.h>
24#include <asm/machdep.h>
25#include <asm/page.h>
26#include <asm/time.h>
27#include <asm/io.h>
28#include <asm/ocp.h>
29#include <asm/ibm_ocp_pci.h>
30#include <asm/todc.h>
31
32#undef DEBUG
33
34#ifdef DEBUG
35#define DBG(x...) printk(x)
36#else
37#define DBG(x...)
38#endif
39
40void *kb_cs;
41void *kb_data;
42void *walnut_rtc_base;
43
44/* Some IRQs unique to Walnut.
45 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
46 */
47int __init
48ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
49{
50 static char pci_irq_table[][4] =
51 /*
52 * PCI IDSEL/INTPIN->INTLINE
53 * A B C D
54 */
55 {
56 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
57 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
58 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
59 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
60 };
61
62 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
63 return PCI_IRQ_TABLE_LOOKUP;
64};
65
66void __init
67walnut_setup_arch(void)
68{
69
70 void *fpga_brdc;
71 unsigned char fpga_brdc_data;
72 void *fpga_enable;
73 void *fpga_polarity;
74 void *fpga_status;
75 void *fpga_trigger;
76
77 ppc4xx_setup_arch();
78
79 ibm_ocp_set_emac(0, 0);
80
81 kb_data = ioremap(WALNUT_PS2_BASE, 8);
82 if (!kb_data) {
83 printk(KERN_CRIT
84 "walnut_setup_arch() kb_data ioremap failed\n");
85 return;
86 }
87
88 kb_cs = kb_data + 1;
89
90 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
91 if (!fpga_status) {
92 printk(KERN_CRIT
93 "walnut_setup_arch() fpga_status ioremap failed\n");
94 return;
95 }
96
97 fpga_enable = fpga_status + 1;
98 fpga_polarity = fpga_status + 2;
99 fpga_trigger = fpga_status + 3;
100 fpga_brdc = fpga_status + 4;
101
102 /* split the keyboard and mouse interrupts */
103 fpga_brdc_data = readb(fpga_brdc);
104 fpga_brdc_data |= 0x80;
105 writeb(fpga_brdc_data, fpga_brdc);
106
107 writeb(0x3, fpga_enable);
108
109 writeb(0x3, fpga_polarity);
110
111 writeb(0x3, fpga_trigger);
112
113 /* RTC step for the walnut */
114 walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
115 TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
116 walnut_rtc_base, 8);
117 /* Identify the system */
118 printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
119}
120
121void __init
122bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
123{
124#ifdef CONFIG_PCI
125 unsigned int bar_response, bar;
126 /*
127 * Expected PCI mapping:
128 *
129 * PLB addr PCI memory addr
130 * --------------------- ---------------------
131 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
132 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
133 *
134 * PLB addr PCI io addr
135 * --------------------- ---------------------
136 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
137 *
138 * The following code is simplified by assuming that the bootrom
139 * has been well behaved in following this mapping.
140 */
141
142#ifdef DEBUG
143 int i;
144
145 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
146 printk("PCI bridge regs before fixup \n");
147 for (i = 0; i <= 3; i++) {
148 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
149 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
150 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
151 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
152 }
153 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
154 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
155 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
156 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
157
158#endif
159
160 /* added for IBM boot rom version 1.15 bios bar changes -AK */
161
162 /* Disable region first */
163 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
164 /* PLB starting addr, PCI: 0x80000000 */
165 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
166 /* PCI start addr, 0x80000000 */
167 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
168 /* 512MB range of PLB to PCI */
169 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
170 /* Enable no pre-fetch, enable region */
171 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
172 (PPC405_PCI_UPPER_MEM -
173 PPC405_PCI_MEM_BASE)) | 0x01));
174
175 /* Disable region one */
176 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
177 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
178 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
179 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
180 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
181 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
182
183 /* Disable region two */
184 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
185 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
186 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
187 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
188 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
189 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
190
191 /* Zero config bars */
192 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
193 early_write_config_dword(hose, hose->first_busno,
194 PCI_FUNC(hose->first_busno), bar,
195 0x00000000);
196 early_read_config_dword(hose, hose->first_busno,
197 PCI_FUNC(hose->first_busno), bar,
198 &bar_response);
199 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
200 hose->first_busno, PCI_SLOT(hose->first_busno),
201 PCI_FUNC(hose->first_busno), bar, bar_response);
202 }
203 /* end work around */
204
205#ifdef DEBUG
206 printk("PCI bridge regs after fixup \n");
207 for (i = 0; i <= 3; i++) {
208 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
209 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
210 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
211 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
212 }
213 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
214 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
215 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
216 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
217
218#endif
219#endif
220}
221
222void __init
223walnut_map_io(void)
224{
225 ppc4xx_map_io();
226 io_block_mapping(WALNUT_RTC_VADDR,
227 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
228}
229
230void __init
231platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
232 unsigned long r6, unsigned long r7)
233{
234 ppc4xx_init(r3, r4, r5, r6, r7);
235
236 ppc_md.setup_arch = walnut_setup_arch;
237 ppc_md.setup_io_mappings = walnut_map_io;
238
239#ifdef CONFIG_GEN_RTC
240 ppc_md.time_init = todc_time_init;
241 ppc_md.set_rtc_time = todc_set_rtc_time;
242 ppc_md.get_rtc_time = todc_get_rtc_time;
243 ppc_md.nvram_read_val = todc_direct_read_val;
244 ppc_md.nvram_write_val = todc_direct_write_val;
245#endif
246}
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
deleted file mode 100644
index d9c4eb788940..000000000000
--- a/arch/ppc/platforms/4xx/walnut.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Walnut board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
9 * Frank Rowand <frank_rowand@mvista.com>
10 * Debbie Chu <debbie_chu@mvista.com>
11 * 2000 (c) MontaVista, Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#ifdef __KERNEL__
21#ifndef __ASM_WALNUT_H__
22#define __ASM_WALNUT_H__
23
24#include <platforms/4xx/ibm405gp.h>
25#include <asm/ppcboot.h>
26
27/* Memory map for the IBM "Walnut" 405GP evaluation board.
28 * Generic 4xx plus RTC.
29 */
30
31#define WALNUT_RTC_PADDR ((uint)0xf0000000)
32#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
33#define WALNUT_RTC_SIZE ((uint)8*1024)
34
35#define BASE_BAUD 691200
36
37#define WALNUT_PS2_BASE 0xF0100000
38
39/* Flash */
40#define PPC40x_FPGA_BASE 0xF0300000
41#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
42#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
43#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
44#define PPC40x_FLASH_LOW 0xFFF00000
45#define PPC40x_FLASH_HIGH 0xFFF80000
46#define PPC40x_FLASH_SIZE 0x80000
47#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE
48
49#define PPC4xx_MACHINE_NAME "IBM Walnut"
50
51#endif /* __ASM_WALNUT_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
deleted file mode 100644
index 6e522fefc26f..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Xilinx ML300 evaluation board initialization
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is licensed
9 * "as is" without any warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/tty.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/serialP.h>
19#include <asm/io.h>
20#include <asm/machdep.h>
21
22#include <syslib/gen550.h>
23#include <syslib/virtex_devices.h>
24#include <platforms/4xx/xparameters/xparameters.h>
25
26/*
27 * As an overview of how the following functions (platform_init,
28 * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the
29 * kernel startup procedure, here's a call tree:
30 *
31 * start_here arch/ppc/kernel/head_4xx.S
32 * early_init arch/ppc/kernel/setup.c
33 * machine_init arch/ppc/kernel/setup.c
34 * platform_init this file
35 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
36 * parse_bootinfo
37 * find_bootinfo
38 * "setup some default ppc_md pointers"
39 * MMU_init arch/ppc/mm/init.c
40 * *ppc_md.setup_io_mappings == ml300_map_io this file
41 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
42 * start_kernel init/main.c
43 * setup_arch arch/ppc/kernel/setup.c
44 * #if defined(CONFIG_KGDB)
45 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
46 * #endif
47 * *ppc_md.setup_arch == ml300_setup_arch this file
48 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
49 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
50 * init_IRQ arch/ppc/kernel/irq.c
51 * *ppc_md.init_IRQ == ml300_init_IRQ this file
52 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
53 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
54 */
55
56const char* virtex_machine_name = "ML300 Reference Design";
57
58#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
59static volatile unsigned *powerdown_base =
60 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
61
62static void
63xilinx_power_off(void)
64{
65 local_irq_disable();
66 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
67 while (1) ;
68}
69#endif
70
71void __init
72ml300_map_io(void)
73{
74 ppc4xx_map_io();
75
76#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
77 powerdown_base = ioremap((unsigned long) powerdown_base,
78 XPAR_POWER_0_POWERDOWN_HIGHADDR -
79 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
80#endif
81}
82
83void __init
84ml300_setup_arch(void)
85{
86 virtex_early_serial_map();
87 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
88
89 /* Identify the system */
90 printk(KERN_INFO "Xilinx ML300 Reference System (Virtex-II Pro)\n");
91}
92
93/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
94void __init
95ml300_init_irq(void)
96{
97 ppc4xx_init_IRQ();
98}
99
100void __init
101platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
102 unsigned long r6, unsigned long r7)
103{
104 ppc4xx_init(r3, r4, r5, r6, r7);
105
106 ppc_md.setup_arch = ml300_setup_arch;
107 ppc_md.setup_io_mappings = ml300_map_io;
108 ppc_md.init_IRQ = ml300_init_irq;
109
110#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
111 ppc_md.power_off = xilinx_power_off;
112#endif
113
114#ifdef CONFIG_KGDB
115 ppc_md.early_serial_map = virtex_early_serial_map;
116#endif
117}
118
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
deleted file mode 100644
index bc3ace3762e7..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml403.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Xilinx ML403 evaluation board initialization
3 *
4 * Author: Grant Likely <grant.likely@secretlab.ca>
5 *
6 * 2005-2007 (c) Secret Lab Technologies Ltd.
7 * 2002-2004 (c) MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/tty.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/serial_8250.h>
20#include <linux/serialP.h>
21#include <asm/io.h>
22#include <asm/machdep.h>
23
24#include <syslib/gen550.h>
25#include <syslib/virtex_devices.h>
26#include <platforms/4xx/xparameters/xparameters.h>
27
28/*
29 * As an overview of how the following functions (platform_init,
30 * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
31 * kernel startup procedure, here's a call tree:
32 *
33 * start_here arch/ppc/kernel/head_4xx.S
34 * early_init arch/ppc/kernel/setup.c
35 * machine_init arch/ppc/kernel/setup.c
36 * platform_init this file
37 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
38 * parse_bootinfo
39 * find_bootinfo
40 * "setup some default ppc_md pointers"
41 * MMU_init arch/ppc/mm/init.c
42 * *ppc_md.setup_io_mappings == ml403_map_io this file
43 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
44 * start_kernel init/main.c
45 * setup_arch arch/ppc/kernel/setup.c
46 * #if defined(CONFIG_KGDB)
47 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
48 * #endif
49 * *ppc_md.setup_arch == ml403_setup_arch this file
50 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
51 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
52 * init_IRQ arch/ppc/kernel/irq.c
53 * *ppc_md.init_IRQ == ml403_init_IRQ this file
54 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
55 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
56 */
57
58const char* virtex_machine_name = "ML403 Reference Design";
59
60#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
61static volatile unsigned *powerdown_base =
62 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
63
64static void
65xilinx_power_off(void)
66{
67 local_irq_disable();
68 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
69 while (1) ;
70}
71#endif
72
73void __init
74ml403_map_io(void)
75{
76 ppc4xx_map_io();
77
78#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
79 powerdown_base = ioremap((unsigned long) powerdown_base,
80 XPAR_POWER_0_POWERDOWN_HIGHADDR -
81 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
82#endif
83}
84
85void __init
86ml403_setup_arch(void)
87{
88 virtex_early_serial_map();
89 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
90
91 /* Identify the system */
92 printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
93}
94
95/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
96void __init
97ml403_init_irq(void)
98{
99 ppc4xx_init_IRQ();
100}
101
102void __init
103platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
104 unsigned long r6, unsigned long r7)
105{
106 ppc4xx_init(r3, r4, r5, r6, r7);
107
108 ppc_md.setup_arch = ml403_setup_arch;
109 ppc_md.setup_io_mappings = ml403_map_io;
110 ppc_md.init_IRQ = ml403_init_irq;
111
112#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
113 ppc_md.power_off = xilinx_power_off;
114#endif
115
116#ifdef CONFIG_KGDB
117 ppc_md.early_serial_map = virtex_early_serial_map;
118#endif
119}
120
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
deleted file mode 100644
index 650888b00fb0..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/xparameters/xparameters.h
3 *
4 * This file includes the correct xparameters.h for the CONFIG'ed board plus
5 * fixups to translate board specific XPAR values to a common set of names
6 *
7 * Author: MontaVista Software, Inc.
8 * source@mvista.com
9 *
10 * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
11 * of the GNU General Public License version 2. This program is licensed
12 * "as is" without any warranty of any kind, whether express or implied.
13 */
14
15
16#if defined(CONFIG_XILINX_ML300)
17 #include "xparameters_ml300.h"
18 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
19 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
20 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
21 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
22#elif defined(CONFIG_XILINX_ML403)
23 #include "xparameters_ml403.h"
24 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
25 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
26 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
27 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
28#else
29 /* Add other board xparameter includes here before the #else */
30 #error No xparameters_*.h file included
31#endif
32
33#ifndef SERIAL_PORT_DFNS
34 /* zImage serial port definitions */
35 #define RS_TABLE_SIZE 1
36 #define SERIAL_PORT_DFNS { \
37 .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
38 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
39 .flags = ASYNC_BOOT_AUTOCONF, \
40 .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
41 .iomem_reg_shift = 2, \
42 .io_type = SERIAL_IO_MEM, \
43 },
44#endif
45
46/*
47 * A few reasonable defaults for the #defines which could be missing depending
48 * on the IP version or variant (e.g. OPB vs PLB)
49 */
50
51#ifndef XPAR_EMAC_0_CAM_EXIST
52#define XPAR_EMAC_0_CAM_EXIST 0
53#endif
54#ifndef XPAR_EMAC_0_JUMBO_EXIST
55#define XPAR_EMAC_0_JUMBO_EXIST 0
56#endif
57#ifndef XPAR_EMAC_0_TX_DRE_TYPE
58#define XPAR_EMAC_0_TX_DRE_TYPE 0
59#endif
60#ifndef XPAR_EMAC_0_RX_DRE_TYPE
61#define XPAR_EMAC_0_RX_DRE_TYPE 0
62#endif
63#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
64#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
65#endif
66#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
67#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
68#endif
69
70#ifndef XPAR_EMAC_1_CAM_EXIST
71#define XPAR_EMAC_1_CAM_EXIST 0
72#endif
73#ifndef XPAR_EMAC_1_JUMBO_EXIST
74#define XPAR_EMAC_1_JUMBO_EXIST 0
75#endif
76#ifndef XPAR_EMAC_1_TX_DRE_TYPE
77#define XPAR_EMAC_1_TX_DRE_TYPE 0
78#endif
79#ifndef XPAR_EMAC_1_RX_DRE_TYPE
80#define XPAR_EMAC_1_RX_DRE_TYPE 0
81#endif
82#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
83#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
84#endif
85#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
86#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
87#endif
88
89#ifndef XPAR_GPIO_0_IS_DUAL
90#define XPAR_GPIO_0_IS_DUAL 0
91#endif
92#ifndef XPAR_GPIO_1_IS_DUAL
93#define XPAR_GPIO_1_IS_DUAL 0
94#endif
95#ifndef XPAR_GPIO_2_IS_DUAL
96#define XPAR_GPIO_2_IS_DUAL 0
97#endif
98#ifndef XPAR_GPIO_3_IS_DUAL
99#define XPAR_GPIO_3_IS_DUAL 0
100#endif
101#ifndef XPAR_GPIO_4_IS_DUAL
102#define XPAR_GPIO_4_IS_DUAL 0
103#endif
104
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
deleted file mode 100644
index 97e3f4d4bd54..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*******************************************************************
2*
3* Author: Xilinx, Inc.
4*
5*
6* This program is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License as published by the
8* Free Software Foundation; either version 2 of the License, or (at your
9* option) any later version.
10*
11*
12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22* FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25* Xilinx hardware products are not intended for use in life support
26* appliances, devices, or systems. Use in such applications is
27* expressly prohibited.
28*
29*
30* (c) Copyright 2002-2004 Xilinx Inc.
31* All rights reserved.
32*
33*
34* You should have received a copy of the GNU General Public License along
35* with this program; if not, write to the Free Software Foundation, Inc.,
36* 675 Mass Ave, Cambridge, MA 02139, USA.
37*
38* Description: Driver parameters
39*
40*******************************************************************/
41
42#define XPAR_XPCI_NUM_INSTANCES 1
43#define XPAR_XPCI_CLOCK_HZ 33333333
44#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
45#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
46#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
47#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
48#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
49#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
50#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
51#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
52#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
53#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
54
55/******************************************************************/
56
57#define XPAR_XEMAC_NUM_INSTANCES 1
58#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
59#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
60#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
61#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
62#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
63#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
64
65/******************************************************************/
66
67#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
68#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
69#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
70#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
71#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
72#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
73#define XPAR_XGPIO_NUM_INSTANCES 2
74
75/******************************************************************/
76
77#define XPAR_XIIC_NUM_INSTANCES 1
78#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
79#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
80#define XPAR_OPB_IIC_0_DEVICE_ID 0
81#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
82
83/******************************************************************/
84
85#define XPAR_XUARTNS550_NUM_INSTANCES 2
86#define XPAR_XUARTNS550_CLOCK_HZ 100000000
87#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
88#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
89#define XPAR_OPB_UART16550_0_DEVICE_ID 0
90#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
91#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
92#define XPAR_OPB_UART16550_1_DEVICE_ID 1
93
94/******************************************************************/
95
96#define XPAR_XSPI_NUM_INSTANCES 1
97#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
98#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
99#define XPAR_OPB_SPI_0_DEVICE_ID 0
100#define XPAR_OPB_SPI_0_FIFO_EXIST 1
101#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
102#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
103
104/******************************************************************/
105
106#define XPAR_XPS2_NUM_INSTANCES 2
107#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
108#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
109#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
110#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
111#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
112#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
113
114/******************************************************************/
115
116#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
117#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
118#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
119#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
120
121/******************************************************************/
122
123#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
124#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
125#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
126#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
127#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
128#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
129
130/******************************************************************/
131
132#define XPAR_XINTC_HAS_IPR 1
133#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
134#define XPAR_XINTC_USE_DCR 0
135#define XPAR_XINTC_NUM_INSTANCES 1
136#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
137#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
138#define XPAR_DCR_INTC_0_DEVICE_ID 0
139#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
140
141/******************************************************************/
142
143#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
144#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
145#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
146#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
147#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
148#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
149#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
150#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
151#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
152#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
153#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
154#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
155#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
156#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
157#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
158#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
159#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
160#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
161
162/******************************************************************/
163
164#define XPAR_XTFT_NUM_INSTANCES 1
165#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
166#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
167#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
168
169/******************************************************************/
170
171#define XPAR_XSYSACE_MEM_WIDTH 8
172#define XPAR_XSYSACE_NUM_INSTANCES 1
173#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
174#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
175#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
176#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
177
178/******************************************************************/
179
180#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
181
182/******************************************************************/
183
184/******************************************************************/
185
186/* Linux Redefines */
187
188/******************************************************************/
189
190#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
191#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
192#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
193#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
194#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
195#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
196#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
197#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
198
199/******************************************************************/
200
201#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
202#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
203#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
204#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
205#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
206#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
207
208/******************************************************************/
209
210#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
211#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
212#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
213#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
214
215/******************************************************************/
216
217#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
218#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
219#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
220
221/******************************************************************/
222
223#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
224#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
225#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
226#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
227
228/******************************************************************/
229
230#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
231#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
232#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
233#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
234#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
235#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
236#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
237#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
238#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
239#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
240#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
241#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
242#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
243
244/******************************************************************/
245
246#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
247#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
248#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
249#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
250#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
251#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
252
253/******************************************************************/
254
255#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
256#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
257#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
258
259/******************************************************************/
260
261#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
262#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
263#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
264
265/******************************************************************/
266
267#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
268
269/******************************************************************/
270
271#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
272#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
273#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
274#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
275#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
276#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
277#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
278#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
279#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
280#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
281#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
282
283/******************************************************************/
284
285#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
286#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
287#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
288#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
289#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
290#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
291
292/******************************************************************/
293
294#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
295#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
296#define XPAR_DDR_0_SIZE 0x08000000
297
298/******************************************************************/
299
300#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
301#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
302#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
303
304/******************************************************************/
305
306#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
307#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
308#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
309
310/******************************************************************/
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
deleted file mode 100644
index 5cacdcb3964d..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
+++ /dev/null
@@ -1,243 +0,0 @@
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
6* DO NOT EDIT.
7*
8* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
9*
10* Description: Driver parameters
11*
12*******************************************************************/
13
14#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
15#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
16
17/******************************************************************/
18
19#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
20#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
21#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
22#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
23#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
24#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
25#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
26#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
27#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
28#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
29
30/******************************************************************/
31
32#define XPAR_XEMAC_NUM_INSTANCES 1
33#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
34#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
35#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
36#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
37#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
38#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
39
40/******************************************************************/
41
42#define XPAR_XUARTNS550_NUM_INSTANCES 1
43#define XPAR_XUARTNS550_CLOCK_HZ 100000000
44#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
45#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
46#define XPAR_OPB_UART16550_0_DEVICE_ID 0
47
48/******************************************************************/
49
50#define XPAR_XGPIO_NUM_INSTANCES 3
51#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
52#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
53#define XPAR_OPB_GPIO_0_DEVICE_ID 0
54#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
55#define XPAR_OPB_GPIO_0_IS_DUAL 1
56#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
57#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
58#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
59#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
60#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
61#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
62#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
63#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
64#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
65#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
66
67/******************************************************************/
68
69#define XPAR_XPS2_NUM_INSTANCES 2
70#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
71#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
72#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
73#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
74#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
75#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
76
77/******************************************************************/
78
79#define XPAR_XIIC_NUM_INSTANCES 1
80#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
81#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
82#define XPAR_OPB_IIC_0_DEVICE_ID 0
83#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
84#define XPAR_OPB_IIC_0_GPO_WIDTH 1
85
86/******************************************************************/
87
88#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
89#define XPAR_XINTC_HAS_IPR 1
90#define XPAR_XINTC_USE_DCR 0
91#define XPAR_XINTC_NUM_INSTANCES 1
92#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
93#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
94#define XPAR_OPB_INTC_0_DEVICE_ID 0
95#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
96
97/******************************************************************/
98
99#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
100#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
101#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
102#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
103#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
104#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
105#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
106#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
107#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
108#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
109#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
110#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
111#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
112#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
113#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
114#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
115#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
116#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
117#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
118#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
119#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
120#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
121#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
122
123/******************************************************************/
124
125#define XPAR_XTFT_NUM_INSTANCES 1
126#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
127#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
128#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
129
130/******************************************************************/
131
132#define XPAR_XSYSACE_MEM_WIDTH 16
133#define XPAR_XSYSACE_NUM_INSTANCES 1
134#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
135#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
136#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
137#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
138
139/******************************************************************/
140
141#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
142
143/******************************************************************/
144
145
146/******************************************************************/
147
148/* Linux Redefines */
149
150/******************************************************************/
151
152#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
153#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
154#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
155#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
156
157/******************************************************************/
158
159#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
160#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
161#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
162#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
163
164/******************************************************************/
165
166#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
167#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
168#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
169#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
170#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
171#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
172
173/******************************************************************/
174
175#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
176
177/******************************************************************/
178
179#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
180#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
181#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
182#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
183#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
184#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
185
186/******************************************************************/
187
188#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
189#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
190#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
191#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
192#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
193#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
194#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
195#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
196#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
197#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
198#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
199#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
200#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
201#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
202#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
203
204/******************************************************************/
205
206#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
207#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
208#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
209#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
210#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
211#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
212
213/******************************************************************/
214
215#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
216#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
217#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
218
219/******************************************************************/
220
221#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
222#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
223#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
224#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
225
226/******************************************************************/
227
228#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
229#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
230#define XPAR_DDR_0_SIZE 0x4000000
231
232/******************************************************************/
233
234#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
235#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
236#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
237
238/******************************************************************/
239
240#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
241
242/******************************************************************/
243
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
deleted file mode 100644
index f6cfd44281fc..000000000000
--- a/arch/ppc/platforms/4xx/yucca.c
+++ /dev/null
@@ -1,393 +0,0 @@
1/*
2 * Yucca board specific routines
3 *
4 * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/types.h>
23#include <linux/major.h>
24#include <linux/blkdev.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/initrd.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/tty.h>
31#include <linux/serial.h>
32#include <linux/serial_core.h>
33#include <linux/serial_8250.h>
34
35#include <asm/system.h>
36#include <asm/pgtable.h>
37#include <asm/page.h>
38#include <asm/dma.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/ocp.h>
42#include <asm/pci-bridge.h>
43#include <asm/time.h>
44#include <asm/todc.h>
45#include <asm/bootinfo.h>
46#include <asm/ppc4xx_pic.h>
47#include <asm/ppcboot.h>
48
49#include <syslib/ibm44x_common.h>
50#include <syslib/ibm440gx_common.h>
51#include <syslib/ibm440sp_common.h>
52#include <syslib/ppc440spe_pcie.h>
53
54extern bd_t __res;
55
56static struct ibm44x_clocks clocks __initdata;
57
58static void __init
59yucca_calibrate_decr(void)
60{
61 unsigned int freq;
62
63 if (mfspr(SPRN_CCR1) & CCR1_TCS)
64 freq = YUCCA_TMR_CLK;
65 else
66 freq = clocks.cpu;
67
68 ibm44x_calibrate_decr(freq);
69}
70
71static int
72yucca_show_cpuinfo(struct seq_file *m)
73{
74 seq_printf(m, "vendor\t\t: AMCC\n");
75 seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
76
77 return 0;
78}
79
80static enum {
81 HOSE_UNKNOWN,
82 HOSE_PCIX,
83 HOSE_PCIE0,
84 HOSE_PCIE1,
85 HOSE_PCIE2
86} hose_type[4];
87
88static inline int
89yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
90{
91 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
92
93 if (hose_type[hose->index] == HOSE_PCIX) {
94 static char pci_irq_table[][4] =
95 /*
96 * PCI IDSEL/INTPIN->INTLINE
97 * A B C D
98 */
99 {
100 { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
101 };
102 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104 } else if (hose_type[hose->index] == HOSE_PCIE0) {
105 static char pci_irq_table[][4] =
106 /*
107 * PCI IDSEL/INTPIN->INTLINE
108 * A B C D
109 */
110 {
111 { 96, 97, 98, 99 },
112 };
113 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
114 return PCI_IRQ_TABLE_LOOKUP;
115 } else if (hose_type[hose->index] == HOSE_PCIE1) {
116 static char pci_irq_table[][4] =
117 /*
118 * PCI IDSEL/INTPIN->INTLINE
119 * A B C D
120 */
121 {
122 { 100, 101, 102, 103 },
123 };
124 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
125 return PCI_IRQ_TABLE_LOOKUP;
126 } else if (hose_type[hose->index] == HOSE_PCIE2) {
127 static char pci_irq_table[][4] =
128 /*
129 * PCI IDSEL/INTPIN->INTLINE
130 * A B C D
131 */
132 {
133 { 104, 105, 106, 107 },
134 };
135 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
136 return PCI_IRQ_TABLE_LOOKUP;
137 }
138 return -1;
139}
140
141static void __init yucca_set_emacdata(void)
142{
143 struct ocp_def *def;
144 struct ocp_func_emac_data *emacdata;
145
146 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
147 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
148 emacdata = def->additions;
149 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
150 emacdata->phy_mode = PHY_MODE_GMII;
151 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
152}
153
154static int __init yucca_pcie_card_present(int port)
155{
156 void __iomem *pcie_fpga_base;
157 u16 reg;
158
159 pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
160 reg = in_be16(pcie_fpga_base + FPGA_REG1C);
161 iounmap(pcie_fpga_base);
162
163 switch(port) {
164 case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
165 case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
166 case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
167 default: return 0;
168 }
169}
170
171/*
172 * For the given slot, set rootpoint mode, send power to the slot,
173 * turn on the green LED and turn off the yellow LED, enable the clock
174 * and turn off reset.
175 */
176static void __init yucca_setup_pcie_fpga_rootpoint(int port)
177{
178 void __iomem *pcie_reg_fpga_base;
179 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
180
181 pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
182
183 switch(port) {
184 case 0:
185 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
186 endpoint = 0;
187 power = FPGA_REG1A_PE0_PWRON;
188 green_led = FPGA_REG1A_PE0_GLED;
189 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
190 yellow_led = FPGA_REG1A_PE0_YLED;
191 reset_off = FPGA_REG1C_PE0_PERST;
192 break;
193 case 1:
194 rootpoint = 0;
195 endpoint = FPGA_REG1C_PE1_ENDPOINT;
196 power = FPGA_REG1A_PE1_PWRON;
197 green_led = FPGA_REG1A_PE1_GLED;
198 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
199 yellow_led = FPGA_REG1A_PE1_YLED;
200 reset_off = FPGA_REG1C_PE1_PERST;
201 break;
202 case 2:
203 rootpoint = 0;
204 endpoint = FPGA_REG1C_PE2_ENDPOINT;
205 power = FPGA_REG1A_PE2_PWRON;
206 green_led = FPGA_REG1A_PE2_GLED;
207 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
208 yellow_led = FPGA_REG1A_PE2_YLED;
209 reset_off = FPGA_REG1C_PE2_PERST;
210 break;
211
212 default:
213 iounmap(pcie_reg_fpga_base);
214 return;
215 }
216
217 out_be16(pcie_reg_fpga_base + FPGA_REG1A,
218 ~(power | clock | green_led) &
219 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
220 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
221 ~(endpoint | reset_off) &
222 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
223
224 /*
225 * Leave device in reset for a while after powering on the
226 * slot to give it a chance to initialize.
227 */
228 mdelay(250);
229
230 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
231 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
232
233 iounmap(pcie_reg_fpga_base);
234}
235
236static void __init
237yucca_setup_hoses(void)
238{
239 struct pci_controller *hose;
240 char name[20];
241 int i;
242
243 if (0 && ppc440spe_init_pcie()) {
244 printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
245 return;
246 }
247
248 for (i = 0; i <= 2; ++i) {
249 if (!yucca_pcie_card_present(i))
250 continue;
251
252 printk(KERN_INFO "PCIE%d: card present\n", i);
253 yucca_setup_pcie_fpga_rootpoint(i);
254 if (ppc440spe_init_pcie_rootport(i)) {
255 printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
256 continue;
257 }
258
259 hose = pcibios_alloc_controller();
260 if (!hose)
261 return;
262
263 sprintf(name, "PCIE%d host bridge", i);
264 pci_init_resource(&hose->io_resource,
265 YUCCA_PCIX_LOWER_IO,
266 YUCCA_PCIX_UPPER_IO,
267 IORESOURCE_IO,
268 name);
269
270 hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
271 i * YUCCA_PCIE_MEM_SIZE;
272 hose->mem_space.end = hose->mem_space.start +
273 YUCCA_PCIE_MEM_SIZE - 1;
274
275 pci_init_resource(&hose->mem_resources[0],
276 hose->mem_space.start,
277 hose->mem_space.end,
278 IORESOURCE_MEM,
279 name);
280
281 hose->first_busno = 0;
282 hose->last_busno = 15;
283 hose_type[hose->index] = HOSE_PCIE0 + i;
284
285 ppc440spe_setup_pcie(hose, i);
286 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
287 }
288
289 ppc_md.pci_swizzle = common_swizzle;
290 ppc_md.pci_map_irq = yucca_map_irq;
291}
292
293TODC_ALLOC();
294
295static void __init
296yucca_early_serial_map(void)
297{
298 struct uart_port port;
299
300 /* Setup ioremapped serial port access */
301 memset(&port, 0, sizeof(port));
302 port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
303 port.irq = UART0_INT;
304 port.uartclk = clocks.uart0;
305 port.regshift = 0;
306 port.iotype = UPIO_MEM;
307 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
308 port.line = 0;
309
310 if (early_serial_setup(&port) != 0) {
311 printk("Early serial init of port 0 failed\n");
312 }
313
314 port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
315 port.irq = UART1_INT;
316 port.uartclk = clocks.uart1;
317 port.line = 1;
318
319 if (early_serial_setup(&port) != 0) {
320 printk("Early serial init of port 1 failed\n");
321 }
322
323 port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
324 port.irq = UART2_INT;
325 port.uartclk = BASE_BAUD;
326 port.line = 2;
327
328 if (early_serial_setup(&port) != 0) {
329 printk("Early serial init of port 2 failed\n");
330 }
331}
332
333static void __init
334yucca_setup_arch(void)
335{
336 yucca_set_emacdata();
337
338#if !defined(CONFIG_BDI_SWITCH)
339 /*
340 * The Abatron BDI JTAG debugger does not tolerate others
341 * mucking with the debug registers.
342 */
343 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
344#endif
345
346 /*
347 * Determine various clocks.
348 * To be completely correct we should get SysClk
349 * from FPGA, because it can be changed by on-board switches
350 * --ebs
351 */
352 /* 440GX and 440SPe clocking is the same - rd */
353 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
354 ocp_sys_info.opb_bus_freq = clocks.opb;
355
356 /* init to some ~sane value until calibrate_delay() runs */
357 loops_per_jiffy = 50000000/HZ;
358
359 /* Setup PCIXn host bridges */
360 yucca_setup_hoses();
361
362#ifdef CONFIG_BLK_DEV_INITRD
363 if (initrd_start)
364 ROOT_DEV = Root_RAM0;
365 else
366#endif
367#ifdef CONFIG_ROOT_NFS
368 ROOT_DEV = Root_NFS;
369#else
370 ROOT_DEV = Root_HDA1;
371#endif
372
373 yucca_early_serial_map();
374
375 /* Identify the system */
376 printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
377}
378
379void __init platform_init(unsigned long r3, unsigned long r4,
380 unsigned long r5, unsigned long r6, unsigned long r7)
381{
382 ibm44x_platform_init(r3, r4, r5, r6, r7);
383
384 ppc_md.setup_arch = yucca_setup_arch;
385 ppc_md.show_cpuinfo = yucca_show_cpuinfo;
386 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
387 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
388
389 ppc_md.calibrate_decr = yucca_calibrate_decr;
390#ifdef CONFIG_KGDB
391 ppc_md.early_serial_map = yucca_early_serial_map;
392#endif
393}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
deleted file mode 100644
index bc9684e66a84..000000000000
--- a/arch/ppc/platforms/4xx/yucca.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * Yucca board definitions
3 *
4 * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_YUCCA_H__
18#define __ASM_YUCCA_H__
19
20#include <platforms/4xx/ppc440spe.h>
21
22/* F/W TLB mapping used in bootloader glue to reset EMAC */
23#define PPC44x_EMAC0_MR0 0xa0000800
24
25/* Location of MAC addresses in PIBS image */
26#define PIBS_FLASH_BASE 0xffe00000
27#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
28
29/* External timer clock frequency */
30#define YUCCA_TMR_CLK 25000000
31
32/*
33 * FPGA registers
34 */
35#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
36#define YUCCA_FPGA_REG_SIZE 0x24
37
38#define FPGA_REG1A 0x1a
39
40#define FPGA_REG1A_PE0_GLED 0x8000
41#define FPGA_REG1A_PE1_GLED 0x4000
42#define FPGA_REG1A_PE2_GLED 0x2000
43#define FPGA_REG1A_PE0_YLED 0x1000
44#define FPGA_REG1A_PE1_YLED 0x0800
45#define FPGA_REG1A_PE2_YLED 0x0400
46#define FPGA_REG1A_PE0_PWRON 0x0200
47#define FPGA_REG1A_PE1_PWRON 0x0100
48#define FPGA_REG1A_PE2_PWRON 0x0080
49#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
50#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
51#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
52#define FPGA_REG1A_PE_SPREAD0 0x0008
53#define FPGA_REG1A_PE_SPREAD1 0x0004
54#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
55#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
56
57#define FPGA_REG1C 0x1c
58
59#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
60#define FPGA_REG1C_PE1_ENDPOINT 0x4000
61#define FPGA_REG1C_PE2_ENDPOINT 0x2000
62#define FPGA_REG1C_PE0_PRSNT 0x1000
63#define FPGA_REG1C_PE1_PRSNT 0x0800
64#define FPGA_REG1C_PE2_PRSNT 0x0400
65#define FPGA_REG1C_PE0_WAKE 0x0080
66#define FPGA_REG1C_PE1_WAKE 0x0040
67#define FPGA_REG1C_PE2_WAKE 0x0020
68#define FPGA_REG1C_PE0_PERST 0x0010
69#define FPGA_REG1C_PE1_PERST 0x0008
70#define FPGA_REG1C_PE2_PERST 0x0004
71
72/*
73 * Serial port defines
74 */
75#define RS_TABLE_SIZE 3
76
77/* PIBS defined UART mappings, used before early_serial_setup */
78#define UART0_IO_BASE 0xa0000200
79#define UART1_IO_BASE 0xa0000300
80#define UART2_IO_BASE 0xa0000600
81
82#define BASE_BAUD 11059200
83#define STD_UART_OP(num) \
84 { 0, BASE_BAUD, 0, UART##num##_INT, \
85 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
86 iomem_base: (void*)UART##num##_IO_BASE, \
87 io_type: SERIAL_IO_MEM},
88
89#define SERIAL_PORT_DFNS \
90 STD_UART_OP(0) \
91 STD_UART_OP(1) \
92 STD_UART_OP(2)
93
94/* PCI support */
95#define YUCCA_PCIX_LOWER_IO 0x00000000
96#define YUCCA_PCIX_UPPER_IO 0x0000ffff
97#define YUCCA_PCIX_LOWER_MEM 0x80000000
98#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
99#define YUCCA_PCIE_LOWER_MEM 0x90000000
100#define YUCCA_PCIE_MEM_SIZE 0x10000000
101
102#define YUCCA_PCIX_MEM_SIZE 0x10000000
103#define YUCCA_PCIX_MEM_OFFSET 0x00000000
104#define YUCCA_PCIE_MEM_SIZE 0x10000000
105#define YUCCA_PCIE_MEM_OFFSET 0x00000000
106
107#endif /* __ASM_YUCCA_H__ */
108#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 21:24:47 -0500