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-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h235
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diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
deleted file mode 100644
index 31a08abaa4a2..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.h
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@@ -1,235 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMSTB4_H__
12#define __ASM_IBMSTB4_H__
13
14
15/* serial port defines */
16#define STB04xxx_IO_BASE ((uint)0xe0000000)
17#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
18#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
19#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
20#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
21
22/*
23 * map STB04xxx internal i/o address (0x400x00xx) to an address
24 * which is below the 2GB limit...
25 *
26 * 4000 000x uart1 -> 0xe000 000x
27 * 4001 00xx ppu
28 * 4002 00xx smart card
29 * 4003 000x iic
30 * 4004 000x uart0
31 * 4005 0xxx timer
32 * 4006 00xx gpio
33 * 4007 00xx smart card
34 * 400b 000x iic
35 * 400c 000x scp
36 * 400d 000x modem
37 * 400e 000x uart2
38*/
39#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
40
41#define RS_TABLE_SIZE 3
42#define UART0_INT 20
43
44#ifdef __BOOTER__
45#define UART0_IO_BASE 0x40040000
46#else
47#define UART0_IO_BASE 0xe0040000
48#endif
49
50#define UART1_INT 21
51
52#ifdef __BOOTER__
53#define UART1_IO_BASE 0x40000000
54#else
55#define UART1_IO_BASE 0xe0000000
56#endif
57
58#define UART2_INT 31
59#ifdef __BOOTER__
60#define UART2_IO_BASE 0x400e0000
61#else
62#define UART2_IO_BASE 0xe00e0000
63#endif
64
65#define IDE0_BASE 0x400F0000
66#define IDE0_SIZE 0x200
67#define IDE0_IRQ 25
68#define IIC0_BASE 0x40030000
69#define IIC1_BASE 0x400b0000
70#define OPB0_BASE 0x40000000
71#define GPIO0_BASE 0x40060000
72
73#define USB0_BASE 0x40010000
74#define USB0_SIZE 0xA0
75#define USB0_IRQ 18
76
77#define IIC_NUMS 2
78#define UART_NUMS 3
79#define IIC0_IRQ 9
80#define IIC1_IRQ 10
81#define IIC_OWN 0x55
82#define IIC_CLOCK 50
83
84#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
85
86#define STD_UART_OP(num) \
87 { 0, BASE_BAUD, 0, UART##num##_INT, \
88 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
89 iomem_base: (u8 *)UART##num##_IO_BASE, \
90 io_type: SERIAL_IO_MEM},
91
92#if defined(CONFIG_UART0_TTYS0)
93#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
94#define SERIAL_PORT_DFNS \
95 STD_UART_OP(0) \
96 STD_UART_OP(1) \
97 STD_UART_OP(2)
98#endif
99
100#if defined(CONFIG_UART0_TTYS1)
101#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
102#define SERIAL_PORT_DFNS \
103 STD_UART_OP(1) \
104 STD_UART_OP(0) \
105 STD_UART_OP(2)
106#endif
107
108#if defined(CONFIG_UART0_TTYS2)
109#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
110#define SERIAL_PORT_DFNS \
111 STD_UART_OP(2) \
112 STD_UART_OP(0) \
113 STD_UART_OP(1)
114#endif
115
116#define DCRN_BE_BASE 0x090
117#define DCRN_DMA0_BASE 0x0C0
118#define DCRN_DMA1_BASE 0x0C8
119#define DCRN_DMA2_BASE 0x0D0
120#define DCRN_DMA3_BASE 0x0D8
121#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
122#define DCRN_DMASR_BASE 0x0E0
123#define DCRN_PLB0_BASE 0x054
124#define DCRN_PLB1_BASE 0x064
125#define DCRN_POB0_BASE 0x0B0
126#define DCRN_SCCR_BASE 0x120
127#define DCRN_UIC0_BASE 0x040
128#define DCRN_BE_BASE 0x090
129#define DCRN_DMA0_BASE 0x0C0
130#define DCRN_DMA1_BASE 0x0C8
131#define DCRN_DMA2_BASE 0x0D0
132#define DCRN_DMA3_BASE 0x0D8
133#define DCRN_CIC_BASE 0x030
134#define DCRN_DMASR_BASE 0x0E0
135#define DCRN_EBIMC_BASE 0x070
136#define DCRN_DCRX_BASE 0x020
137#define DCRN_CPMFR_BASE 0x102
138#define DCRN_SCCR_BASE 0x120
139#define UIC0 DCRN_UIC0_BASE
140
141#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
142#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
143#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
144#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
145#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
146#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
147#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
148#define IBM_CPM_DMA 0x01000000 /* DMA controller */
149#define IBM_CPM_DMA1 0x00800000 /* reserved */
150#define IBM_CPM_XPT1 0x00400000 /* reserved */
151#define IBM_CPM_XPT2 0x00200000 /* reserved */
152#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
153#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
154#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
155#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
156#define IBM_CPM_VID 0x00010000 /* reserved */
157#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
158#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
159#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
160#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
161#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
162#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
163#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
164#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
165#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
166#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
167#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
168#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
169#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
170#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
171
172#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
173 | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
174 | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
175 | IBM_CPM_XPT27 | IBM_CPM_UIC )
176
177#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
178#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
179/* DCRN_BESR */
180#define BESR_DSES 0x80000000 /* Data-Side Error Status */
181#define BESR_DMES 0x40000000 /* DMA Error Status */
182#define BESR_RWS 0x20000000 /* Read/Write Status */
183#define BESR_ETMASK 0x1C000000 /* Error Type */
184#define ET_PROT 0
185#define ET_PARITY 1
186#define ET_NCFG 2
187#define ET_BUSERR 4
188#define ET_BUSTO 6
189
190#define CHR1_CETE 0x00800000 /* CPU external timer enable */
191#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
192
193#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
194#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
195#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
196#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
197#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
198#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
199#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
200#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
201#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
202
203#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
204#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
205#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
206#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
207#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
208#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
209#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
210#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
211
212#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
213#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
214#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
215#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
216#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
217#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
218#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
219#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
220#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
221#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
222#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
223#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
224#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
225#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
226#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
227#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
228#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
229#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
230#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
231
232#include <asm/ibm405.h>
233
234#endif /* __ASM_IBMSTB4_H__ */
235#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 14:15:36 -0500