aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc/platforms/4xx/ibm405ep.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/ppc/platforms/4xx/ibm405ep.h')
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.h148
1 files changed, 148 insertions, 0 deletions
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
new file mode 100644
index 000000000000..e051e3fe8c63
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405ep.h
@@ -0,0 +1,148 @@
1/*
2 * arch/ppc/platforms/4xx/ibm405ep.h
3 *
4 * IBM PPC 405EP processor defines.
5 *
6 * Author: SAW (IBM), derived from ibm405gp.h.
7 * Maintained by MontaVista Software <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_IBM405EP_H__
17#define __ASM_IBM405EP_H__
18
19#include <linux/config.h>
20
21/* ibm405.h at bottom of this file */
22
23/* PCI
24 * PCI Bridge config reg definitions
25 * see 17-19 of manual
26 */
27
28#define PPC405_PCI_CONFIG_ADDR 0xeec00000
29#define PPC405_PCI_CONFIG_DATA 0xeec00004
30
31#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
32 /* setbat */
33#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
34#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
35#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
36
37#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
38#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
39#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
40#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
41
42#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
43
44#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
45#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
46#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
47#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
48#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
49#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
50#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
51#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
52#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
53#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
54#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
55#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
56
57/* serial port defines */
58#define RS_TABLE_SIZE 2
59
60#define UART0_INT 0
61#define UART1_INT 1
62
63#define PCIL0_BASE 0xEF400000
64#define UART0_IO_BASE 0xEF600300
65#define UART1_IO_BASE 0xEF600400
66#define EMAC0_BASE 0xEF600800
67
68#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
69
70#if defined(CONFIG_UART0_TTYS0)
71#define ACTING_UART0_IO_BASE UART0_IO_BASE
72#define ACTING_UART1_IO_BASE UART1_IO_BASE
73#define ACTING_UART0_INT UART0_INT
74#define ACTING_UART1_INT UART1_INT
75#else
76#define ACTING_UART0_IO_BASE UART1_IO_BASE
77#define ACTING_UART1_IO_BASE UART0_IO_BASE
78#define ACTING_UART0_INT UART1_INT
79#define ACTING_UART1_INT UART0_INT
80#endif
81
82#define STD_UART_OP(num) \
83 { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \
84 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
85 iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \
86 io_type: SERIAL_IO_MEM},
87
88#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE
89#define SERIAL_PORT_DFNS \
90 STD_UART_OP(0) \
91 STD_UART_OP(1)
92
93/* DCR defines */
94#define DCRN_CPMSR_BASE 0x0BA
95#define DCRN_CPMFR_BASE 0x0B9
96
97#define DCRN_CPC0_PLLMR0_BASE 0x0F0
98#define DCRN_CPC0_BOOT_BASE 0x0F1
99#define DCRN_CPC0_CR1_BASE 0x0F2
100#define DCRN_CPC0_EPRCSR_BASE 0x0F3
101#define DCRN_CPC0_PLLMR1_BASE 0x0F4
102#define DCRN_CPC0_UCR_BASE 0x0F5
103#define DCRN_CPC0_UCR_U0DIV 0x07F
104#define DCRN_CPC0_SRR_BASE 0x0F6
105#define DCRN_CPC0_JTAGID_BASE 0x0F7
106#define DCRN_CPC0_SPARE_BASE 0x0F8
107#define DCRN_CPC0_PCI_BASE 0x0F9
108
109
110#define IBM_CPM_GPT 0x80000000 /* GPT interface */
111#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
112#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
113#define IBM_CPM_CPU 0x00008000 /* processor core */
114#define IBM_CPM_EBC 0x00002000 /* EBC controller */
115#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
116#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
117#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
118#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
119#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
120#define IBM_CPM_DMA 0x00000040 /* DMA controller */
121#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
122#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
123#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
124#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
125 | IBM_CPM_OPB | IBM_CPM_EBC \
126 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
127 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405EP_H__ */
148#endif /* __KERNEL__ */