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-rw-r--r--arch/ppc/mm/ppc_mmu.c28
1 files changed, 1 insertions, 27 deletions
diff --git a/arch/ppc/mm/ppc_mmu.c b/arch/ppc/mm/ppc_mmu.c
index 9a381ed5eb21..25bb6f3347c1 100644
--- a/arch/ppc/mm/ppc_mmu.c
+++ b/arch/ppc/mm/ppc_mmu.c
@@ -2,7 +2,7 @@
2 * This file contains the routines for handling the MMU on those 2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the 3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx, 4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * 8260, and POWER3 implementations but excludes the 8xx and 4xx. 5 * 8260, and 83xx implementations but excludes the 8xx and 4xx.
6 * -- paulus 6 * -- paulus
7 * 7 *
8 * Derived from arch/ppc/mm/init.c: 8 * Derived from arch/ppc/mm/init.c:
@@ -42,11 +42,7 @@ unsigned long _SDR1;
42 42
43union ubat { /* BAT register values to be loaded */ 43union ubat { /* BAT register values to be loaded */
44 BAT bat; 44 BAT bat;
45#ifdef CONFIG_PPC64BRIDGE
46 u64 word[2];
47#else
48 u32 word[2]; 45 u32 word[2];
49#endif
50} BATS[4][2]; /* 4 pairs of IBAT, DBAT */ 46} BATS[4][2]; /* 4 pairs of IBAT, DBAT */
51 47
52struct batrange { /* stores address ranges mapped by BATs */ 48struct batrange { /* stores address ranges mapped by BATs */
@@ -83,9 +79,6 @@ unsigned long p_mapped_by_bats(unsigned long pa)
83 79
84unsigned long __init mmu_mapin_ram(void) 80unsigned long __init mmu_mapin_ram(void)
85{ 81{
86#ifdef CONFIG_POWER4
87 return 0;
88#else
89 unsigned long tot, bl, done; 82 unsigned long tot, bl, done;
90 unsigned long max_size = (256<<20); 83 unsigned long max_size = (256<<20);
91 unsigned long align; 84 unsigned long align;
@@ -122,7 +115,6 @@ unsigned long __init mmu_mapin_ram(void)
122 } 115 }
123 116
124 return done; 117 return done;
125#endif
126} 118}
127 119
128/* 120/*
@@ -205,27 +197,10 @@ void __init MMU_init_hw(void)
205 197
206 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105); 198 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
207 199
208#ifdef CONFIG_PPC64BRIDGE
209#define LG_HPTEG_SIZE 7 /* 128 bytes per HPTEG */
210#define SDR1_LOW_BITS (lg_n_hpteg - 11)
211#define MIN_N_HPTEG 2048 /* min 256kB hash table */
212#else
213#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */ 200#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
214#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10) 201#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
215#define MIN_N_HPTEG 1024 /* min 64kB hash table */ 202#define MIN_N_HPTEG 1024 /* min 64kB hash table */
216#endif
217
218#ifdef CONFIG_POWER4
219 /* The hash table has already been allocated and initialized
220 in prom.c */
221 n_hpteg = Hash_size >> LG_HPTEG_SIZE;
222 lg_n_hpteg = __ilog2(n_hpteg);
223
224 /* Remove the hash table from the available memory */
225 if (Hash)
226 reserve_phys_mem(__pa(Hash), Hash_size);
227 203
228#else /* CONFIG_POWER4 */
229 /* 204 /*
230 * Allow 1 HPTE (1/8 HPTEG) for each page of memory. 205 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
231 * This is less than the recommended amount, but then 206 * This is less than the recommended amount, but then
@@ -248,7 +223,6 @@ void __init MMU_init_hw(void)
248 Hash = mem_pieces_find(Hash_size, Hash_size); 223 Hash = mem_pieces_find(Hash_size, Hash_size);
249 cacheable_memzero(Hash, Hash_size); 224 cacheable_memzero(Hash, Hash_size);
250 _SDR1 = __pa(Hash) | SDR1_LOW_BITS; 225 _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
251#endif /* CONFIG_POWER4 */
252 226
253 Hash_end = (PTE *) ((unsigned long)Hash + Hash_size); 227 Hash_end = (PTE *) ((unsigned long)Hash + Hash_size);
254 228