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-rw-r--r--arch/ppc/mm/ppc_mmu.c269
1 files changed, 0 insertions, 269 deletions
diff --git a/arch/ppc/mm/ppc_mmu.c b/arch/ppc/mm/ppc_mmu.c
deleted file mode 100644
index 0c1dc155996a..000000000000
--- a/arch/ppc/mm/ppc_mmu.c
+++ /dev/null
@@ -1,269 +0,0 @@
1/*
2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * and 8260 implementations but excludes the 8xx and 4xx.
6 * -- paulus
7 *
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
14 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
15 *
16 * Derived from "arch/i386/mm/init.c"
17 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/init.h>
29#include <linux/highmem.h>
30
31#include <asm/prom.h>
32#include <asm/mmu.h>
33#include <asm/machdep.h>
34
35#include "mmu_decl.h"
36#include "mem_pieces.h"
37
38PTE *Hash, *Hash_end;
39unsigned long Hash_size, Hash_mask;
40unsigned long _SDR1;
41
42union ubat { /* BAT register values to be loaded */
43 BAT bat;
44 u32 word[2];
45} BATS[4][2]; /* 4 pairs of IBAT, DBAT */
46
47struct batrange { /* stores address ranges mapped by BATs */
48 unsigned long start;
49 unsigned long limit;
50 unsigned long phys;
51} bat_addrs[4];
52
53/*
54 * Return PA for this VA if it is mapped by a BAT, or 0
55 */
56unsigned long v_mapped_by_bats(unsigned long va)
57{
58 int b;
59 for (b = 0; b < 4; ++b)
60 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
61 return bat_addrs[b].phys + (va - bat_addrs[b].start);
62 return 0;
63}
64
65/*
66 * Return VA for a given PA or 0 if not mapped
67 */
68unsigned long p_mapped_by_bats(unsigned long pa)
69{
70 int b;
71 for (b = 0; b < 4; ++b)
72 if (pa >= bat_addrs[b].phys
73 && pa < (bat_addrs[b].limit-bat_addrs[b].start)
74 +bat_addrs[b].phys)
75 return bat_addrs[b].start+(pa-bat_addrs[b].phys);
76 return 0;
77}
78
79unsigned long __init mmu_mapin_ram(void)
80{
81 unsigned long tot, bl, done;
82 unsigned long max_size = (256<<20);
83 unsigned long align;
84
85 if (__map_without_bats)
86 return 0;
87
88 /* Set up BAT2 and if necessary BAT3 to cover RAM. */
89
90 /* Make sure we don't map a block larger than the
91 smallest alignment of the physical address. */
92 /* alignment of PPC_MEMSTART */
93 align = ~(PPC_MEMSTART-1) & PPC_MEMSTART;
94 /* set BAT block size to MIN(max_size, align) */
95 if (align && align < max_size)
96 max_size = align;
97
98 tot = total_lowmem;
99 for (bl = 128<<10; bl < max_size; bl <<= 1) {
100 if (bl * 2 > tot)
101 break;
102 }
103
104 setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
105 done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
106 if ((done < tot) && !bat_addrs[3].limit) {
107 /* use BAT3 to cover a bit more */
108 tot -= done;
109 for (bl = 128<<10; bl < max_size; bl <<= 1)
110 if (bl * 2 > tot)
111 break;
112 setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
113 done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
114 }
115
116 return done;
117}
118
119/*
120 * Set up one of the I/D BAT (block address translation) register pairs.
121 * The parameters are not checked; in particular size must be a power
122 * of 2 between 128k and 256M.
123 */
124void __init setbat(int index, unsigned long virt, unsigned long phys,
125 unsigned int size, int flags)
126{
127 unsigned int bl;
128 int wimgxpp;
129 union ubat *bat = BATS[index];
130
131 if (((flags & _PAGE_NO_CACHE) == 0) &&
132 cpu_has_feature(CPU_FTR_NEED_COHERENT))
133 flags |= _PAGE_COHERENT;
134
135 bl = (size >> 17) - 1;
136 if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
137 /* 603, 604, etc. */
138 /* Do DBAT first */
139 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
140 | _PAGE_COHERENT | _PAGE_GUARDED);
141 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
142 bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
143 bat[1].word[1] = phys | wimgxpp;
144#ifndef CONFIG_KGDB /* want user access for breakpoints */
145 if (flags & _PAGE_USER)
146#endif
147 bat[1].bat.batu.vp = 1;
148 if (flags & _PAGE_GUARDED) {
149 /* G bit must be zero in IBATs */
150 bat[0].word[0] = bat[0].word[1] = 0;
151 } else {
152 /* make IBAT same as DBAT */
153 bat[0] = bat[1];
154 }
155 } else {
156 /* 601 cpu */
157 if (bl > BL_8M)
158 bl = BL_8M;
159 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
160 | _PAGE_COHERENT);
161 wimgxpp |= (flags & _PAGE_RW)?
162 ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
163 bat->word[0] = virt | wimgxpp | 4; /* Ks=0, Ku=1 */
164 bat->word[1] = phys | bl | 0x40; /* V=1 */
165 }
166
167 bat_addrs[index].start = virt;
168 bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
169 bat_addrs[index].phys = phys;
170}
171
172/*
173 * Initialize the hash table and patch the instructions in hashtable.S.
174 */
175void __init MMU_init_hw(void)
176{
177 unsigned int hmask, mb, mb2;
178 unsigned int n_hpteg, lg_n_hpteg;
179
180 extern unsigned int hash_page_patch_A[];
181 extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
182 extern unsigned int hash_page[];
183 extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
184
185 if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) {
186 /*
187 * Put a blr (procedure return) instruction at the
188 * start of hash_page, since we can still get DSI
189 * exceptions on a 603.
190 */
191 hash_page[0] = 0x4e800020;
192 flush_icache_range((unsigned long) &hash_page[0],
193 (unsigned long) &hash_page[1]);
194 return;
195 }
196
197 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
198
199#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
200#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
201#define MIN_N_HPTEG 1024 /* min 64kB hash table */
202
203 /*
204 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
205 * This is less than the recommended amount, but then
206 * Linux ain't AIX.
207 */
208 n_hpteg = total_memory / (PAGE_SIZE * 8);
209 if (n_hpteg < MIN_N_HPTEG)
210 n_hpteg = MIN_N_HPTEG;
211 lg_n_hpteg = __ilog2(n_hpteg);
212 if (n_hpteg & (n_hpteg - 1)) {
213 ++lg_n_hpteg; /* round up if not power of 2 */
214 n_hpteg = 1 << lg_n_hpteg;
215 }
216 Hash_size = n_hpteg << LG_HPTEG_SIZE;
217
218 /*
219 * Find some memory for the hash table.
220 */
221 if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
222 Hash = mem_pieces_find(Hash_size, Hash_size);
223 cacheable_memzero(Hash, Hash_size);
224 _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
225
226 Hash_end = (PTE *) ((unsigned long)Hash + Hash_size);
227
228 printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
229 total_memory >> 20, Hash_size >> 10, Hash);
230
231
232 /*
233 * Patch up the instructions in hashtable.S:create_hpte
234 */
235 if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
236 Hash_mask = n_hpteg - 1;
237 hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
238 mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
239 if (lg_n_hpteg > 16)
240 mb2 = 16 - LG_HPTEG_SIZE;
241
242 hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
243 | ((unsigned int)(Hash) >> 16);
244 hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
245 hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
246 hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
247 hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
248
249 /*
250 * Ensure that the locations we've patched have been written
251 * out from the data cache and invalidated in the instruction
252 * cache, on those machines with split caches.
253 */
254 flush_icache_range((unsigned long) &hash_page_patch_A[0],
255 (unsigned long) &hash_page_patch_C[1]);
256
257 /*
258 * Patch up the instructions in hashtable.S:flush_hash_page
259 */
260 flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
261 | ((unsigned int)(Hash) >> 16);
262 flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
263 flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
264 flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
265 flush_icache_range((unsigned long) &flush_hash_patch_A[0],
266 (unsigned long) &flush_hash_patch_B[1]);
267
268 if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
269}
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