2 files changed, 47 insertions, 7 deletions

diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index fba7ca17a67e..b19bfef2034d 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -244,6 +244,13 @@ syscall_exit_cont:
         andis.  r10,r0,DBCR0_IC@h
         bnel-   load_dbcr0
 #endif
+#ifdef CONFIG_44x
+        lis     r4,icache_44x_need_flush@ha
+        lwz     r5,icache_44x_need_flush@l(r4)
+        cmplwi  cr0,r5,0
+        bne-    2f
+1:
+#endif /* CONFIG_44x */
         stwcx.  r0,0,r1                 /* to clear the reservation */
         lwz     r4,_LINK(r1)
         lwz     r5,_CCR(r1)
@@ -258,6 +265,12 @@ syscall_exit_cont:
         mtspr   SPRN_SRR1,r8
         SYNC
         RFI
+#ifdef CONFIG_44x
+2:      li      r7,0
+        iccci   r0,r0
+        stw     r7,icache_44x_need_flush@l(r4)
+        b       1b
+#endif  /* CONFIG_44x */
 
 66:     li      r3,-ENOSYS
         b       ret_from_syscall
@@ -679,6 +692,16 @@ resume_kernel:
 
         /* interrupts are hard-disabled at this point */
 restore:
+#ifdef CONFIG_44x
+        lis     r4,icache_44x_need_flush@ha
+        lwz     r5,icache_44x_need_flush@l(r4)
+        cmplwi  cr0,r5,0
+        beq+    1f
+        li      r6,0
+        iccci   r0,r0
+        stw     r6,icache_44x_need_flush@l(r4)
+1:
+#endif  /* CONFIG_44x */
         lwz     r0,GPR0(r1)
         lwz     r2,GPR2(r1)
         REST_4GPRS(3, r1)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index a22e1f4d94c8..e0c850d85c53 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -224,7 +224,16 @@ _GLOBAL(_tlbia)
  */
 _GLOBAL(_tlbie)
 #if defined(CONFIG_40x)
+        /* We run the search with interrupts disabled because we have to change
+         * the PID and I don't want to preempt when that happens.
+         */
+        mfmsr   r5
+        mfspr   r6,SPRN_PID
+        wrteei  0
+        mtspr   SPRN_PID,r4
         tlbsx.  r3, 0, r3
+        mtspr   SPRN_PID,r6
+        wrtee   r5
         bne     10f
         sync
         /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
@@ -234,22 +243,21 @@ _GLOBAL(_tlbie)
         isync
 10:
 #elif defined(CONFIG_44x)
-        mfspr   r4,SPRN_MMUCR
-        mfspr   r5,SPRN_PID                     /* Get PID */
-        rlwimi  r4,r5,0,24,31                   /* Set TID */
+        mfspr   r5,SPRN_MMUCR
+        rlwimi  r5,r4,0,24,31                   /* Set TID */
 
         /* We have to run the search with interrupts disabled, even critical
          * and debug interrupts (in fact the only critical exceptions we have
          * are debug and machine check).  Otherwise  an interrupt which causes
          * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
-        mfmsr   r5
+        mfmsr   r4
         lis     r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
         addi    r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
-        andc    r6,r5,r6
+        andc    r6,r4,r6
         mtmsr   r6
-        mtspr   SPRN_MMUCR,r4
+        mtspr   SPRN_MMUCR,r5
         tlbsx.  r3, 0, r3
-        mtmsr   r5
+        mtmsr   r4
         bne     10f
         sync
         /* There are only 64 TLB entries, so r3 < 64,
@@ -491,12 +499,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         addi    r3,r3,L1_CACHE_BYTES
         bdnz    0b
         sync
+#ifndef CONFIG_44x
+        /* We don't flush the icache on 44x. Those have a virtual icache
+         * and we don't have access to the virtual address here (it's
+         * not the page vaddr but where it's mapped in user space). The
+         * flushing of the icache on these is handled elsewhere, when
+         * a change in the address space occurs, before returning to
+         * user space
+         */
         mtctr   r4
 1:      icbi    0,r6
         addi    r6,r6,L1_CACHE_BYTES
         bdnz    1b
         sync
         isync
+#endif /* CONFIG_44x */
         blr
 
 /*