10 files changed, 158 insertions, 70 deletions

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 468721d9ebd2..bd037caa4055 100644
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
         sync
         isync
 
-        /* Enable L2 HW prefetch
+        /* Enable L2 HW prefetch, if L2 is enabled
          */
+        mfspr   r3,SPRN_L2CR
+        andis.  r3,r3,L2CR_L2E@h
+        beqlr
         mfspr   r3,SPRN_MSSCR0
         ori     r3,r3,3
         sync
@@ -324,6 +327,7 @@ _GLOBAL(__save_cpu_setup)
         cmplwi  cr4,r3,0x8002   /* 7457 */
         cmplwi  cr5,r3,0x8003   /* 7447A */
         cmplwi  cr6,r3,0x7000   /* 750FX */
+        cmplwi  cr7,r3,0x8004   /* 7448 */
         /* cr1 is 7400 || 7410 */
         cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
         /* cr0 is 74xx */
@@ -331,6 +335,7 @@ _GLOBAL(__save_cpu_setup)
         cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
         cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
+        cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
         bne     1f
         /* Backup 74xx specific regs */
         mfspr   r4,SPRN_MSSCR0
@@ -393,6 +398,7 @@ _GLOBAL(__restore_cpu_setup)
         cmplwi  cr4,r3,0x8002   /* 7457 */
         cmplwi  cr5,r3,0x8003   /* 7447A */
         cmplwi  cr6,r3,0x7000   /* 750FX */
+        cmplwi  cr7,r3,0x8004   /* 7448 */
         /* cr1 is 7400 || 7410 */
         cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
         /* cr0 is 74xx */
@@ -400,6 +406,7 @@ _GLOBAL(__restore_cpu_setup)
         cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
         cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
+        cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
         bne     2f
         /* Restore 74xx specific regs */
         lwz     r4,CS_MSSCR0(r5)
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 8a3d74f2531e..546e1ea4cafa 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -198,10 +198,10 @@ struct cpu_spec	cpu_specs[] = {
                 .num_pmcs               = 4,
                 .cpu_setup              = __setup_cpu_750
         },
-        {       /* 745/755 */
-                .pvr_mask               = 0xfffff000,
-                .pvr_value              = 0x00083000,
-                .cpu_name               = "745/755",
+        {       /* 750CX (80100 and 8010x?) */
+                .pvr_mask               = 0xfffffff0,
+                .pvr_value              = 0x00080100,
+                .cpu_name               = "750CX",
                 .cpu_features           = CPU_FTR_COMMON |
                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
@@ -210,11 +210,11 @@ struct cpu_spec	cpu_specs[] = {
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
                 .num_pmcs               = 4,
-                .cpu_setup              = __setup_cpu_750
+                .cpu_setup              = __setup_cpu_750cx
         },
-        {       /* 750CX (80100 and 8010x?) */
+        {       /* 750CX (82201 and 82202) */
                 .pvr_mask               = 0xfffffff0,
-                .pvr_value              = 0x00080100,
+                .pvr_value              = 0x00082200,
                 .cpu_name               = "750CX",
                 .cpu_features           = CPU_FTR_COMMON |
                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
@@ -226,10 +226,10 @@ struct cpu_spec	cpu_specs[] = {
                 .num_pmcs               = 4,
                 .cpu_setup              = __setup_cpu_750cx
         },
-        {       /* 750CX (82201 and 82202) */
+        {       /* 750CXe (82214) */
                 .pvr_mask               = 0xfffffff0,
-                .pvr_value              = 0x00082200,
-                .cpu_name               = "750CX",
+                .pvr_value              = 0x00082210,
+                .cpu_name               = "750CXe",
                 .cpu_features           = CPU_FTR_COMMON |
                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
@@ -240,9 +240,9 @@ struct cpu_spec	cpu_specs[] = {
                 .num_pmcs               = 4,
                 .cpu_setup              = __setup_cpu_750cx
         },
-        {       /* 750CXe (82214) */
-                .pvr_mask               = 0xfffffff0,
-                .pvr_value              = 0x00082210,
+        {       /* 750CXe "Gekko" (83214) */
+                .pvr_mask               = 0xffffffff,
+                .pvr_value              = 0x00083214,
                 .cpu_name               = "750CXe",
                 .cpu_features           = CPU_FTR_COMMON |
                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
@@ -254,6 +254,20 @@ struct cpu_spec	cpu_specs[] = {
                 .num_pmcs               = 4,
                 .cpu_setup              = __setup_cpu_750cx
         },
+        {       /* 745/755 */
+                .pvr_mask               = 0xfffff000,
+                .pvr_value              = 0x00083000,
+                .cpu_name               = "745/755",
+                .cpu_features           = CPU_FTR_COMMON |
+                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+                        CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+                        CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+                .cpu_user_features      = COMMON_PPC,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .num_pmcs               = 4,
+                .cpu_setup              = __setup_cpu_750
+        },
         {       /* 750FX rev 1.x */
                 .pvr_mask               = 0xffffff00,
                 .pvr_value              = 0x70000100,
@@ -536,6 +550,22 @@ struct cpu_spec	cpu_specs[] = {
                 .num_pmcs               = 6,
                 .cpu_setup              = __setup_cpu_745x
         },
+        {       /* 7448 */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x80040000,
+                .cpu_name               = "7448",
+                .cpu_features           = CPU_FTR_COMMON |
+                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+                        CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
+                        CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+                        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+                .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .num_pmcs               = 6,
+                .cpu_setup              = __setup_cpu_745x
+        },
         {       /* 82xx (8240, 8245, 8260 are all 603e cores) */
                 .pvr_mask               = 0x7fff0000,
                 .pvr_value              = 0x00810000,
@@ -922,6 +952,26 @@ struct cpu_spec	cpu_specs[] = {
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
         },
+        { /* 440GX Rev. F */
+                .pvr_mask               = 0xf0000fff,
+                .pvr_value              = 0x50000894,
+                .cpu_name               = "440GX Rev. F",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB,
+                .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+        },
+        { /* 440SP Rev. A */
+                .pvr_mask               = 0xff000fff,
+                .pvr_value              = 0x53000891,
+                .cpu_name               = "440SP Rev. A",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB,
+                .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+        },
 #endif /* CONFIG_44x */
 #ifdef CONFIG_FSL_BOOKE
         {       /* e200z5 */
diff --git a/arch/ppc/kernel/find_name.c b/arch/ppc/kernel/find_name.c
deleted file mode 100644
index 3c0fa8e0c077..000000000000
--- a/arch/ppc/kernel/find_name.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <stdio.h>
-#include <asm/page.h>
-#include <sys/mman.h>
-#include <strings.h>
-/*
- * Finds a given address in the System.map and prints it out
- * with its neighbors.  -- Cort
- */
-
-int main(int argc, char **argv)
-{
-        unsigned long addr, cmp, i;
-        FILE *f;
-        char s[256], last[256];
-        
-        if ( argc < 2 )
-        {
-                fprintf(stderr, "Usage: %s <address>\n", argv[0]);
-                return -1;
-        }
-
-        for ( i = 1 ; argv[i] ; i++ )
-        {
-                sscanf( argv[i], "%0lx", &addr );
-                /* adjust if addr is relative to kernelbase */
-                if ( addr < PAGE_OFFSET )
-                        addr += PAGE_OFFSET;
-                
-                if ( (f = fopen( "System.map", "r" )) == NULL )
-                {
-                        perror("fopen()\n");
-                        exit(-1);
-                }
-                
-                while ( !feof(f) )
-                {
-                        fgets(s, 255 , f);
-                        sscanf( s, "%0lx", &cmp );
-                        if ( addr < cmp )
-                                break;
-                        strcpy( last, s);
-                }
-                
-                printf( "%s%s", last, s );
-        }               
-        fclose(f);
-        return 0;
-}
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 69ff3a9961e8..9e68e32edb60 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -462,7 +462,11 @@ interrupt_base:
 
         /* Watchdog Timer Interrupt */
         /* TODO: Add watchdog support */
+#ifdef CONFIG_BOOKE_WDT
+        CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
+#else
         CRITICAL_EXCEPTION(0x1020, WatchdogTimer, UnknownException)
+#endif
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S
index 23fb51819ba5..0a5e723d3be6 100644
--- a/arch/ppc/kernel/head_4xx.S
+++ b/arch/ppc/kernel/head_4xx.S
@@ -448,7 +448,9 @@ label:
 
 /* 0x1020 - Watchdog Timer (WDT) Exception
 */
-
+#ifdef CONFIG_BOOKE_WDT
+        CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException)
+#else
         CRITICAL_EXCEPTION(0x1020, WDTException, UnknownException)
 #endif
 
diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
index eb804b7a3cb2..4028f4c7d978 100644
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -564,8 +564,11 @@ interrupt_base:
         EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
 
         /* Watchdog Timer Interrupt */
-        /* TODO: Add watchdog support */
+#ifdef CONFIG_BOOKE_WDT
+        CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
+#else
         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
+#endif
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S
index c39441048266..861115249b35 100644
--- a/arch/ppc/kernel/l2cr.S
+++ b/arch/ppc/kernel/l2cr.S
@@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
                The bit moved on the 7450.....
           ****/
 
+BEGIN_FTR_SECTION
+        /* Disable L2 prefetch on some 745x and try to ensure
+         * L2 prefetch engines are idle. As explained by errata
+         * text, we can't be sure they are, we just hope very hard
+         * that well be enough (sic !). At least I noticed Apple
+         * doesn't even bother doing the dcbf's here...
+         */
+        mfspr   r4,SPRN_MSSCR0
+        rlwinm  r4,r4,0,0,29
+        sync
+        mtspr   SPRN_MSSCR0,r4
+        sync
+        isync
+        lis     r4,KERNELBASE@h
+        dcbf    0,r4
+        dcbf    0,r4
+        dcbf    0,r4
+        dcbf    0,r4
+END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
+
         /* TODO: use HW flush assist when available */
 
         lis     r4,0x0002
@@ -230,7 +250,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
         oris    r3,r3,0x8000
         mtspr   SPRN_L2CR,r3
         sync
-
+        
+        /* Enable L2 HW prefetch on 744x/745x */
+BEGIN_FTR_SECTION
+        mfspr   r3,SPRN_MSSCR0
+        ori     r3,r3,3
+        sync
+        mtspr   SPRN_MSSCR0,r3
+        sync
+        isync
+END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
 4:
 
         /* Restore HID0[DPM] to whatever it was before */
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index e7d40cc6c1b6..88f6bb7b6964 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -51,9 +51,6 @@
 #include <asm/commproc.h>
 #endif
 
-/* Tell string.h we don't want memcpy etc. as cpp defines */
-#define EXPORT_SYMTAB_STROPS
-
 extern void transfer_to_handler(void);
 extern void do_IRQ(struct pt_regs *regs);
 extern void MachineCheckException(struct pt_regs *regs);
@@ -263,6 +260,7 @@ EXPORT_SYMBOL(__ashrdi3);
 EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__lshrdi3);
 EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(cacheable_memcpy);
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(memscan);
diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c
index 929e5d1cc7fe..545cfd0fab59 100644
--- a/arch/ppc/kernel/setup.c
+++ b/arch/ppc/kernel/setup.c
@@ -41,7 +41,11 @@
 #include <asm/xmon.h>
 #include <asm/ocp.h>
 
-#if defined(CONFIG_85xx) || defined(CONFIG_83xx) || defined(CONFIG_MPC10X_BRIDGE)
+#define USES_PPC_SYS (defined(CONFIG_85xx) || defined(CONFIG_83xx) || \
+                      defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_8260) || \
+                      defined(CONFIG_PPC_MPC52xx))
+
+#if USES_PPC_SYS
 #include <asm/ppc_sys.h>
 #endif
 
@@ -241,7 +245,7 @@ int show_cpuinfo(struct seq_file *m, void *v)
         seq_printf(m, "bogomips\t: %lu.%02lu\n",
                    lpj / (500000/HZ), (lpj / (5000/HZ)) % 100);
 
-#if defined(CONFIG_85xx) || defined(CONFIG_83xx) || defined(CONFIG_MPC10X_BRIDGE)
+#if USES_PPC_SYS
         if (cur_ppc_sys_spec->ppc_sys_name)
                 seq_printf(m, "chipset\t\t: %s\n",
                         cur_ppc_sys_spec->ppc_sys_name);
@@ -615,6 +619,26 @@ machine_init(unsigned long r3, unsigned long r4, unsigned long r5,
         if (ppc_md.progress)
                 ppc_md.progress("id mach(): done", 0x200);
 }
+#ifdef CONFIG_BOOKE_WDT
+/* Checks wdt=x and wdt_period=xx command-line option */
+int __init early_parse_wdt(char *p)
+{
+        if (p && strncmp(p, "0", 1) != 0)
+               booke_wdt_enabled = 1;
+
+        return 0;
+}
+early_param("wdt", early_parse_wdt);
+
+int __init early_parse_wdt_period (char *p)
+{
+        if (p)
+                booke_wdt_period = simple_strtoul(p, NULL, 0);
+
+        return 0;
+}
+early_param("wdt_period", early_parse_wdt_period);
+#endif  /* CONFIG_BOOKE_WDT */
 
 /* Checks "l2cr=xxxx" command-line option */
 int __init ppc_setup_l2cr(char *str)
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
index 9e6ae5696650..d87423d1003a 100644
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -904,6 +904,25 @@ void SPEFloatingPointException(struct pt_regs *regs)
 }
 #endif
 
+#ifdef CONFIG_BOOKE_WDT
+/*
+ * Default handler for a Watchdog exception,
+ * spins until a reboot occurs
+ */
+void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
+{
+        /* Generic WatchdogHandler, implement your own */
+        mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
+        return;
+}
+
+void WatchdogException(struct pt_regs *regs)
+{
+        printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
+        WatchdogHandler(regs);
+}
+#endif
+
 void __init trap_init(void)
 {
 }