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-rw-r--r--arch/ppc/kernel/pci.c1849
1 files changed, 1849 insertions, 0 deletions
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
new file mode 100644
index 000000000000..98f94b60204c
--- /dev/null
+++ b/arch/ppc/kernel/pci.c
@@ -0,0 +1,1849 @@
1/*
2 * Common pmac/prep/chrp pci routines. -- Cort
3 */
4
5#include <linux/config.h>
6#include <linux/kernel.h>
7#include <linux/pci.h>
8#include <linux/delay.h>
9#include <linux/string.h>
10#include <linux/init.h>
11#include <linux/capability.h>
12#include <linux/sched.h>
13#include <linux/errno.h>
14#include <linux/bootmem.h>
15
16#include <asm/processor.h>
17#include <asm/io.h>
18#include <asm/prom.h>
19#include <asm/sections.h>
20#include <asm/pci-bridge.h>
21#include <asm/byteorder.h>
22#include <asm/irq.h>
23#include <asm/uaccess.h>
24
25#undef DEBUG
26
27#ifdef DEBUG
28#define DBG(x...) printk(x)
29#else
30#define DBG(x...)
31#endif
32
33unsigned long isa_io_base = 0;
34unsigned long isa_mem_base = 0;
35unsigned long pci_dram_offset = 0;
36int pcibios_assign_bus_offset = 1;
37
38void pcibios_make_OF_bus_map(void);
39
40static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43static void update_bridge_base(struct pci_bus *bus, int i);
44static void pcibios_fixup_resources(struct pci_dev* dev);
45static void fixup_broken_pcnet32(struct pci_dev* dev);
46static int reparent_resources(struct resource *parent, struct resource *res);
47static void fixup_rev1_53c810(struct pci_dev* dev);
48static void fixup_cpc710_pci64(struct pci_dev* dev);
49#ifdef CONFIG_PPC_OF
50static u8* pci_to_OF_bus_map;
51#endif
52
53/* By default, we don't re-assign bus numbers. We do this only on
54 * some pmacs
55 */
56int pci_assign_all_busses;
57
58struct pci_controller* hose_head;
59struct pci_controller** hose_tail = &hose_head;
60
61static int pci_bus_count;
62
63static void
64fixup_rev1_53c810(struct pci_dev* dev)
65{
66 /* rev 1 ncr53c810 chips don't set the class at all which means
67 * they don't get their resources remapped. Fix that here.
68 */
69
70 if ((dev->class == PCI_CLASS_NOT_DEFINED)) {
71 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
72 dev->class = PCI_CLASS_STORAGE_SCSI;
73 }
74}
75DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
76
77static void
78fixup_broken_pcnet32(struct pci_dev* dev)
79{
80 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
81 dev->vendor = PCI_VENDOR_ID_AMD;
82 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
83 pci_name_device(dev);
84 }
85}
86DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
87
88static void
89fixup_cpc710_pci64(struct pci_dev* dev)
90{
91 /* Hide the PCI64 BARs from the kernel as their content doesn't
92 * fit well in the resource management
93 */
94 dev->resource[0].start = dev->resource[0].end = 0;
95 dev->resource[0].flags = 0;
96 dev->resource[1].start = dev->resource[1].end = 0;
97 dev->resource[1].flags = 0;
98}
99DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
100
101static void
102pcibios_fixup_resources(struct pci_dev *dev)
103{
104 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
105 int i;
106 unsigned long offset;
107
108 if (!hose) {
109 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
110 return;
111 }
112 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
113 struct resource *res = dev->resource + i;
114 if (!res->flags)
115 continue;
116 if (res->end == 0xffffffff) {
117 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
118 pci_name(dev), i, res->start, res->end);
119 res->end -= res->start;
120 res->start = 0;
121 res->flags |= IORESOURCE_UNSET;
122 continue;
123 }
124 offset = 0;
125 if (res->flags & IORESOURCE_MEM) {
126 offset = hose->pci_mem_offset;
127 } else if (res->flags & IORESOURCE_IO) {
128 offset = (unsigned long) hose->io_base_virt
129 - isa_io_base;
130 }
131 if (offset != 0) {
132 res->start += offset;
133 res->end += offset;
134#ifdef DEBUG
135 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
136 i, res->flags, pci_name(dev),
137 res->start - offset, res->start);
138#endif
139 }
140 }
141
142 /* Call machine specific resource fixup */
143 if (ppc_md.pcibios_fixup_resources)
144 ppc_md.pcibios_fixup_resources(dev);
145}
146DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
147
148void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
149 struct resource *res)
150{
151 unsigned long offset = 0;
152 struct pci_controller *hose = dev->sysdata;
153
154 if (hose && res->flags & IORESOURCE_IO)
155 offset = (unsigned long)hose->io_base_virt - isa_io_base;
156 else if (hose && res->flags & IORESOURCE_MEM)
157 offset = hose->pci_mem_offset;
158 region->start = res->start - offset;
159 region->end = res->end - offset;
160}
161EXPORT_SYMBOL(pcibios_resource_to_bus);
162
163/*
164 * We need to avoid collisions with `mirrored' VGA ports
165 * and other strange ISA hardware, so we always want the
166 * addresses to be allocated in the 0x000-0x0ff region
167 * modulo 0x400.
168 *
169 * Why? Because some silly external IO cards only decode
170 * the low 10 bits of the IO address. The 0x00-0xff region
171 * is reserved for motherboard devices that decode all 16
172 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
173 * but we want to try to avoid allocating at 0x2900-0x2bff
174 * which might have be mirrored at 0x0100-0x03ff..
175 */
176void pcibios_align_resource(void *data, struct resource *res, unsigned long size,
177 unsigned long align)
178{
179 struct pci_dev *dev = data;
180
181 if (res->flags & IORESOURCE_IO) {
182 unsigned long start = res->start;
183
184 if (size > 0x100) {
185 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
186 " (%ld bytes)\n", pci_name(dev),
187 dev->resource - res, size);
188 }
189
190 if (start & 0x300) {
191 start = (start + 0x3ff) & ~0x3ff;
192 res->start = start;
193 }
194 }
195}
196EXPORT_SYMBOL(pcibios_align_resource);
197
198/*
199 * Handle resources of PCI devices. If the world were perfect, we could
200 * just allocate all the resource regions and do nothing more. It isn't.
201 * On the other hand, we cannot just re-allocate all devices, as it would
202 * require us to know lots of host bridge internals. So we attempt to
203 * keep as much of the original configuration as possible, but tweak it
204 * when it's found to be wrong.
205 *
206 * Known BIOS problems we have to work around:
207 * - I/O or memory regions not configured
208 * - regions configured, but not enabled in the command register
209 * - bogus I/O addresses above 64K used
210 * - expansion ROMs left enabled (this may sound harmless, but given
211 * the fact the PCI specs explicitly allow address decoders to be
212 * shared between expansion ROMs and other resource regions, it's
213 * at least dangerous)
214 *
215 * Our solution:
216 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
217 * This gives us fixed barriers on where we can allocate.
218 * (2) Allocate resources for all enabled devices. If there is
219 * a collision, just mark the resource as unallocated. Also
220 * disable expansion ROMs during this step.
221 * (3) Try to allocate resources for disabled devices. If the
222 * resources were assigned correctly, everything goes well,
223 * if they weren't, they won't disturb allocation of other
224 * resources.
225 * (4) Assign new addresses to resources which were either
226 * not configured at all or misconfigured. If explicitly
227 * requested by the user, configure expansion ROM address
228 * as well.
229 */
230
231static void __init
232pcibios_allocate_bus_resources(struct list_head *bus_list)
233{
234 struct pci_bus *bus;
235 int i;
236 struct resource *res, *pr;
237
238 /* Depth-First Search on bus tree */
239 list_for_each_entry(bus, bus_list, node) {
240 for (i = 0; i < 4; ++i) {
241 if ((res = bus->resource[i]) == NULL || !res->flags
242 || res->start > res->end)
243 continue;
244 if (bus->parent == NULL)
245 pr = (res->flags & IORESOURCE_IO)?
246 &ioport_resource: &iomem_resource;
247 else {
248 pr = pci_find_parent_resource(bus->self, res);
249 if (pr == res) {
250 /* this happens when the generic PCI
251 * code (wrongly) decides that this
252 * bridge is transparent -- paulus
253 */
254 continue;
255 }
256 }
257
258 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
259 res->start, res->end, res->flags, pr);
260 if (pr) {
261 if (request_resource(pr, res) == 0)
262 continue;
263 /*
264 * Must be a conflict with an existing entry.
265 * Move that entry (or entries) under the
266 * bridge resource and try again.
267 */
268 if (reparent_resources(pr, res) == 0)
269 continue;
270 }
271 printk(KERN_ERR "PCI: Cannot allocate resource region "
272 "%d of PCI bridge %d\n", i, bus->number);
273 if (pci_relocate_bridge_resource(bus, i))
274 bus->resource[i] = NULL;
275 }
276 pcibios_allocate_bus_resources(&bus->children);
277 }
278}
279
280/*
281 * Reparent resource children of pr that conflict with res
282 * under res, and make res replace those children.
283 */
284static int __init
285reparent_resources(struct resource *parent, struct resource *res)
286{
287 struct resource *p, **pp;
288 struct resource **firstpp = NULL;
289
290 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
291 if (p->end < res->start)
292 continue;
293 if (res->end < p->start)
294 break;
295 if (p->start < res->start || p->end > res->end)
296 return -1; /* not completely contained */
297 if (firstpp == NULL)
298 firstpp = pp;
299 }
300 if (firstpp == NULL)
301 return -1; /* didn't find any conflicting entries? */
302 res->parent = parent;
303 res->child = *firstpp;
304 res->sibling = *pp;
305 *firstpp = res;
306 *pp = NULL;
307 for (p = res->child; p != NULL; p = p->sibling) {
308 p->parent = res;
309 DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n",
310 p->name, p->start, p->end, res->name);
311 }
312 return 0;
313}
314
315/*
316 * A bridge has been allocated a range which is outside the range
317 * of its parent bridge, so it needs to be moved.
318 */
319static int __init
320pci_relocate_bridge_resource(struct pci_bus *bus, int i)
321{
322 struct resource *res, *pr, *conflict;
323 unsigned long try, size;
324 int j;
325 struct pci_bus *parent = bus->parent;
326
327 if (parent == NULL) {
328 /* shouldn't ever happen */
329 printk(KERN_ERR "PCI: can't move host bridge resource\n");
330 return -1;
331 }
332 res = bus->resource[i];
333 if (res == NULL)
334 return -1;
335 pr = NULL;
336 for (j = 0; j < 4; j++) {
337 struct resource *r = parent->resource[j];
338 if (!r)
339 continue;
340 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
341 continue;
342 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
343 pr = r;
344 break;
345 }
346 if (res->flags & IORESOURCE_PREFETCH)
347 pr = r;
348 }
349 if (pr == NULL)
350 return -1;
351 size = res->end - res->start;
352 if (pr->start > pr->end || size > pr->end - pr->start)
353 return -1;
354 try = pr->end;
355 for (;;) {
356 res->start = try - size;
357 res->end = try;
358 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
359 break;
360 if (conflict->start <= pr->start + size)
361 return -1;
362 try = conflict->start - 1;
363 }
364 if (request_resource(pr, res)) {
365 DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n",
366 res->start, res->end);
367 return -1; /* "can't happen" */
368 }
369 update_bridge_base(bus, i);
370 printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n",
371 bus->number, i, res->start, res->end);
372 return 0;
373}
374
375static int __init
376probe_resource(struct pci_bus *parent, struct resource *pr,
377 struct resource *res, struct resource **conflict)
378{
379 struct pci_bus *bus;
380 struct pci_dev *dev;
381 struct resource *r;
382 int i;
383
384 for (r = pr->child; r != NULL; r = r->sibling) {
385 if (r->end >= res->start && res->end >= r->start) {
386 *conflict = r;
387 return 1;
388 }
389 }
390 list_for_each_entry(bus, &parent->children, node) {
391 for (i = 0; i < 4; ++i) {
392 if ((r = bus->resource[i]) == NULL)
393 continue;
394 if (!r->flags || r->start > r->end || r == res)
395 continue;
396 if (pci_find_parent_resource(bus->self, r) != pr)
397 continue;
398 if (r->end >= res->start && res->end >= r->start) {
399 *conflict = r;
400 return 1;
401 }
402 }
403 }
404 list_for_each_entry(dev, &parent->devices, bus_list) {
405 for (i = 0; i < 6; ++i) {
406 r = &dev->resource[i];
407 if (!r->flags || (r->flags & IORESOURCE_UNSET))
408 continue;
409 if (pci_find_parent_resource(dev, r) != pr)
410 continue;
411 if (r->end >= res->start && res->end >= r->start) {
412 *conflict = r;
413 return 1;
414 }
415 }
416 }
417 return 0;
418}
419
420static void __init
421update_bridge_base(struct pci_bus *bus, int i)
422{
423 struct resource *res = bus->resource[i];
424 u8 io_base_lo, io_limit_lo;
425 u16 mem_base, mem_limit;
426 u16 cmd;
427 unsigned long start, end, off;
428 struct pci_dev *dev = bus->self;
429 struct pci_controller *hose = dev->sysdata;
430
431 if (!hose) {
432 printk("update_bridge_base: no hose?\n");
433 return;
434 }
435 pci_read_config_word(dev, PCI_COMMAND, &cmd);
436 pci_write_config_word(dev, PCI_COMMAND,
437 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
438 if (res->flags & IORESOURCE_IO) {
439 off = (unsigned long) hose->io_base_virt - isa_io_base;
440 start = res->start - off;
441 end = res->end - off;
442 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
443 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
444 if (end > 0xffff) {
445 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
446 start >> 16);
447 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
448 end >> 16);
449 io_base_lo |= PCI_IO_RANGE_TYPE_32;
450 } else
451 io_base_lo |= PCI_IO_RANGE_TYPE_16;
452 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
453 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
454
455 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
456 == IORESOURCE_MEM) {
457 off = hose->pci_mem_offset;
458 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
459 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
460 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
461 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
462
463 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
464 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
465 off = hose->pci_mem_offset;
466 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
467 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
468 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
469 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
470
471 } else {
472 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
473 pci_name(dev), i, res->flags);
474 }
475 pci_write_config_word(dev, PCI_COMMAND, cmd);
476}
477
478static inline void alloc_resource(struct pci_dev *dev, int idx)
479{
480 struct resource *pr, *r = &dev->resource[idx];
481
482 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
483 pci_name(dev), idx, r->start, r->end, r->flags);
484 pr = pci_find_parent_resource(dev, r);
485 if (!pr || request_resource(pr, r) < 0) {
486 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
487 " of device %s\n", idx, pci_name(dev));
488 if (pr)
489 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
490 pr, pr->start, pr->end, pr->flags);
491 /* We'll assign a new address later */
492 r->flags |= IORESOURCE_UNSET;
493 r->end -= r->start;
494 r->start = 0;
495 }
496}
497
498static void __init
499pcibios_allocate_resources(int pass)
500{
501 struct pci_dev *dev = NULL;
502 int idx, disabled;
503 u16 command;
504 struct resource *r;
505
506 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
507 pci_read_config_word(dev, PCI_COMMAND, &command);
508 for (idx = 0; idx < 6; idx++) {
509 r = &dev->resource[idx];
510 if (r->parent) /* Already allocated */
511 continue;
512 if (!r->flags || (r->flags & IORESOURCE_UNSET))
513 continue; /* Not assigned at all */
514 if (r->flags & IORESOURCE_IO)
515 disabled = !(command & PCI_COMMAND_IO);
516 else
517 disabled = !(command & PCI_COMMAND_MEMORY);
518 if (pass == disabled)
519 alloc_resource(dev, idx);
520 }
521 if (pass)
522 continue;
523 r = &dev->resource[PCI_ROM_RESOURCE];
524 if (r->flags & IORESOURCE_ROM_ENABLE) {
525 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
526 u32 reg;
527 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
528 r->flags &= ~IORESOURCE_ROM_ENABLE;
529 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
530 pci_write_config_dword(dev, dev->rom_base_reg,
531 reg & ~PCI_ROM_ADDRESS_ENABLE);
532 }
533 }
534}
535
536static void __init
537pcibios_assign_resources(void)
538{
539 struct pci_dev *dev = NULL;
540 int idx;
541 struct resource *r;
542
543 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
544 int class = dev->class >> 8;
545
546 /* Don't touch classless devices and host bridges */
547 if (!class || class == PCI_CLASS_BRIDGE_HOST)
548 continue;
549
550 for (idx = 0; idx < 6; idx++) {
551 r = &dev->resource[idx];
552
553 /*
554 * We shall assign a new address to this resource,
555 * either because the BIOS (sic) forgot to do so
556 * or because we have decided the old address was
557 * unusable for some reason.
558 */
559 if ((r->flags & IORESOURCE_UNSET) && r->end &&
560 (!ppc_md.pcibios_enable_device_hook ||
561 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
562 r->flags &= ~IORESOURCE_UNSET;
563 pci_assign_resource(dev, idx);
564 }
565 }
566
567#if 0 /* don't assign ROMs */
568 r = &dev->resource[PCI_ROM_RESOURCE];
569 r->end -= r->start;
570 r->start = 0;
571 if (r->end)
572 pci_assign_resource(dev, PCI_ROM_RESOURCE);
573#endif
574 }
575}
576
577
578int
579pcibios_enable_resources(struct pci_dev *dev, int mask)
580{
581 u16 cmd, old_cmd;
582 int idx;
583 struct resource *r;
584
585 pci_read_config_word(dev, PCI_COMMAND, &cmd);
586 old_cmd = cmd;
587 for (idx=0; idx<6; idx++) {
588 /* Only set up the requested stuff */
589 if (!(mask & (1<<idx)))
590 continue;
591
592 r = &dev->resource[idx];
593 if (r->flags & IORESOURCE_UNSET) {
594 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
595 return -EINVAL;
596 }
597 if (r->flags & IORESOURCE_IO)
598 cmd |= PCI_COMMAND_IO;
599 if (r->flags & IORESOURCE_MEM)
600 cmd |= PCI_COMMAND_MEMORY;
601 }
602 if (dev->resource[PCI_ROM_RESOURCE].start)
603 cmd |= PCI_COMMAND_MEMORY;
604 if (cmd != old_cmd) {
605 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
606 pci_write_config_word(dev, PCI_COMMAND, cmd);
607 }
608 return 0;
609}
610
611static int next_controller_index;
612
613struct pci_controller * __init
614pcibios_alloc_controller(void)
615{
616 struct pci_controller *hose;
617
618 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
619 memset(hose, 0, sizeof(struct pci_controller));
620
621 *hose_tail = hose;
622 hose_tail = &hose->next;
623
624 hose->index = next_controller_index++;
625
626 return hose;
627}
628
629#ifdef CONFIG_PPC_OF
630/*
631 * Functions below are used on OpenFirmware machines.
632 */
633static void __openfirmware
634make_one_node_map(struct device_node* node, u8 pci_bus)
635{
636 int *bus_range;
637 int len;
638
639 if (pci_bus >= pci_bus_count)
640 return;
641 bus_range = (int *) get_property(node, "bus-range", &len);
642 if (bus_range == NULL || len < 2 * sizeof(int)) {
643 printk(KERN_WARNING "Can't get bus-range for %s, "
644 "assuming it starts at 0\n", node->full_name);
645 pci_to_OF_bus_map[pci_bus] = 0;
646 } else
647 pci_to_OF_bus_map[pci_bus] = bus_range[0];
648
649 for (node=node->child; node != 0;node = node->sibling) {
650 struct pci_dev* dev;
651 unsigned int *class_code, *reg;
652
653 class_code = (unsigned int *) get_property(node, "class-code", NULL);
654 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
655 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
656 continue;
657 reg = (unsigned int *)get_property(node, "reg", NULL);
658 if (!reg)
659 continue;
660 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
661 if (!dev || !dev->subordinate)
662 continue;
663 make_one_node_map(node, dev->subordinate->number);
664 }
665}
666
667void __openfirmware
668pcibios_make_OF_bus_map(void)
669{
670 int i;
671 struct pci_controller* hose;
672 u8* of_prop_map;
673
674 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
675 if (!pci_to_OF_bus_map) {
676 printk(KERN_ERR "Can't allocate OF bus map !\n");
677 return;
678 }
679
680 /* We fill the bus map with invalid values, that helps
681 * debugging.
682 */
683 for (i=0; i<pci_bus_count; i++)
684 pci_to_OF_bus_map[i] = 0xff;
685
686 /* For each hose, we begin searching bridges */
687 for(hose=hose_head; hose; hose=hose->next) {
688 struct device_node* node;
689 node = (struct device_node *)hose->arch_data;
690 if (!node)
691 continue;
692 make_one_node_map(node, hose->first_busno);
693 }
694 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", NULL);
695 if (of_prop_map)
696 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
697#ifdef DEBUG
698 printk("PCI->OF bus map:\n");
699 for (i=0; i<pci_bus_count; i++) {
700 if (pci_to_OF_bus_map[i] == 0xff)
701 continue;
702 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
703 }
704#endif
705}
706
707typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
708
709static struct device_node* __openfirmware
710scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
711{
712 struct device_node* sub_node;
713
714 for (; node != 0;node = node->sibling) {
715 unsigned int *class_code;
716
717 if (filter(node, data))
718 return node;
719
720 /* For PCI<->PCI bridges or CardBus bridges, we go down
721 * Note: some OFs create a parent node "multifunc-device" as
722 * a fake root for all functions of a multi-function device,
723 * we go down them as well.
724 */
725 class_code = (unsigned int *) get_property(node, "class-code", NULL);
726 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
727 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
728 strcmp(node->name, "multifunc-device"))
729 continue;
730 sub_node = scan_OF_pci_childs(node->child, filter, data);
731 if (sub_node)
732 return sub_node;
733 }
734 return NULL;
735}
736
737static int
738scan_OF_pci_childs_iterator(struct device_node* node, void* data)
739{
740 unsigned int *reg;
741 u8* fdata = (u8*)data;
742
743 reg = (unsigned int *) get_property(node, "reg", NULL);
744 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
745 && ((reg[0] >> 16) & 0xff) == fdata[0])
746 return 1;
747 return 0;
748}
749
750static struct device_node* __openfirmware
751scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
752{
753 u8 filter_data[2] = {bus, dev_fn};
754
755 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
756}
757
758/*
759 * Scans the OF tree for a device node matching a PCI device
760 */
761struct device_node *
762pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
763{
764 struct pci_controller *hose;
765 struct device_node *node;
766 int busnr;
767
768 if (!have_of)
769 return NULL;
770
771 /* Lookup the hose */
772 busnr = bus->number;
773 hose = pci_bus_to_hose(busnr);
774 if (!hose)
775 return NULL;
776
777 /* Check it has an OF node associated */
778 node = (struct device_node *) hose->arch_data;
779 if (!node)
780 return NULL;
781
782 /* Fixup bus number according to what OF think it is. */
783#ifdef CONFIG_PPC_PMAC
784 /* The G5 need a special case here. Basically, we don't remap all
785 * busses on it so we don't create the pci-OF-map. However, we do
786 * remap the AGP bus and so have to deal with it. A future better
787 * fix has to be done by making the remapping per-host and always
788 * filling the pci_to_OF map. --BenH
789 */
790 if (_machine == _MACH_Pmac && busnr >= 0xf0)
791 busnr -= 0xf0;
792 else
793#endif
794 if (pci_to_OF_bus_map)
795 busnr = pci_to_OF_bus_map[busnr];
796 if (busnr == 0xff)
797 return NULL;
798
799 /* Now, lookup childs of the hose */
800 return scan_OF_childs_for_device(node->child, busnr, devfn);
801}
802
803struct device_node*
804pci_device_to_OF_node(struct pci_dev *dev)
805{
806 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
807}
808
809/* This routine is meant to be used early during boot, when the
810 * PCI bus numbers have not yet been assigned, and you need to
811 * issue PCI config cycles to an OF device.
812 * It could also be used to "fix" RTAS config cycles if you want
813 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
814 * config cycles.
815 */
816struct pci_controller*
817pci_find_hose_for_OF_device(struct device_node* node)
818{
819 if (!have_of)
820 return NULL;
821 while(node) {
822 struct pci_controller* hose;
823 for (hose=hose_head;hose;hose=hose->next)
824 if (hose->arch_data == node)
825 return hose;
826 node=node->parent;
827 }
828 return NULL;
829}
830
831static int __openfirmware
832find_OF_pci_device_filter(struct device_node* node, void* data)
833{
834 return ((void *)node == data);
835}
836
837/*
838 * Returns the PCI device matching a given OF node
839 */
840int
841pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
842{
843 unsigned int *reg;
844 struct pci_controller* hose;
845 struct pci_dev* dev = NULL;
846
847 if (!have_of)
848 return -ENODEV;
849 /* Make sure it's really a PCI device */
850 hose = pci_find_hose_for_OF_device(node);
851 if (!hose || !hose->arch_data)
852 return -ENODEV;
853 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
854 find_OF_pci_device_filter, (void *)node))
855 return -ENODEV;
856 reg = (unsigned int *) get_property(node, "reg", NULL);
857 if (!reg)
858 return -ENODEV;
859 *bus = (reg[0] >> 16) & 0xff;
860 *devfn = ((reg[0] >> 8) & 0xff);
861
862 /* Ok, here we need some tweak. If we have already renumbered
863 * all busses, we can't rely on the OF bus number any more.
864 * the pci_to_OF_bus_map is not enough as several PCI busses
865 * may match the same OF bus number.
866 */
867 if (!pci_to_OF_bus_map)
868 return 0;
869 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
870 if (pci_to_OF_bus_map[dev->bus->number] != *bus)
871 continue;
872 if (dev->devfn != *devfn)
873 continue;
874 *bus = dev->bus->number;
875 return 0;
876 }
877 return -ENODEV;
878}
879
880void __init
881pci_process_bridge_OF_ranges(struct pci_controller *hose,
882 struct device_node *dev, int primary)
883{
884 static unsigned int static_lc_ranges[256] __initdata;
885 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
886 unsigned int size;
887 int rlen = 0, orig_rlen;
888 int memno = 0;
889 struct resource *res;
890 int np, na = prom_n_addr_cells(dev);
891 np = na + 5;
892
893 /* First we try to merge ranges to fix a problem with some pmacs
894 * that can have more than 3 ranges, fortunately using contiguous
895 * addresses -- BenH
896 */
897 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
898 if (!dt_ranges)
899 return;
900 /* Sanity check, though hopefully that never happens */
901 if (rlen > sizeof(static_lc_ranges)) {
902 printk(KERN_WARNING "OF ranges property too large !\n");
903 rlen = sizeof(static_lc_ranges);
904 }
905 lc_ranges = static_lc_ranges;
906 memcpy(lc_ranges, dt_ranges, rlen);
907 orig_rlen = rlen;
908
909 /* Let's work on a copy of the "ranges" property instead of damaging
910 * the device-tree image in memory
911 */
912 ranges = lc_ranges;
913 prev = NULL;
914 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
915 if (prev) {
916 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
917 (prev[2] + prev[na+4]) == ranges[2] &&
918 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
919 prev[na+4] += ranges[na+4];
920 ranges[0] = 0;
921 ranges += np;
922 continue;
923 }
924 }
925 prev = ranges;
926 ranges += np;
927 }
928
929 /*
930 * The ranges property is laid out as an array of elements,
931 * each of which comprises:
932 * cells 0 - 2: a PCI address
933 * cells 3 or 3+4: a CPU physical address
934 * (size depending on dev->n_addr_cells)
935 * cells 4+5 or 5+6: the size of the range
936 */
937 ranges = lc_ranges;
938 rlen = orig_rlen;
939 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
940 res = NULL;
941 size = ranges[na+4];
942 switch (ranges[0] >> 24) {
943 case 1: /* I/O space */
944 if (ranges[2] != 0)
945 break;
946 hose->io_base_phys = ranges[na+2];
947 /* limit I/O space to 16MB */
948 if (size > 0x01000000)
949 size = 0x01000000;
950 hose->io_base_virt = ioremap(ranges[na+2], size);
951 if (primary)
952 isa_io_base = (unsigned long) hose->io_base_virt;
953 res = &hose->io_resource;
954 res->flags = IORESOURCE_IO;
955 res->start = ranges[2];
956 break;
957 case 2: /* memory space */
958 memno = 0;
959 if (ranges[1] == 0 && ranges[2] == 0
960 && ranges[na+4] <= (16 << 20)) {
961 /* 1st 16MB, i.e. ISA memory area */
962 if (primary)
963 isa_mem_base = ranges[na+2];
964 memno = 1;
965 }
966 while (memno < 3 && hose->mem_resources[memno].flags)
967 ++memno;
968 if (memno == 0)
969 hose->pci_mem_offset = ranges[na+2] - ranges[2];
970 if (memno < 3) {
971 res = &hose->mem_resources[memno];
972 res->flags = IORESOURCE_MEM;
973 res->start = ranges[na+2];
974 }
975 break;
976 }
977 if (res != NULL) {
978 res->name = dev->full_name;
979 res->end = res->start + size - 1;
980 res->parent = NULL;
981 res->sibling = NULL;
982 res->child = NULL;
983 }
984 ranges += np;
985 }
986}
987
988/* We create the "pci-OF-bus-map" property now so it appears in the
989 * /proc device tree
990 */
991void __init
992pci_create_OF_bus_map(void)
993{
994 struct property* of_prop;
995
996 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
997 if (of_prop && find_path_device("/")) {
998 memset(of_prop, -1, sizeof(struct property) + 256);
999 of_prop->name = "pci-OF-bus-map";
1000 of_prop->length = 256;
1001 of_prop->value = (unsigned char *)&of_prop[1];
1002 prom_add_property(find_path_device("/"), of_prop);
1003 }
1004}
1005
1006static ssize_t pci_show_devspec(struct device *dev, char *buf)
1007{
1008 struct pci_dev *pdev;
1009 struct device_node *np;
1010
1011 pdev = to_pci_dev (dev);
1012 np = pci_device_to_OF_node(pdev);
1013 if (np == NULL || np->full_name == NULL)
1014 return 0;
1015 return sprintf(buf, "%s", np->full_name);
1016}
1017static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1018
1019#endif /* CONFIG_PPC_OF */
1020
1021/* Add sysfs properties */
1022void pcibios_add_platform_entries(struct pci_dev *pdev)
1023{
1024#ifdef CONFIG_PPC_OF
1025 device_create_file(&pdev->dev, &dev_attr_devspec);
1026#endif /* CONFIG_PPC_OF */
1027}
1028
1029
1030#ifdef CONFIG_PPC_PMAC
1031/*
1032 * This set of routines checks for PCI<->PCI bridges that have closed
1033 * IO resources and have child devices. It tries to re-open an IO
1034 * window on them.
1035 *
1036 * This is a _temporary_ fix to workaround a problem with Apple's OF
1037 * closing IO windows on P2P bridges when the OF drivers of cards
1038 * below this bridge don't claim any IO range (typically ATI or
1039 * Adaptec).
1040 *
1041 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1042 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1043 * ordering when creating the host bus resources, and maybe a few more
1044 * minor tweaks
1045 */
1046
1047/* Initialize bridges with base/limit values we have collected */
1048static void __init
1049do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1050{
1051 struct pci_dev *bridge = bus->self;
1052 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1053 u32 l;
1054 u16 w;
1055 struct resource res;
1056
1057 if (bus->resource[0] == NULL)
1058 return;
1059 res = *(bus->resource[0]);
1060
1061 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1062 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1063 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1064 DBG(" IO window: %08lx-%08lx\n", res.start, res.end);
1065
1066 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1067 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1068 l &= 0xffff000f;
1069 l |= (res.start >> 8) & 0x00f0;
1070 l |= res.end & 0xf000;
1071 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1072
1073 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1074 l = (res.start >> 16) | (res.end & 0xffff0000);
1075 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1076 }
1077
1078 pci_read_config_word(bridge, PCI_COMMAND, &w);
1079 w |= PCI_COMMAND_IO;
1080 pci_write_config_word(bridge, PCI_COMMAND, w);
1081
1082#if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1083 if (enable_vga) {
1084 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1085 w |= PCI_BRIDGE_CTL_VGA;
1086 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1087 }
1088#endif
1089}
1090
1091/* This function is pretty basic and actually quite broken for the
1092 * general case, it's enough for us right now though. It's supposed
1093 * to tell us if we need to open an IO range at all or not and what
1094 * size.
1095 */
1096static int __init
1097check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1098{
1099 struct pci_dev *dev;
1100 int i;
1101 int rc = 0;
1102
1103#define push_end(res, size) do { unsigned long __sz = (size) ; \
1104 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1105 } while (0)
1106
1107 list_for_each_entry(dev, &bus->devices, bus_list) {
1108 u16 class = dev->class >> 8;
1109
1110 if (class == PCI_CLASS_DISPLAY_VGA ||
1111 class == PCI_CLASS_NOT_DEFINED_VGA)
1112 *found_vga = 1;
1113 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1114 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1115 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1116 push_end(res, 0xfff);
1117
1118 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1119 struct resource *r;
1120 unsigned long r_size;
1121
1122 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1123 && i >= PCI_BRIDGE_RESOURCES)
1124 continue;
1125 r = &dev->resource[i];
1126 r_size = r->end - r->start;
1127 if (r_size < 0xfff)
1128 r_size = 0xfff;
1129 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1130 rc = 1;
1131 push_end(res, r_size);
1132 }
1133 }
1134 }
1135
1136 return rc;
1137}
1138
1139/* Here we scan all P2P bridges of a given level that have a closed
1140 * IO window. Note that the test for the presence of a VGA card should
1141 * be improved to take into account already configured P2P bridges,
1142 * currently, we don't see them and might end up configuring 2 bridges
1143 * with VGA pass through enabled
1144 */
1145static void __init
1146do_fixup_p2p_level(struct pci_bus *bus)
1147{
1148 struct pci_bus *b;
1149 int i, parent_io;
1150 int has_vga = 0;
1151
1152 for (parent_io=0; parent_io<4; parent_io++)
1153 if (bus->resource[parent_io]
1154 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1155 break;
1156 if (parent_io >= 4)
1157 return;
1158
1159 list_for_each_entry(b, &bus->children, node) {
1160 struct pci_dev *d = b->self;
1161 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1162 struct resource *res = b->resource[0];
1163 struct resource tmp_res;
1164 unsigned long max;
1165 int found_vga = 0;
1166
1167 memset(&tmp_res, 0, sizeof(tmp_res));
1168 tmp_res.start = bus->resource[parent_io]->start;
1169
1170 /* We don't let low addresses go through that closed P2P bridge, well,
1171 * that may not be necessary but I feel safer that way
1172 */
1173 if (tmp_res.start == 0)
1174 tmp_res.start = 0x1000;
1175
1176 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1177 res != bus->resource[parent_io] &&
1178 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1179 check_for_io_childs(b, &tmp_res, &found_vga)) {
1180 u8 io_base_lo;
1181
1182 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1183
1184 if (found_vga) {
1185 if (has_vga) {
1186 printk(KERN_WARNING "Skipping VGA, already active"
1187 " on bus segment\n");
1188 found_vga = 0;
1189 } else
1190 has_vga = 1;
1191 }
1192 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1193
1194 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1195 max = ((unsigned long) hose->io_base_virt
1196 - isa_io_base) + 0xffffffff;
1197 else
1198 max = ((unsigned long) hose->io_base_virt
1199 - isa_io_base) + 0xffff;
1200
1201 *res = tmp_res;
1202 res->flags = IORESOURCE_IO;
1203 res->name = b->name;
1204
1205 /* Find a resource in the parent where we can allocate */
1206 for (i = 0 ; i < 4; i++) {
1207 struct resource *r = bus->resource[i];
1208 if (!r)
1209 continue;
1210 if ((r->flags & IORESOURCE_IO) == 0)
1211 continue;
1212 DBG("Trying to allocate from %08lx, size %08lx from parent"
1213 " res %d: %08lx -> %08lx\n",
1214 res->start, res->end, i, r->start, r->end);
1215
1216 if (allocate_resource(r, res, res->end + 1, res->start, max,
1217 res->end + 1, NULL, NULL) < 0) {
1218 DBG("Failed !\n");
1219 continue;
1220 }
1221 do_update_p2p_io_resource(b, found_vga);
1222 break;
1223 }
1224 }
1225 do_fixup_p2p_level(b);
1226 }
1227}
1228
1229static void
1230pcibios_fixup_p2p_bridges(void)
1231{
1232 struct pci_bus *b;
1233
1234 list_for_each_entry(b, &pci_root_buses, node)
1235 do_fixup_p2p_level(b);
1236}
1237
1238#endif /* CONFIG_PPC_PMAC */
1239
1240static int __init
1241pcibios_init(void)
1242{
1243 struct pci_controller *hose;
1244 struct pci_bus *bus;
1245 int next_busno;
1246
1247 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1248
1249 /* Scan all of the recorded PCI controllers. */
1250 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1251 if (pci_assign_all_busses)
1252 hose->first_busno = next_busno;
1253 hose->last_busno = 0xff;
1254 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1255 hose->last_busno = bus->subordinate;
1256 if (pci_assign_all_busses || next_busno <= hose->last_busno)
1257 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1258 }
1259 pci_bus_count = next_busno;
1260
1261 /* OpenFirmware based machines need a map of OF bus
1262 * numbers vs. kernel bus numbers since we may have to
1263 * remap them.
1264 */
1265 if (pci_assign_all_busses && have_of)
1266 pcibios_make_OF_bus_map();
1267
1268 /* Do machine dependent PCI interrupt routing */
1269 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1270 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1271
1272 /* Call machine dependent fixup */
1273 if (ppc_md.pcibios_fixup)
1274 ppc_md.pcibios_fixup();
1275
1276 /* Allocate and assign resources */
1277 pcibios_allocate_bus_resources(&pci_root_buses);
1278 pcibios_allocate_resources(0);
1279 pcibios_allocate_resources(1);
1280#ifdef CONFIG_PPC_PMAC
1281 pcibios_fixup_p2p_bridges();
1282#endif /* CONFIG_PPC_PMAC */
1283 pcibios_assign_resources();
1284
1285 /* Call machine dependent post-init code */
1286 if (ppc_md.pcibios_after_init)
1287 ppc_md.pcibios_after_init();
1288
1289 return 0;
1290}
1291
1292subsys_initcall(pcibios_init);
1293
1294unsigned char __init
1295common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1296{
1297 struct pci_controller *hose = dev->sysdata;
1298
1299 if (dev->bus->number != hose->first_busno) {
1300 u8 pin = *pinp;
1301 do {
1302 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1303 /* Move up the chain of bridges. */
1304 dev = dev->bus->self;
1305 } while (dev->bus->self);
1306 *pinp = pin;
1307
1308 /* The slot is the idsel of the last bridge. */
1309 }
1310 return PCI_SLOT(dev->devfn);
1311}
1312
1313unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1314 unsigned long start, unsigned long size)
1315{
1316 return start;
1317}
1318
1319void __init pcibios_fixup_bus(struct pci_bus *bus)
1320{
1321 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1322 unsigned long io_offset;
1323 struct resource *res;
1324 int i;
1325
1326 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1327 if (bus->parent == NULL) {
1328 /* This is a host bridge - fill in its resources */
1329 hose->bus = bus;
1330
1331 bus->resource[0] = res = &hose->io_resource;
1332 if (!res->flags) {
1333 if (io_offset)
1334 printk(KERN_ERR "I/O resource not set for host"
1335 " bridge %d\n", hose->index);
1336 res->start = 0;
1337 res->end = IO_SPACE_LIMIT;
1338 res->flags = IORESOURCE_IO;
1339 }
1340 res->start += io_offset;
1341 res->end += io_offset;
1342
1343 for (i = 0; i < 3; ++i) {
1344 res = &hose->mem_resources[i];
1345 if (!res->flags) {
1346 if (i > 0)
1347 continue;
1348 printk(KERN_ERR "Memory resource not set for "
1349 "host bridge %d\n", hose->index);
1350 res->start = hose->pci_mem_offset;
1351 res->end = ~0U;
1352 res->flags = IORESOURCE_MEM;
1353 }
1354 bus->resource[i+1] = res;
1355 }
1356 } else {
1357 /* This is a subordinate bridge */
1358 pci_read_bridge_bases(bus);
1359
1360 for (i = 0; i < 4; ++i) {
1361 if ((res = bus->resource[i]) == NULL)
1362 continue;
1363 if (!res->flags)
1364 continue;
1365 if (io_offset && (res->flags & IORESOURCE_IO)) {
1366 res->start += io_offset;
1367 res->end += io_offset;
1368 } else if (hose->pci_mem_offset
1369 && (res->flags & IORESOURCE_MEM)) {
1370 res->start += hose->pci_mem_offset;
1371 res->end += hose->pci_mem_offset;
1372 }
1373 }
1374 }
1375
1376 if (ppc_md.pcibios_fixup_bus)
1377 ppc_md.pcibios_fixup_bus(bus);
1378}
1379
1380char __init *pcibios_setup(char *str)
1381{
1382 return str;
1383}
1384
1385/* the next one is stolen from the alpha port... */
1386void __init
1387pcibios_update_irq(struct pci_dev *dev, int irq)
1388{
1389 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1390 /* XXX FIXME - update OF device tree node interrupt property */
1391}
1392
1393int pcibios_enable_device(struct pci_dev *dev, int mask)
1394{
1395 u16 cmd, old_cmd;
1396 int idx;
1397 struct resource *r;
1398
1399 if (ppc_md.pcibios_enable_device_hook)
1400 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1401 return -EINVAL;
1402
1403 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1404 old_cmd = cmd;
1405 for (idx=0; idx<6; idx++) {
1406 r = &dev->resource[idx];
1407 if (r->flags & IORESOURCE_UNSET) {
1408 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1409 return -EINVAL;
1410 }
1411 if (r->flags & IORESOURCE_IO)
1412 cmd |= PCI_COMMAND_IO;
1413 if (r->flags & IORESOURCE_MEM)
1414 cmd |= PCI_COMMAND_MEMORY;
1415 }
1416 if (cmd != old_cmd) {
1417 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1418 pci_name(dev), old_cmd, cmd);
1419 pci_write_config_word(dev, PCI_COMMAND, cmd);
1420 }
1421 return 0;
1422}
1423
1424struct pci_controller*
1425pci_bus_to_hose(int bus)
1426{
1427 struct pci_controller* hose = hose_head;
1428
1429 for (; hose; hose = hose->next)
1430 if (bus >= hose->first_busno && bus <= hose->last_busno)
1431 return hose;
1432 return NULL;
1433}
1434
1435void*
1436pci_bus_io_base(unsigned int bus)
1437{
1438 struct pci_controller *hose;
1439
1440 hose = pci_bus_to_hose(bus);
1441 if (!hose)
1442 return NULL;
1443 return hose->io_base_virt;
1444}
1445
1446unsigned long
1447pci_bus_io_base_phys(unsigned int bus)
1448{
1449 struct pci_controller *hose;
1450
1451 hose = pci_bus_to_hose(bus);
1452 if (!hose)
1453 return 0;
1454 return hose->io_base_phys;
1455}
1456
1457unsigned long
1458pci_bus_mem_base_phys(unsigned int bus)
1459{
1460 struct pci_controller *hose;
1461
1462 hose = pci_bus_to_hose(bus);
1463 if (!hose)
1464 return 0;
1465 return hose->pci_mem_offset;
1466}
1467
1468unsigned long
1469pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1470{
1471 /* Hack alert again ! See comments in chrp_pci.c
1472 */
1473 struct pci_controller* hose =
1474 (struct pci_controller *)pdev->sysdata;
1475 if (hose && res->flags & IORESOURCE_MEM)
1476 return res->start - hose->pci_mem_offset;
1477 /* We may want to do something with IOs here... */
1478 return res->start;
1479}
1480
1481
1482static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1483 unsigned long *offset,
1484 enum pci_mmap_state mmap_state)
1485{
1486 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1487 unsigned long io_offset = 0;
1488 int i, res_bit;
1489
1490 if (hose == 0)
1491 return NULL; /* should never happen */
1492
1493 /* If memory, add on the PCI bridge address offset */
1494 if (mmap_state == pci_mmap_mem) {
1495 *offset += hose->pci_mem_offset;
1496 res_bit = IORESOURCE_MEM;
1497 } else {
1498 io_offset = (unsigned long)hose->io_base_virt;
1499 *offset += io_offset;
1500 res_bit = IORESOURCE_IO;
1501 }
1502
1503 /*
1504 * Check that the offset requested corresponds to one of the
1505 * resources of the device.
1506 */
1507 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1508 struct resource *rp = &dev->resource[i];
1509 int flags = rp->flags;
1510
1511 /* treat ROM as memory (should be already) */
1512 if (i == PCI_ROM_RESOURCE)
1513 flags |= IORESOURCE_MEM;
1514
1515 /* Active and same type? */
1516 if ((flags & res_bit) == 0)
1517 continue;
1518
1519 /* In the range of this resource? */
1520 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1521 continue;
1522
1523 /* found it! construct the final physical address */
1524 if (mmap_state == pci_mmap_io)
1525 *offset += hose->io_base_phys - _IO_BASE;
1526 return rp;
1527 }
1528
1529 return NULL;
1530}
1531
1532/*
1533 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1534 * device mapping.
1535 */
1536static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1537 pgprot_t protection,
1538 enum pci_mmap_state mmap_state,
1539 int write_combine)
1540{
1541 unsigned long prot = pgprot_val(protection);
1542
1543 /* Write combine is always 0 on non-memory space mappings. On
1544 * memory space, if the user didn't pass 1, we check for a
1545 * "prefetchable" resource. This is a bit hackish, but we use
1546 * this to workaround the inability of /sysfs to provide a write
1547 * combine bit
1548 */
1549 if (mmap_state != pci_mmap_mem)
1550 write_combine = 0;
1551 else if (write_combine == 0) {
1552 if (rp->flags & IORESOURCE_PREFETCH)
1553 write_combine = 1;
1554 }
1555
1556 /* XXX would be nice to have a way to ask for write-through */
1557 prot |= _PAGE_NO_CACHE;
1558 if (write_combine)
1559 prot &= ~_PAGE_GUARDED;
1560 else
1561 prot |= _PAGE_GUARDED;
1562
1563 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
1564 prot);
1565
1566 return __pgprot(prot);
1567}
1568
1569/*
1570 * This one is used by /dev/mem and fbdev who have no clue about the
1571 * PCI device, it tries to find the PCI device first and calls the
1572 * above routine
1573 */
1574pgprot_t pci_phys_mem_access_prot(struct file *file,
1575 unsigned long offset,
1576 unsigned long size,
1577 pgprot_t protection)
1578{
1579 struct pci_dev *pdev = NULL;
1580 struct resource *found = NULL;
1581 unsigned long prot = pgprot_val(protection);
1582 int i;
1583
1584 if (page_is_ram(offset >> PAGE_SHIFT))
1585 return prot;
1586
1587 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1588
1589 for_each_pci_dev(pdev) {
1590 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1591 struct resource *rp = &pdev->resource[i];
1592 int flags = rp->flags;
1593
1594 /* Active and same type? */
1595 if ((flags & IORESOURCE_MEM) == 0)
1596 continue;
1597 /* In the range of this resource? */
1598 if (offset < (rp->start & PAGE_MASK) ||
1599 offset > rp->end)
1600 continue;
1601 found = rp;
1602 break;
1603 }
1604 if (found)
1605 break;
1606 }
1607 if (found) {
1608 if (found->flags & IORESOURCE_PREFETCH)
1609 prot &= ~_PAGE_GUARDED;
1610 pci_dev_put(pdev);
1611 }
1612
1613 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1614
1615 return __pgprot(prot);
1616}
1617
1618
1619/*
1620 * Perform the actual remap of the pages for a PCI device mapping, as
1621 * appropriate for this architecture. The region in the process to map
1622 * is described by vm_start and vm_end members of VMA, the base physical
1623 * address is found in vm_pgoff.
1624 * The pci device structure is provided so that architectures may make mapping
1625 * decisions on a per-device or per-bus basis.
1626 *
1627 * Returns a negative error code on failure, zero on success.
1628 */
1629int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1630 enum pci_mmap_state mmap_state,
1631 int write_combine)
1632{
1633 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1634 struct resource *rp;
1635 int ret;
1636
1637 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1638 if (rp == NULL)
1639 return -EINVAL;
1640
1641 vma->vm_pgoff = offset >> PAGE_SHIFT;
1642 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1643 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1644 vma->vm_page_prot,
1645 mmap_state, write_combine);
1646
1647 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1648 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1649
1650 return ret;
1651}
1652
1653/* Obsolete functions. Should be removed once the symbios driver
1654 * is fixed
1655 */
1656unsigned long
1657phys_to_bus(unsigned long pa)
1658{
1659 struct pci_controller *hose;
1660 int i;
1661
1662 for (hose = hose_head; hose; hose = hose->next) {
1663 for (i = 0; i < 3; ++i) {
1664 if (pa >= hose->mem_resources[i].start
1665 && pa <= hose->mem_resources[i].end) {
1666 /*
1667 * XXX the hose->pci_mem_offset really
1668 * only applies to mem_resources[0].
1669 * We need a way to store an offset for
1670 * the others. -- paulus
1671 */
1672 if (i == 0)
1673 pa -= hose->pci_mem_offset;
1674 return pa;
1675 }
1676 }
1677 }
1678 /* hmmm, didn't find it */
1679 return 0;
1680}
1681
1682unsigned long
1683pci_phys_to_bus(unsigned long pa, int busnr)
1684{
1685 struct pci_controller* hose = pci_bus_to_hose(busnr);
1686 if (!hose)
1687 return pa;
1688 return pa - hose->pci_mem_offset;
1689}
1690
1691unsigned long
1692pci_bus_to_phys(unsigned int ba, int busnr)
1693{
1694 struct pci_controller* hose = pci_bus_to_hose(busnr);
1695 if (!hose)
1696 return ba;
1697 return ba + hose->pci_mem_offset;
1698}
1699
1700/* Provide information on locations of various I/O regions in physical
1701 * memory. Do this on a per-card basis so that we choose the right
1702 * root bridge.
1703 * Note that the returned IO or memory base is a physical address
1704 */
1705
1706long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1707{
1708 struct pci_controller* hose;
1709 long result = -EOPNOTSUPP;
1710
1711 /* Argh ! Please forgive me for that hack, but that's the
1712 * simplest way to get existing XFree to not lockup on some
1713 * G5 machines... So when something asks for bus 0 io base
1714 * (bus 0 is HT root), we return the AGP one instead.
1715 */
1716#ifdef CONFIG_PPC_PMAC
1717 if (_machine == _MACH_Pmac && machine_is_compatible("MacRISC4"))
1718 if (bus == 0)
1719 bus = 0xf0;
1720#endif /* CONFIG_PPC_PMAC */
1721
1722 hose = pci_bus_to_hose(bus);
1723 if (!hose)
1724 return -ENODEV;
1725
1726 switch (which) {
1727 case IOBASE_BRIDGE_NUMBER:
1728 return (long)hose->first_busno;
1729 case IOBASE_MEMORY:
1730 return (long)hose->pci_mem_offset;
1731 case IOBASE_IO:
1732 return (long)hose->io_base_phys;
1733 case IOBASE_ISA_IO:
1734 return (long)isa_io_base;
1735 case IOBASE_ISA_MEM:
1736 return (long)isa_mem_base;
1737 }
1738
1739 return result;
1740}
1741
1742void __init
1743pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1744 int flags, char *name)
1745{
1746 res->start = start;
1747 res->end = end;
1748 res->flags = flags;
1749 res->name = name;
1750 res->parent = NULL;
1751 res->sibling = NULL;
1752 res->child = NULL;
1753}
1754
1755void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1756{
1757 unsigned long start = pci_resource_start(dev, bar);
1758 unsigned long len = pci_resource_len(dev, bar);
1759 unsigned long flags = pci_resource_flags(dev, bar);
1760
1761 if (!len)
1762 return NULL;
1763 if (max && len > max)
1764 len = max;
1765 if (flags & IORESOURCE_IO)
1766 return ioport_map(start, len);
1767 if (flags & IORESOURCE_MEM)
1768 /* Not checking IORESOURCE_CACHEABLE because PPC does
1769 * not currently distinguish between ioremap and
1770 * ioremap_nocache.
1771 */
1772 return ioremap(start, len);
1773 /* What? */
1774 return NULL;
1775}
1776
1777void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1778{
1779 /* Nothing to do */
1780}
1781EXPORT_SYMBOL(pci_iomap);
1782EXPORT_SYMBOL(pci_iounmap);
1783
1784
1785/*
1786 * Null PCI config access functions, for the case when we can't
1787 * find a hose.
1788 */
1789#define NULL_PCI_OP(rw, size, type) \
1790static int \
1791null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1792{ \
1793 return PCIBIOS_DEVICE_NOT_FOUND; \
1794}
1795
1796static int
1797null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1798 int len, u32 *val)
1799{
1800 return PCIBIOS_DEVICE_NOT_FOUND;
1801}
1802
1803static int
1804null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1805 int len, u32 val)
1806{
1807 return PCIBIOS_DEVICE_NOT_FOUND;
1808}
1809
1810static struct pci_ops null_pci_ops =
1811{
1812 null_read_config,
1813 null_write_config
1814};
1815
1816/*
1817 * These functions are used early on before PCI scanning is done
1818 * and all of the pci_dev and pci_bus structures have been created.
1819 */
1820static struct pci_bus *
1821fake_pci_bus(struct pci_controller *hose, int busnr)
1822{
1823 static struct pci_bus bus;
1824
1825 if (hose == 0) {
1826 hose = pci_bus_to_hose(busnr);
1827 if (hose == 0)
1828 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1829 }
1830 bus.number = busnr;
1831 bus.sysdata = hose;
1832 bus.ops = hose? hose->ops: &null_pci_ops;
1833 return &bus;
1834}
1835
1836#define EARLY_PCI_OP(rw, size, type) \
1837int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1838 int devfn, int offset, type value) \
1839{ \
1840 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1841 devfn, offset, value); \
1842}
1843
1844EARLY_PCI_OP(read, byte, u8 *)
1845EARLY_PCI_OP(read, word, u16 *)
1846EARLY_PCI_OP(read, dword, u32 *)
1847EARLY_PCI_OP(write, byte, u8)
1848EARLY_PCI_OP(write, word, u16)
1849EARLY_PCI_OP(write, dword, u32)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 19:54:35 -0500