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-rw-r--r--arch/ppc/kernel/pci.c1233
1 files changed, 0 insertions, 1233 deletions
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
deleted file mode 100644
index df3ef6db072c..000000000000
--- a/arch/ppc/kernel/pci.c
+++ /dev/null
@@ -1,1233 +0,0 @@
1/*
2 * Common prep/chrp pci routines. -- Cort
3 */
4
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/delay.h>
8#include <linux/string.h>
9#include <linux/init.h>
10#include <linux/capability.h>
11#include <linux/sched.h>
12#include <linux/errno.h>
13#include <linux/bootmem.h>
14
15#include <asm/processor.h>
16#include <asm/io.h>
17#include <asm/prom.h>
18#include <asm/sections.h>
19#include <asm/pci-bridge.h>
20#include <asm/byteorder.h>
21#include <asm/irq.h>
22#include <asm/uaccess.h>
23#include <asm/machdep.h>
24
25#undef DEBUG
26
27#ifdef DEBUG
28#define DBG(x...) printk(x)
29#else
30#define DBG(x...)
31#endif
32
33unsigned long isa_io_base = 0;
34unsigned long isa_mem_base = 0;
35unsigned long pci_dram_offset = 0;
36int pcibios_assign_bus_offset = 1;
37
38void pcibios_make_OF_bus_map(void);
39
40static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43static void update_bridge_base(struct pci_bus *bus, int i);
44static void pcibios_fixup_resources(struct pci_dev* dev);
45static void fixup_broken_pcnet32(struct pci_dev* dev);
46static int reparent_resources(struct resource *parent, struct resource *res);
47static void fixup_cpc710_pci64(struct pci_dev* dev);
48
49/* By default, we don't re-assign bus numbers.
50 */
51int pci_assign_all_buses;
52
53struct pci_controller* hose_head;
54struct pci_controller** hose_tail = &hose_head;
55
56static int pci_bus_count;
57
58static void
59fixup_broken_pcnet32(struct pci_dev* dev)
60{
61 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
62 dev->vendor = PCI_VENDOR_ID_AMD;
63 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
64 }
65}
66DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
67
68static void
69fixup_cpc710_pci64(struct pci_dev* dev)
70{
71 /* Hide the PCI64 BARs from the kernel as their content doesn't
72 * fit well in the resource management
73 */
74 dev->resource[0].start = dev->resource[0].end = 0;
75 dev->resource[0].flags = 0;
76 dev->resource[1].start = dev->resource[1].end = 0;
77 dev->resource[1].flags = 0;
78}
79DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
80
81static void
82pcibios_fixup_resources(struct pci_dev *dev)
83{
84 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
85 int i;
86 unsigned long offset;
87
88 if (!hose) {
89 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
90 return;
91 }
92 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
93 struct resource *res = dev->resource + i;
94 if (!res->flags)
95 continue;
96 if (res->end == 0xffffffff) {
97 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
98 pci_name(dev), i,
99 (unsigned long long)res->start,
100 (unsigned long long)res->end);
101 res->end -= res->start;
102 res->start = 0;
103 res->flags |= IORESOURCE_UNSET;
104 continue;
105 }
106 offset = 0;
107 if (res->flags & IORESOURCE_MEM) {
108 offset = hose->pci_mem_offset;
109 } else if (res->flags & IORESOURCE_IO) {
110 offset = (unsigned long) hose->io_base_virt
111 - isa_io_base;
112 }
113 if (offset != 0) {
114 res->start += offset;
115 res->end += offset;
116#ifdef DEBUG
117 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
118 i, res->flags, pci_name(dev),
119 res->start - offset, res->start);
120#endif
121 }
122 }
123
124 /* Call machine specific resource fixup */
125 if (ppc_md.pcibios_fixup_resources)
126 ppc_md.pcibios_fixup_resources(dev);
127}
128DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
129
130void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
131 struct resource *res)
132{
133 unsigned long offset = 0;
134 struct pci_controller *hose = dev->sysdata;
135
136 if (hose && res->flags & IORESOURCE_IO)
137 offset = (unsigned long)hose->io_base_virt - isa_io_base;
138 else if (hose && res->flags & IORESOURCE_MEM)
139 offset = hose->pci_mem_offset;
140 region->start = res->start - offset;
141 region->end = res->end - offset;
142}
143EXPORT_SYMBOL(pcibios_resource_to_bus);
144
145void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
146 struct pci_bus_region *region)
147{
148 unsigned long offset = 0;
149 struct pci_controller *hose = dev->sysdata;
150
151 if (hose && res->flags & IORESOURCE_IO)
152 offset = (unsigned long)hose->io_base_virt - isa_io_base;
153 else if (hose && res->flags & IORESOURCE_MEM)
154 offset = hose->pci_mem_offset;
155 res->start = region->start + offset;
156 res->end = region->end + offset;
157}
158EXPORT_SYMBOL(pcibios_bus_to_resource);
159
160/*
161 * We need to avoid collisions with `mirrored' VGA ports
162 * and other strange ISA hardware, so we always want the
163 * addresses to be allocated in the 0x000-0x0ff region
164 * modulo 0x400.
165 *
166 * Why? Because some silly external IO cards only decode
167 * the low 10 bits of the IO address. The 0x00-0xff region
168 * is reserved for motherboard devices that decode all 16
169 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
170 * but we want to try to avoid allocating at 0x2900-0x2bff
171 * which might have be mirrored at 0x0100-0x03ff..
172 */
173void pcibios_align_resource(void *data, struct resource *res,
174 resource_size_t size, resource_size_t align)
175{
176 struct pci_dev *dev = data;
177
178 if (res->flags & IORESOURCE_IO) {
179 resource_size_t start = res->start;
180
181 if (size > 0x100) {
182 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
183 " (%lld bytes)\n", pci_name(dev),
184 dev->resource - res, (unsigned long long)size);
185 }
186
187 if (start & 0x300) {
188 start = (start + 0x3ff) & ~0x3ff;
189 res->start = start;
190 }
191 }
192}
193EXPORT_SYMBOL(pcibios_align_resource);
194
195/*
196 * Handle resources of PCI devices. If the world were perfect, we could
197 * just allocate all the resource regions and do nothing more. It isn't.
198 * On the other hand, we cannot just re-allocate all devices, as it would
199 * require us to know lots of host bridge internals. So we attempt to
200 * keep as much of the original configuration as possible, but tweak it
201 * when it's found to be wrong.
202 *
203 * Known BIOS problems we have to work around:
204 * - I/O or memory regions not configured
205 * - regions configured, but not enabled in the command register
206 * - bogus I/O addresses above 64K used
207 * - expansion ROMs left enabled (this may sound harmless, but given
208 * the fact the PCI specs explicitly allow address decoders to be
209 * shared between expansion ROMs and other resource regions, it's
210 * at least dangerous)
211 *
212 * Our solution:
213 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
214 * This gives us fixed barriers on where we can allocate.
215 * (2) Allocate resources for all enabled devices. If there is
216 * a collision, just mark the resource as unallocated. Also
217 * disable expansion ROMs during this step.
218 * (3) Try to allocate resources for disabled devices. If the
219 * resources were assigned correctly, everything goes well,
220 * if they weren't, they won't disturb allocation of other
221 * resources.
222 * (4) Assign new addresses to resources which were either
223 * not configured at all or misconfigured. If explicitly
224 * requested by the user, configure expansion ROM address
225 * as well.
226 */
227
228static void __init
229pcibios_allocate_bus_resources(struct list_head *bus_list)
230{
231 struct pci_bus *bus;
232 int i;
233 struct resource *res, *pr;
234
235 /* Depth-First Search on bus tree */
236 list_for_each_entry(bus, bus_list, node) {
237 for (i = 0; i < 4; ++i) {
238 if ((res = bus->resource[i]) == NULL || !res->flags
239 || res->start > res->end)
240 continue;
241 if (bus->parent == NULL)
242 pr = (res->flags & IORESOURCE_IO)?
243 &ioport_resource: &iomem_resource;
244 else {
245 pr = pci_find_parent_resource(bus->self, res);
246 if (pr == res) {
247 /* this happens when the generic PCI
248 * code (wrongly) decides that this
249 * bridge is transparent -- paulus
250 */
251 continue;
252 }
253 }
254
255 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
256 (unsigned long long)res->start,
257 (unsigned long long)res->end, res->flags, pr);
258 if (pr) {
259 if (request_resource(pr, res) == 0)
260 continue;
261 /*
262 * Must be a conflict with an existing entry.
263 * Move that entry (or entries) under the
264 * bridge resource and try again.
265 */
266 if (reparent_resources(pr, res) == 0)
267 continue;
268 }
269 printk(KERN_ERR "PCI: Cannot allocate resource region "
270 "%d of PCI bridge %d\n", i, bus->number);
271 if (pci_relocate_bridge_resource(bus, i))
272 bus->resource[i] = NULL;
273 }
274 pcibios_allocate_bus_resources(&bus->children);
275 }
276}
277
278/*
279 * Reparent resource children of pr that conflict with res
280 * under res, and make res replace those children.
281 */
282static int __init
283reparent_resources(struct resource *parent, struct resource *res)
284{
285 struct resource *p, **pp;
286 struct resource **firstpp = NULL;
287
288 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
289 if (p->end < res->start)
290 continue;
291 if (res->end < p->start)
292 break;
293 if (p->start < res->start || p->end > res->end)
294 return -1; /* not completely contained */
295 if (firstpp == NULL)
296 firstpp = pp;
297 }
298 if (firstpp == NULL)
299 return -1; /* didn't find any conflicting entries? */
300 res->parent = parent;
301 res->child = *firstpp;
302 res->sibling = *pp;
303 *firstpp = res;
304 *pp = NULL;
305 for (p = res->child; p != NULL; p = p->sibling) {
306 p->parent = res;
307 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
308 p->name, (unsigned long long)p->start,
309 (unsigned long long)p->end, res->name);
310 }
311 return 0;
312}
313
314/*
315 * A bridge has been allocated a range which is outside the range
316 * of its parent bridge, so it needs to be moved.
317 */
318static int __init
319pci_relocate_bridge_resource(struct pci_bus *bus, int i)
320{
321 struct resource *res, *pr, *conflict;
322 unsigned long try, size;
323 int j;
324 struct pci_bus *parent = bus->parent;
325
326 if (parent == NULL) {
327 /* shouldn't ever happen */
328 printk(KERN_ERR "PCI: can't move host bridge resource\n");
329 return -1;
330 }
331 res = bus->resource[i];
332 if (res == NULL)
333 return -1;
334 pr = NULL;
335 for (j = 0; j < 4; j++) {
336 struct resource *r = parent->resource[j];
337 if (!r)
338 continue;
339 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
340 continue;
341 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
342 pr = r;
343 break;
344 }
345 if (res->flags & IORESOURCE_PREFETCH)
346 pr = r;
347 }
348 if (pr == NULL)
349 return -1;
350 size = res->end - res->start;
351 if (pr->start > pr->end || size > pr->end - pr->start)
352 return -1;
353 try = pr->end;
354 for (;;) {
355 res->start = try - size;
356 res->end = try;
357 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
358 break;
359 if (conflict->start <= pr->start + size)
360 return -1;
361 try = conflict->start - 1;
362 }
363 if (request_resource(pr, res)) {
364 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
365 (unsigned long long)res->start,
366 (unsigned long long)res->end);
367 return -1; /* "can't happen" */
368 }
369 update_bridge_base(bus, i);
370 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
371 bus->number, i, (unsigned long long)res->start,
372 (unsigned long long)res->end);
373 return 0;
374}
375
376static int __init
377probe_resource(struct pci_bus *parent, struct resource *pr,
378 struct resource *res, struct resource **conflict)
379{
380 struct pci_bus *bus;
381 struct pci_dev *dev;
382 struct resource *r;
383 int i;
384
385 for (r = pr->child; r != NULL; r = r->sibling) {
386 if (r->end >= res->start && res->end >= r->start) {
387 *conflict = r;
388 return 1;
389 }
390 }
391 list_for_each_entry(bus, &parent->children, node) {
392 for (i = 0; i < 4; ++i) {
393 if ((r = bus->resource[i]) == NULL)
394 continue;
395 if (!r->flags || r->start > r->end || r == res)
396 continue;
397 if (pci_find_parent_resource(bus->self, r) != pr)
398 continue;
399 if (r->end >= res->start && res->end >= r->start) {
400 *conflict = r;
401 return 1;
402 }
403 }
404 }
405 list_for_each_entry(dev, &parent->devices, bus_list) {
406 for (i = 0; i < 6; ++i) {
407 r = &dev->resource[i];
408 if (!r->flags || (r->flags & IORESOURCE_UNSET))
409 continue;
410 if (pci_find_parent_resource(dev, r) != pr)
411 continue;
412 if (r->end >= res->start && res->end >= r->start) {
413 *conflict = r;
414 return 1;
415 }
416 }
417 }
418 return 0;
419}
420
421static void __init
422update_bridge_base(struct pci_bus *bus, int i)
423{
424 struct resource *res = bus->resource[i];
425 u8 io_base_lo, io_limit_lo;
426 u16 mem_base, mem_limit;
427 u16 cmd;
428 unsigned long start, end, off;
429 struct pci_dev *dev = bus->self;
430 struct pci_controller *hose = dev->sysdata;
431
432 if (!hose) {
433 printk("update_bridge_base: no hose?\n");
434 return;
435 }
436 pci_read_config_word(dev, PCI_COMMAND, &cmd);
437 pci_write_config_word(dev, PCI_COMMAND,
438 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
439 if (res->flags & IORESOURCE_IO) {
440 off = (unsigned long) hose->io_base_virt - isa_io_base;
441 start = res->start - off;
442 end = res->end - off;
443 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
444 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
445 if (end > 0xffff) {
446 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
447 start >> 16);
448 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
449 end >> 16);
450 io_base_lo |= PCI_IO_RANGE_TYPE_32;
451 } else
452 io_base_lo |= PCI_IO_RANGE_TYPE_16;
453 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
454 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
455
456 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
457 == IORESOURCE_MEM) {
458 off = hose->pci_mem_offset;
459 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
460 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
461 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
462 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
463
464 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
465 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
466 off = hose->pci_mem_offset;
467 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
468 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
469 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
470 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
471
472 } else {
473 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
474 pci_name(dev), i, res->flags);
475 }
476 pci_write_config_word(dev, PCI_COMMAND, cmd);
477}
478
479static inline void alloc_resource(struct pci_dev *dev, int idx)
480{
481 struct resource *pr, *r = &dev->resource[idx];
482
483 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
484 pci_name(dev), idx, (unsigned long long)r->start,
485 (unsigned long long)r->end, r->flags);
486 pr = pci_find_parent_resource(dev, r);
487 if (!pr || request_resource(pr, r) < 0) {
488 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
489 " of device %s\n", idx, pci_name(dev));
490 if (pr)
491 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
492 pr, (unsigned long long)pr->start,
493 (unsigned long long)pr->end, pr->flags);
494 /* We'll assign a new address later */
495 r->flags |= IORESOURCE_UNSET;
496 r->end -= r->start;
497 r->start = 0;
498 }
499}
500
501static void __init
502pcibios_allocate_resources(int pass)
503{
504 struct pci_dev *dev = NULL;
505 int idx, disabled;
506 u16 command;
507 struct resource *r;
508
509 for_each_pci_dev(dev) {
510 pci_read_config_word(dev, PCI_COMMAND, &command);
511 for (idx = 0; idx < 6; idx++) {
512 r = &dev->resource[idx];
513 if (r->parent) /* Already allocated */
514 continue;
515 if (!r->flags || (r->flags & IORESOURCE_UNSET))
516 continue; /* Not assigned at all */
517 if (r->flags & IORESOURCE_IO)
518 disabled = !(command & PCI_COMMAND_IO);
519 else
520 disabled = !(command & PCI_COMMAND_MEMORY);
521 if (pass == disabled)
522 alloc_resource(dev, idx);
523 }
524 if (pass)
525 continue;
526 r = &dev->resource[PCI_ROM_RESOURCE];
527 if (r->flags & IORESOURCE_ROM_ENABLE) {
528 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
529 u32 reg;
530 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
531 r->flags &= ~IORESOURCE_ROM_ENABLE;
532 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
533 pci_write_config_dword(dev, dev->rom_base_reg,
534 reg & ~PCI_ROM_ADDRESS_ENABLE);
535 }
536 }
537}
538
539static void __init
540pcibios_assign_resources(void)
541{
542 struct pci_dev *dev = NULL;
543 int idx;
544 struct resource *r;
545
546 for_each_pci_dev(dev) {
547 int class = dev->class >> 8;
548
549 /* Don't touch classless devices and host bridges */
550 if (!class || class == PCI_CLASS_BRIDGE_HOST)
551 continue;
552
553 for (idx = 0; idx < 6; idx++) {
554 r = &dev->resource[idx];
555
556 /*
557 * We shall assign a new address to this resource,
558 * either because the BIOS (sic) forgot to do so
559 * or because we have decided the old address was
560 * unusable for some reason.
561 */
562 if ((r->flags & IORESOURCE_UNSET) && r->end &&
563 (!ppc_md.pcibios_enable_device_hook ||
564 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
565 r->flags &= ~IORESOURCE_UNSET;
566 pci_assign_resource(dev, idx);
567 }
568 }
569
570#if 0 /* don't assign ROMs */
571 r = &dev->resource[PCI_ROM_RESOURCE];
572 r->end -= r->start;
573 r->start = 0;
574 if (r->end)
575 pci_assign_resource(dev, PCI_ROM_RESOURCE);
576#endif
577 }
578}
579
580
581static int next_controller_index;
582
583struct pci_controller * __init
584pcibios_alloc_controller(void)
585{
586 struct pci_controller *hose;
587
588 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
589 memset(hose, 0, sizeof(struct pci_controller));
590
591 *hose_tail = hose;
592 hose_tail = &hose->next;
593
594 hose->index = next_controller_index++;
595
596 return hose;
597}
598
599void pcibios_make_OF_bus_map(void)
600{
601}
602
603static int __init
604pcibios_init(void)
605{
606 struct pci_controller *hose;
607 struct pci_bus *bus;
608 int next_busno;
609
610 printk(KERN_INFO "PCI: Probing PCI hardware\n");
611
612 /* Scan all of the recorded PCI controllers. */
613 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
614 if (pci_assign_all_buses)
615 hose->first_busno = next_busno;
616 hose->last_busno = 0xff;
617 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
618 hose->last_busno = bus->subordinate;
619 if (pci_assign_all_buses || next_busno <= hose->last_busno)
620 next_busno = hose->last_busno + pcibios_assign_bus_offset;
621 }
622 pci_bus_count = next_busno;
623
624 /* OpenFirmware based machines need a map of OF bus
625 * numbers vs. kernel bus numbers since we may have to
626 * remap them.
627 */
628 if (pci_assign_all_buses && have_of)
629 pcibios_make_OF_bus_map();
630
631 /* Do machine dependent PCI interrupt routing */
632 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
633 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
634
635 /* Call machine dependent fixup */
636 if (ppc_md.pcibios_fixup)
637 ppc_md.pcibios_fixup();
638
639 /* Allocate and assign resources */
640 pcibios_allocate_bus_resources(&pci_root_buses);
641 pcibios_allocate_resources(0);
642 pcibios_allocate_resources(1);
643 pcibios_assign_resources();
644
645 /* Call machine dependent post-init code */
646 if (ppc_md.pcibios_after_init)
647 ppc_md.pcibios_after_init();
648
649 return 0;
650}
651
652subsys_initcall(pcibios_init);
653
654unsigned char __init
655common_swizzle(struct pci_dev *dev, unsigned char *pinp)
656{
657 struct pci_controller *hose = dev->sysdata;
658
659 if (dev->bus->number != hose->first_busno) {
660 u8 pin = *pinp;
661 do {
662 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
663 /* Move up the chain of bridges. */
664 dev = dev->bus->self;
665 } while (dev->bus->self);
666 *pinp = pin;
667
668 /* The slot is the idsel of the last bridge. */
669 }
670 return PCI_SLOT(dev->devfn);
671}
672
673unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
674 unsigned long start, unsigned long size)
675{
676 return start;
677}
678
679void __init pcibios_fixup_bus(struct pci_bus *bus)
680{
681 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
682 unsigned long io_offset;
683 struct resource *res;
684 int i;
685
686 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
687 if (bus->parent == NULL) {
688 /* This is a host bridge - fill in its resources */
689 hose->bus = bus;
690
691 bus->resource[0] = res = &hose->io_resource;
692 if (!res->flags) {
693 if (io_offset)
694 printk(KERN_ERR "I/O resource not set for host"
695 " bridge %d\n", hose->index);
696 res->start = 0;
697 res->end = IO_SPACE_LIMIT;
698 res->flags = IORESOURCE_IO;
699 }
700 res->start += io_offset;
701 res->end += io_offset;
702
703 for (i = 0; i < 3; ++i) {
704 res = &hose->mem_resources[i];
705 if (!res->flags) {
706 if (i > 0)
707 continue;
708 printk(KERN_ERR "Memory resource not set for "
709 "host bridge %d\n", hose->index);
710 res->start = hose->pci_mem_offset;
711 res->end = ~0U;
712 res->flags = IORESOURCE_MEM;
713 }
714 bus->resource[i+1] = res;
715 }
716 } else {
717 /* This is a subordinate bridge */
718 pci_read_bridge_bases(bus);
719
720 for (i = 0; i < 4; ++i) {
721 if ((res = bus->resource[i]) == NULL)
722 continue;
723 if (!res->flags)
724 continue;
725 if (io_offset && (res->flags & IORESOURCE_IO)) {
726 res->start += io_offset;
727 res->end += io_offset;
728 } else if (hose->pci_mem_offset
729 && (res->flags & IORESOURCE_MEM)) {
730 res->start += hose->pci_mem_offset;
731 res->end += hose->pci_mem_offset;
732 }
733 }
734 }
735
736 if (ppc_md.pcibios_fixup_bus)
737 ppc_md.pcibios_fixup_bus(bus);
738}
739
740char __init *pcibios_setup(char *str)
741{
742 return str;
743}
744
745/* the next one is stolen from the alpha port... */
746void __init
747pcibios_update_irq(struct pci_dev *dev, int irq)
748{
749 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
750 /* XXX FIXME - update OF device tree node interrupt property */
751}
752
753int pcibios_enable_device(struct pci_dev *dev, int mask)
754{
755 if (ppc_md.pcibios_enable_device_hook)
756 if (ppc_md.pcibios_enable_device_hook(dev, 0))
757 return -EINVAL;
758
759 return pci_enable_resources(dev, mask);
760}
761
762struct pci_controller*
763pci_bus_to_hose(int bus)
764{
765 struct pci_controller* hose = hose_head;
766
767 for (; hose; hose = hose->next)
768 if (bus >= hose->first_busno && bus <= hose->last_busno)
769 return hose;
770 return NULL;
771}
772
773void __iomem *
774pci_bus_io_base(unsigned int bus)
775{
776 struct pci_controller *hose;
777
778 hose = pci_bus_to_hose(bus);
779 if (!hose)
780 return NULL;
781 return hose->io_base_virt;
782}
783
784unsigned long
785pci_bus_io_base_phys(unsigned int bus)
786{
787 struct pci_controller *hose;
788
789 hose = pci_bus_to_hose(bus);
790 if (!hose)
791 return 0;
792 return hose->io_base_phys;
793}
794
795unsigned long
796pci_bus_mem_base_phys(unsigned int bus)
797{
798 struct pci_controller *hose;
799
800 hose = pci_bus_to_hose(bus);
801 if (!hose)
802 return 0;
803 return hose->pci_mem_offset;
804}
805
806unsigned long
807pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
808{
809 /* Hack alert again ! See comments in chrp_pci.c
810 */
811 struct pci_controller* hose =
812 (struct pci_controller *)pdev->sysdata;
813 if (hose && res->flags & IORESOURCE_MEM)
814 return res->start - hose->pci_mem_offset;
815 /* We may want to do something with IOs here... */
816 return res->start;
817}
818
819
820static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
821 resource_size_t *offset,
822 enum pci_mmap_state mmap_state)
823{
824 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
825 unsigned long io_offset = 0;
826 int i, res_bit;
827
828 if (hose == 0)
829 return NULL; /* should never happen */
830
831 /* If memory, add on the PCI bridge address offset */
832 if (mmap_state == pci_mmap_mem) {
833#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
834 *offset += hose->pci_mem_offset;
835#endif
836 res_bit = IORESOURCE_MEM;
837 } else {
838 io_offset = hose->io_base_virt - ___IO_BASE;
839 *offset += io_offset;
840 res_bit = IORESOURCE_IO;
841 }
842
843 /*
844 * Check that the offset requested corresponds to one of the
845 * resources of the device.
846 */
847 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
848 struct resource *rp = &dev->resource[i];
849 int flags = rp->flags;
850
851 /* treat ROM as memory (should be already) */
852 if (i == PCI_ROM_RESOURCE)
853 flags |= IORESOURCE_MEM;
854
855 /* Active and same type? */
856 if ((flags & res_bit) == 0)
857 continue;
858
859 /* In the range of this resource? */
860 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
861 continue;
862
863 /* found it! construct the final physical address */
864 if (mmap_state == pci_mmap_io)
865 *offset += hose->io_base_phys - io_offset;
866 return rp;
867 }
868
869 return NULL;
870}
871
872/*
873 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
874 * device mapping.
875 */
876static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
877 pgprot_t protection,
878 enum pci_mmap_state mmap_state,
879 int write_combine)
880{
881 unsigned long prot = pgprot_val(protection);
882
883 /* Write combine is always 0 on non-memory space mappings. On
884 * memory space, if the user didn't pass 1, we check for a
885 * "prefetchable" resource. This is a bit hackish, but we use
886 * this to workaround the inability of /sysfs to provide a write
887 * combine bit
888 */
889 if (mmap_state != pci_mmap_mem)
890 write_combine = 0;
891 else if (write_combine == 0) {
892 if (rp->flags & IORESOURCE_PREFETCH)
893 write_combine = 1;
894 }
895
896 /* XXX would be nice to have a way to ask for write-through */
897 prot |= _PAGE_NO_CACHE;
898 if (write_combine)
899 prot &= ~_PAGE_GUARDED;
900 else
901 prot |= _PAGE_GUARDED;
902
903 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev),
904 (unsigned long long)rp->start, prot);
905
906 return __pgprot(prot);
907}
908
909/*
910 * This one is used by /dev/mem and fbdev who have no clue about the
911 * PCI device, it tries to find the PCI device first and calls the
912 * above routine
913 */
914pgprot_t pci_phys_mem_access_prot(struct file *file,
915 unsigned long pfn,
916 unsigned long size,
917 pgprot_t protection)
918{
919 struct pci_dev *pdev = NULL;
920 struct resource *found = NULL;
921 unsigned long prot = pgprot_val(protection);
922 unsigned long offset = pfn << PAGE_SHIFT;
923 int i;
924
925 if (page_is_ram(pfn))
926 return prot;
927
928 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
929
930 for_each_pci_dev(pdev) {
931 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
932 struct resource *rp = &pdev->resource[i];
933 int flags = rp->flags;
934
935 /* Active and same type? */
936 if ((flags & IORESOURCE_MEM) == 0)
937 continue;
938 /* In the range of this resource? */
939 if (offset < (rp->start & PAGE_MASK) ||
940 offset > rp->end)
941 continue;
942 found = rp;
943 break;
944 }
945 if (found)
946 break;
947 }
948 if (found) {
949 if (found->flags & IORESOURCE_PREFETCH)
950 prot &= ~_PAGE_GUARDED;
951 pci_dev_put(pdev);
952 }
953
954 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
955
956 return __pgprot(prot);
957}
958
959
960/*
961 * Perform the actual remap of the pages for a PCI device mapping, as
962 * appropriate for this architecture. The region in the process to map
963 * is described by vm_start and vm_end members of VMA, the base physical
964 * address is found in vm_pgoff.
965 * The pci device structure is provided so that architectures may make mapping
966 * decisions on a per-device or per-bus basis.
967 *
968 * Returns a negative error code on failure, zero on success.
969 */
970int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
971 enum pci_mmap_state mmap_state,
972 int write_combine)
973{
974 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
975 struct resource *rp;
976 int ret;
977
978 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
979 if (rp == NULL)
980 return -EINVAL;
981
982 vma->vm_pgoff = offset >> PAGE_SHIFT;
983 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
984 vma->vm_page_prot,
985 mmap_state, write_combine);
986
987 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
988 vma->vm_end - vma->vm_start, vma->vm_page_prot);
989
990 return ret;
991}
992
993/* Obsolete functions. Should be removed once the symbios driver
994 * is fixed
995 */
996unsigned long
997phys_to_bus(unsigned long pa)
998{
999 struct pci_controller *hose;
1000 int i;
1001
1002 for (hose = hose_head; hose; hose = hose->next) {
1003 for (i = 0; i < 3; ++i) {
1004 if (pa >= hose->mem_resources[i].start
1005 && pa <= hose->mem_resources[i].end) {
1006 /*
1007 * XXX the hose->pci_mem_offset really
1008 * only applies to mem_resources[0].
1009 * We need a way to store an offset for
1010 * the others. -- paulus
1011 */
1012 if (i == 0)
1013 pa -= hose->pci_mem_offset;
1014 return pa;
1015 }
1016 }
1017 }
1018 /* hmmm, didn't find it */
1019 return 0;
1020}
1021
1022unsigned long
1023pci_phys_to_bus(unsigned long pa, int busnr)
1024{
1025 struct pci_controller* hose = pci_bus_to_hose(busnr);
1026 if (!hose)
1027 return pa;
1028 return pa - hose->pci_mem_offset;
1029}
1030
1031unsigned long
1032pci_bus_to_phys(unsigned int ba, int busnr)
1033{
1034 struct pci_controller* hose = pci_bus_to_hose(busnr);
1035 if (!hose)
1036 return ba;
1037 return ba + hose->pci_mem_offset;
1038}
1039
1040/* Provide information on locations of various I/O regions in physical
1041 * memory. Do this on a per-card basis so that we choose the right
1042 * root bridge.
1043 * Note that the returned IO or memory base is a physical address
1044 */
1045
1046long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1047{
1048 struct pci_controller* hose;
1049 long result = -EOPNOTSUPP;
1050
1051 hose = pci_bus_to_hose(bus);
1052 if (!hose)
1053 return -ENODEV;
1054
1055 switch (which) {
1056 case IOBASE_BRIDGE_NUMBER:
1057 return (long)hose->first_busno;
1058 case IOBASE_MEMORY:
1059 return (long)hose->pci_mem_offset;
1060 case IOBASE_IO:
1061 return (long)hose->io_base_phys;
1062 case IOBASE_ISA_IO:
1063 return (long)isa_io_base;
1064 case IOBASE_ISA_MEM:
1065 return (long)isa_mem_base;
1066 }
1067
1068 return result;
1069}
1070
1071void pci_resource_to_user(const struct pci_dev *dev, int bar,
1072 const struct resource *rsrc,
1073 resource_size_t *start, resource_size_t *end)
1074{
1075 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1076 resource_size_t offset = 0;
1077
1078 if (hose == NULL)
1079 return;
1080
1081 if (rsrc->flags & IORESOURCE_IO)
1082 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1083
1084 /* We pass a fully fixed up address to userland for MMIO instead of
1085 * a BAR value because X is lame and expects to be able to use that
1086 * to pass to /dev/mem !
1087 *
1088 * That means that we'll have potentially 64 bits values where some
1089 * userland apps only expect 32 (like X itself since it thinks only
1090 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1091 * 32 bits CHRPs :-(
1092 *
1093 * Hopefully, the sysfs insterface is immune to that gunk. Once X
1094 * has been fixed (and the fix spread enough), we can re-enable the
1095 * 2 lines below and pass down a BAR value to userland. In that case
1096 * we'll also have to re-enable the matching code in
1097 * __pci_mmap_make_offset().
1098 *
1099 * BenH.
1100 */
1101#if 0
1102 else if (rsrc->flags & IORESOURCE_MEM)
1103 offset = hose->pci_mem_offset;
1104#endif
1105
1106 *start = rsrc->start - offset;
1107 *end = rsrc->end - offset;
1108}
1109
1110void __init pci_init_resource(struct resource *res, resource_size_t start,
1111 resource_size_t end, int flags, char *name)
1112{
1113 res->start = start;
1114 res->end = end;
1115 res->flags = flags;
1116 res->name = name;
1117 res->parent = NULL;
1118 res->sibling = NULL;
1119 res->child = NULL;
1120}
1121
1122void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1123{
1124 resource_size_t start = pci_resource_start(dev, bar);
1125 resource_size_t len = pci_resource_len(dev, bar);
1126 unsigned long flags = pci_resource_flags(dev, bar);
1127
1128 if (!len)
1129 return NULL;
1130 if (max && len > max)
1131 len = max;
1132 if (flags & IORESOURCE_IO)
1133 return ioport_map(start, len);
1134 if (flags & IORESOURCE_MEM)
1135 /* Not checking IORESOURCE_CACHEABLE because PPC does
1136 * not currently distinguish between ioremap and
1137 * ioremap_nocache.
1138 */
1139 return ioremap(start, len);
1140 /* What? */
1141 return NULL;
1142}
1143
1144void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1145{
1146 /* Nothing to do */
1147}
1148EXPORT_SYMBOL(pci_iomap);
1149EXPORT_SYMBOL(pci_iounmap);
1150
1151unsigned long pci_address_to_pio(phys_addr_t address)
1152{
1153 struct pci_controller* hose = hose_head;
1154
1155 for (; hose; hose = hose->next) {
1156 unsigned int size = hose->io_resource.end -
1157 hose->io_resource.start + 1;
1158 if (address >= hose->io_base_phys &&
1159 address < (hose->io_base_phys + size)) {
1160 unsigned long base =
1161 (unsigned long)hose->io_base_virt - _IO_BASE;
1162 return base + (address - hose->io_base_phys);
1163 }
1164 }
1165 return (unsigned int)-1;
1166}
1167EXPORT_SYMBOL(pci_address_to_pio);
1168
1169/*
1170 * Null PCI config access functions, for the case when we can't
1171 * find a hose.
1172 */
1173#define NULL_PCI_OP(rw, size, type) \
1174static int \
1175null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1176{ \
1177 return PCIBIOS_DEVICE_NOT_FOUND; \
1178}
1179
1180static int
1181null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1182 int len, u32 *val)
1183{
1184 return PCIBIOS_DEVICE_NOT_FOUND;
1185}
1186
1187static int
1188null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1189 int len, u32 val)
1190{
1191 return PCIBIOS_DEVICE_NOT_FOUND;
1192}
1193
1194static struct pci_ops null_pci_ops =
1195{
1196 null_read_config,
1197 null_write_config
1198};
1199
1200/*
1201 * These functions are used early on before PCI scanning is done
1202 * and all of the pci_dev and pci_bus structures have been created.
1203 */
1204static struct pci_bus *
1205fake_pci_bus(struct pci_controller *hose, int busnr)
1206{
1207 static struct pci_bus bus;
1208
1209 if (hose == 0) {
1210 hose = pci_bus_to_hose(busnr);
1211 if (hose == 0)
1212 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1213 }
1214 bus.number = busnr;
1215 bus.sysdata = hose;
1216 bus.ops = hose? hose->ops: &null_pci_ops;
1217 return &bus;
1218}
1219
1220#define EARLY_PCI_OP(rw, size, type) \
1221int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1222 int devfn, int offset, type value) \
1223{ \
1224 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1225 devfn, offset, value); \
1226}
1227
1228EARLY_PCI_OP(read, byte, u8 *)
1229EARLY_PCI_OP(read, word, u16 *)
1230EARLY_PCI_OP(read, dword, u32 *)
1231EARLY_PCI_OP(write, byte, u8)
1232EARLY_PCI_OP(write, word, u16)
1233EARLY_PCI_OP(write, dword, u32)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 08:34:14 -0500