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-rw-r--r--arch/ppc/kernel/entry.S12
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index 59e77eb63338..5f3a5d068a5c 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -519,12 +519,7 @@ BEGIN_FTR_SECTION
519 stw r12,THREAD+THREAD_VRSAVE(r2) 519 stw r12,THREAD+THREAD_VRSAVE(r2)
520END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 520END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
521#endif /* CONFIG_ALTIVEC */ 521#endif /* CONFIG_ALTIVEC */
522#ifdef CONFIG_SPE 522 and. r0,r0,r11 /* FP or altivec enabled? */
523 oris r0,r0,MSR_SPE@h /* Disable SPE */
524 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
525 stw r12,THREAD+THREAD_SPEFSCR(r2)
526#endif /* CONFIG_SPE */
527 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
528 beq+ 1f 523 beq+ 1f
529 andc r11,r11,r0 524 andc r11,r11,r0
530 MTMSRD(r11) 525 MTMSRD(r11)
@@ -557,11 +552,6 @@ BEGIN_FTR_SECTION
557 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ 552 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
558END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 553END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
559#endif /* CONFIG_ALTIVEC */ 554#endif /* CONFIG_ALTIVEC */
560#ifdef CONFIG_SPE
561 lwz r0,THREAD+THREAD_SPEFSCR(r2)
562 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
563#endif /* CONFIG_SPE */
564
565 lwz r0,_CCR(r1) 555 lwz r0,_CCR(r1)
566 mtcrf 0xFF,r0 556 mtcrf 0xFF,r0
567 /* r3-r12 are destroyed -- Cort */ 557 /* r3-r12 are destroyed -- Cort */