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-rw-r--r--arch/ppc/kernel/cpu_setup_power4.S197
1 files changed, 0 insertions, 197 deletions
diff --git a/arch/ppc/kernel/cpu_setup_power4.S b/arch/ppc/kernel/cpu_setup_power4.S
deleted file mode 100644
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1/*
2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 */
11
12#include <asm/processor.h>
13#include <asm/page.h>
14#include <asm/ppc_asm.h>
15#include <asm/cputable.h>
16#include <asm/asm-offsets.h>
17#include <asm/cache.h>
18
19_GLOBAL(__970_cpu_preinit)
20 /*
21 * Deal only with PPC970 and PPC970FX.
22 */
23 mfspr r0,SPRN_PVR
24 srwi r0,r0,16
25 cmpwi cr0,r0,0x39
26 cmpwi cr1,r0,0x3c
27 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
28 bnelr
29
30 /* Make sure HID4:rm_ci is off before MMU is turned off, that large
31 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
32 * HID5:DCBZ32_ill
33 */
34 li r0,0
35 mfspr r11,SPRN_HID4
36 rldimi r11,r0,40,23 /* clear bit 23 (rm_ci) */
37 rldimi r11,r0,2,61 /* clear bit 61 (lg_pg_en) */
38 sync
39 mtspr SPRN_HID4,r11
40 isync
41 sync
42 mfspr r11,SPRN_HID5
43 rldimi r11,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
44 sync
45 mtspr SPRN_HID5,r11
46 isync
47 sync
48
49 /* Setup some basic HID1 features */
50 mfspr r0,SPRN_HID1
51 li r11,0x1200 /* enable i-fetch cacheability */
52 sldi r11,r11,44 /* and prefetch */
53 or r0,r0,r11
54 mtspr SPRN_HID1,r0
55 mtspr SPRN_HID1,r0
56 isync
57
58 /* Clear HIOR */
59 li r0,0
60 sync
61 mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
62 isync
63 blr
64
65_GLOBAL(__setup_cpu_ppc970)
66 mfspr r0,SPRN_HID0
67 li r11,5 /* clear DOZE and SLEEP */
68 rldimi r0,r11,52,8 /* set NAP and DPM */
69 mtspr SPRN_HID0,r0
70 mfspr r0,SPRN_HID0
71 mfspr r0,SPRN_HID0
72 mfspr r0,SPRN_HID0
73 mfspr r0,SPRN_HID0
74 mfspr r0,SPRN_HID0
75 mfspr r0,SPRN_HID0
76 sync
77 isync
78 blr
79
80/* Definitions for the table use to save CPU states */
81#define CS_HID0 0
82#define CS_HID1 8
83#define CS_HID4 16
84#define CS_HID5 24
85#define CS_SIZE 32
86
87 .data
88 .balign L1_CACHE_BYTES
89cpu_state_storage:
90 .space CS_SIZE
91 .balign L1_CACHE_BYTES,0
92 .text
93
94/* Called in normal context to backup CPU 0 state. This
95 * does not include cache settings. This function is also
96 * called for machine sleep. This does not include the MMU
97 * setup, BATs, etc... but rather the "special" registers
98 * like HID0, HID1, HID4, etc...
99 */
100_GLOBAL(__save_cpu_setup)
101 /* Some CR fields are volatile, we back it up all */
102 mfcr r7
103
104 /* Get storage ptr */
105 lis r5,cpu_state_storage@h
106 ori r5,r5,cpu_state_storage@l
107
108 /* We only deal with 970 for now */
109 mfspr r0,SPRN_PVR
110 srwi r0,r0,16
111 cmpwi cr0,r0,0x39
112 cmpwi cr1,r0,0x3c
113 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
114 bne 1f
115
116 /* Save HID0,1,4 and 5 */
117 mfspr r3,SPRN_HID0
118 std r3,CS_HID0(r5)
119 mfspr r3,SPRN_HID1
120 std r3,CS_HID1(r5)
121 mfspr r3,SPRN_HID4
122 std r3,CS_HID4(r5)
123 mfspr r3,SPRN_HID5
124 std r3,CS_HID5(r5)
125
1261:
127 mtcr r7
128 blr
129
130/* Called with no MMU context (typically MSR:IR/DR off) to
131 * restore CPU state as backed up by the previous
132 * function. This does not include cache setting
133 */
134_GLOBAL(__restore_cpu_setup)
135 /* Some CR fields are volatile, we back it up all */
136 mfcr r7
137
138 /* Get storage ptr */
139 lis r5,(cpu_state_storage-KERNELBASE)@h
140 ori r5,r5,cpu_state_storage@l
141
142 /* We only deal with 970 for now */
143 mfspr r0,SPRN_PVR
144 srwi r0,r0,16
145 cmpwi cr0,r0,0x39
146 cmpwi cr1,r0,0x3c
147 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
148 bne 1f
149
150 /* Clear interrupt prefix */
151 li r0,0
152 sync
153 mtspr SPRN_HIOR,0
154 isync
155
156 /* Restore HID0 */
157 ld r3,CS_HID0(r5)
158 sync
159 isync
160 mtspr SPRN_HID0,r3
161 mfspr r3,SPRN_HID0
162 mfspr r3,SPRN_HID0
163 mfspr r3,SPRN_HID0
164 mfspr r3,SPRN_HID0
165 mfspr r3,SPRN_HID0
166 mfspr r3,SPRN_HID0
167 sync
168 isync
169
170 /* Restore HID1 */
171 ld r3,CS_HID1(r5)
172 sync
173 isync
174 mtspr SPRN_HID1,r3
175 mtspr SPRN_HID1,r3
176 sync
177 isync
178
179 /* Restore HID4 */
180 ld r3,CS_HID4(r5)
181 sync
182 isync
183 mtspr SPRN_HID4,r3
184 sync
185 isync
186
187 /* Restore HID5 */
188 ld r3,CS_HID5(r5)
189 sync
190 isync
191 mtspr SPRN_HID5,r3
192 sync
193 isync
1941:
195 mtcr r7
196 blr
197
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