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-rw-r--r--arch/ppc/kernel/cpu_setup_6xx.S12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 468721d9ebd2..ba396438ede3 100644
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -12,10 +12,9 @@
12#include <linux/config.h> 12#include <linux/config.h>
13#include <asm/processor.h> 13#include <asm/processor.h>
14#include <asm/page.h> 14#include <asm/page.h>
15#include <asm/ppc_asm.h>
16#include <asm/cputable.h> 15#include <asm/cputable.h>
17#include <asm/ppc_asm.h> 16#include <asm/ppc_asm.h>
18#include <asm/offsets.h> 17#include <asm/asm-offsets.h>
19#include <asm/cache.h> 18#include <asm/cache.h>
20 19
21_GLOBAL(__setup_cpu_601) 20_GLOBAL(__setup_cpu_601)
@@ -249,8 +248,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
249 sync 248 sync
250 isync 249 isync
251 250
252 /* Enable L2 HW prefetch 251 /* Enable L2 HW prefetch, if L2 is enabled
253 */ 252 */
253 mfspr r3,SPRN_L2CR
254 andis. r3,r3,L2CR_L2E@h
255 beqlr
254 mfspr r3,SPRN_MSSCR0 256 mfspr r3,SPRN_MSSCR0
255 ori r3,r3,3 257 ori r3,r3,3
256 sync 258 sync
@@ -324,6 +326,7 @@ _GLOBAL(__save_cpu_setup)
324 cmplwi cr4,r3,0x8002 /* 7457 */ 326 cmplwi cr4,r3,0x8002 /* 7457 */
325 cmplwi cr5,r3,0x8003 /* 7447A */ 327 cmplwi cr5,r3,0x8003 /* 7447A */
326 cmplwi cr6,r3,0x7000 /* 750FX */ 328 cmplwi cr6,r3,0x7000 /* 750FX */
329 cmplwi cr7,r3,0x8004 /* 7448 */
327 /* cr1 is 7400 || 7410 */ 330 /* cr1 is 7400 || 7410 */
328 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 331 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
329 /* cr0 is 74xx */ 332 /* cr0 is 74xx */
@@ -331,6 +334,7 @@ _GLOBAL(__save_cpu_setup)
331 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq 334 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
332 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 335 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
333 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq 336 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
337 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
334 bne 1f 338 bne 1f
335 /* Backup 74xx specific regs */ 339 /* Backup 74xx specific regs */
336 mfspr r4,SPRN_MSSCR0 340 mfspr r4,SPRN_MSSCR0
@@ -393,6 +397,7 @@ _GLOBAL(__restore_cpu_setup)
393 cmplwi cr4,r3,0x8002 /* 7457 */ 397 cmplwi cr4,r3,0x8002 /* 7457 */
394 cmplwi cr5,r3,0x8003 /* 7447A */ 398 cmplwi cr5,r3,0x8003 /* 7447A */
395 cmplwi cr6,r3,0x7000 /* 750FX */ 399 cmplwi cr6,r3,0x7000 /* 750FX */
400 cmplwi cr7,r3,0x8004 /* 7448 */
396 /* cr1 is 7400 || 7410 */ 401 /* cr1 is 7400 || 7410 */
397 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 402 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
398 /* cr0 is 74xx */ 403 /* cr0 is 74xx */
@@ -400,6 +405,7 @@ _GLOBAL(__restore_cpu_setup)
400 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq 405 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
401 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 406 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
402 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq 407 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
408 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
403 bne 2f 409 bne 2f
404 /* Restore 74xx specific regs */ 410 /* Restore 74xx specific regs */
405 lwz r4,CS_MSSCR0(r5) 411 lwz r4,CS_MSSCR0(r5)