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-rw-r--r--arch/ppc/boot/simple/Makefile277
-rw-r--r--arch/ppc/boot/simple/chrpmap.c12
-rw-r--r--arch/ppc/boot/simple/clear.S19
-rw-r--r--arch/ppc/boot/simple/cpc700_memory.c34
-rw-r--r--arch/ppc/boot/simple/dummy.c4
-rw-r--r--arch/ppc/boot/simple/embed_config.c938
-rw-r--r--arch/ppc/boot/simple/head.S137
-rw-r--r--arch/ppc/boot/simple/iic.c214
-rw-r--r--arch/ppc/boot/simple/m8260_tty.c325
-rw-r--r--arch/ppc/boot/simple/m8xx_tty.c289
-rw-r--r--arch/ppc/boot/simple/misc-chestnut.c32
-rw-r--r--arch/ppc/boot/simple/misc-cpci690.c65
-rw-r--r--arch/ppc/boot/simple/misc-embedded.c276
-rw-r--r--arch/ppc/boot/simple/misc-ev64260.c54
-rw-r--r--arch/ppc/boot/simple/misc-ev64360.c42
-rw-r--r--arch/ppc/boot/simple/misc-katana.c42
-rw-r--r--arch/ppc/boot/simple/misc-mv64x60.c85
-rw-r--r--arch/ppc/boot/simple/misc-prep.c209
-rw-r--r--arch/ppc/boot/simple/misc-radstone_ppc7d.c24
-rw-r--r--arch/ppc/boot/simple/misc-spruce.c271
-rw-r--r--arch/ppc/boot/simple/misc.c278
-rw-r--r--arch/ppc/boot/simple/mpc10x_memory.c109
-rw-r--r--arch/ppc/boot/simple/mpc52xx_tty.c137
-rw-r--r--arch/ppc/boot/simple/mv64x60_tty.c364
-rw-r--r--arch/ppc/boot/simple/openbios.c128
-rw-r--r--arch/ppc/boot/simple/pci.c274
-rw-r--r--arch/ppc/boot/simple/pibs.c104
-rw-r--r--arch/ppc/boot/simple/prepmap.c12
-rw-r--r--arch/ppc/boot/simple/qspan_pci.c269
-rw-r--r--arch/ppc/boot/simple/relocate.S213
-rw-r--r--arch/ppc/boot/simple/rw4/ppc_40x.h664
-rw-r--r--arch/ppc/boot/simple/rw4/rw4_init.S78
-rw-r--r--arch/ppc/boot/simple/rw4/rw4_init_brd.S1125
-rw-r--r--arch/ppc/boot/simple/rw4/stb.h239
-rw-r--r--arch/ppc/boot/simple/uartlite_tty.c45
35 files changed, 0 insertions, 7388 deletions
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
deleted file mode 100644
index 5b877792d14f..000000000000
--- a/arch/ppc/boot/simple/Makefile
+++ /dev/null
@@ -1,277 +0,0 @@
1# This is far from simple, but I couldn't think of a good name. This is
2# for making the 'zImage' or 'zImage.initrd' on a number of targets.
3#
4# Author: Tom Rini <trini@mvista.com>
5#
6# Notes:
7# (1) For machines that do not want to use the ELF image directly (including
8# stripping just the ELF header off), they must set the variables
9# zimage-$(CONFIG_MACHINE) and zimagerd-$(CONFIG_MACHINE) to the target
10# that produces the desired image and they must set end-$(CONFIG_MACHINE)
11# to what will be suffixed to the image filename.
12# (2) Regardless of (1), to have the resulting image be something other
13# than 'zImage.elf', set end-$(CONFIG_MACHINE) to be the suffix used for
14# the zImage, znetboot, and znetbootrd targets.
15# (3) For machine targets which use the mktree program, you can optionally
16# set entrypoint-$(CONFIG_MACHINE) to the location which the image should be
17# loaded at. The optimal setting for entrypoint-$(CONFIG_MACHINE) is the link
18# address.
19# (4) It is advisable to pass in the memory size using BI_MEMSIZE and
20# get_mem_size(), which is memory controller dependent. Add in the correct
21# XXX_memory.o file for this to work, as well as editing the
22# misc-$(CONFIG_MACHINE) variable.
23
24boot := arch/ppc/boot
25common := $(boot)/common
26utils := $(boot)/utils
27bootlib := $(boot)/lib
28images := $(boot)/images
29of1275 := $(boot)/of1275
30tftpboot := /tftpboot
31
32# Normally, we use the 'misc.c' file for decompress_kernel and
33# whatnot. Sometimes we need to override this however.
34misc-y := misc.o
35
36# Normally, we have our images end in .elf, but something we want to
37# change this.
38end-y := elf
39
40# Additionally, we normally don't need to mess with the L2 / L3 caches
41# if present on 'classic' PPC.
42cacheflag-y := -DCLEAR_CACHES=""
43# This file will flush / disable the L2, and L3 if present.
44clear_L2_L3 := $(srctree)/$(boot)/simple/clear.S
45
46#
47# See arch/ppc/kconfig and arch/ppc/platforms/Kconfig
48# for definition of what platform each config option refer to.
49#----------------------------------------------------------------------------
50 zimage-$(CONFIG_CPCI690) := zImage-STRIPELF
51zimageinitrd-$(CONFIG_CPCI690) := zImage.initrd-STRIPELF
52 extra.o-$(CONFIG_CPCI690) := misc-cpci690.o
53 end-$(CONFIG_CPCI690) := cpci690
54 cacheflag-$(CONFIG_CPCI690) := -include $(clear_L2_L3)
55
56 zimage-$(CONFIG_IBM_OPENBIOS) := zImage-TREE
57zimageinitrd-$(CONFIG_IBM_OPENBIOS) := zImage.initrd-TREE
58 end-$(CONFIG_IBM_OPENBIOS) := treeboot
59 misc-$(CONFIG_IBM_OPENBIOS) := misc-embedded.o
60
61 end-$(CONFIG_EMBEDDEDBOOT) := embedded
62 misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
63
64 zimage-$(CONFIG_BAMBOO) := zImage-TREE
65zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
66 end-$(CONFIG_BAMBOO) := bamboo
67 entrypoint-$(CONFIG_BAMBOO) := 0x01000000
68 extra.o-$(CONFIG_BAMBOO) := pibs.o
69
70 zimage-$(CONFIG_BUBINGA) := zImage-TREE
71zimageinitrd-$(CONFIG_BUBINGA) := zImage.initrd-TREE
72 end-$(CONFIG_BUBINGA) := bubinga
73 entrypoint-$(CONFIG_BUBINGA) := 0x01000000
74 extra.o-$(CONFIG_BUBINGA) := openbios.o
75
76 zimage-$(CONFIG_EBONY) := zImage-TREE
77zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
78 end-$(CONFIG_EBONY) := ebony
79 entrypoint-$(CONFIG_EBONY) := 0x01000000
80 extra.o-$(CONFIG_EBONY) := openbios.o
81
82 zimage-$(CONFIG_LUAN) := zImage-TREE
83zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE
84 end-$(CONFIG_LUAN) := luan
85 entrypoint-$(CONFIG_LUAN) := 0x01000000
86 extra.o-$(CONFIG_LUAN) := pibs.o
87
88 zimage-$(CONFIG_YUCCA) := zImage-TREE
89zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE
90 end-$(CONFIG_YUCCA) := yucca
91 entrypoint-$(CONFIG_YUCCA) := 0x01000000
92 extra.o-$(CONFIG_YUCCA) := pibs.o
93
94 zimage-$(CONFIG_OCOTEA) := zImage-TREE
95zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE
96 end-$(CONFIG_OCOTEA) := ocotea
97 entrypoint-$(CONFIG_OCOTEA) := 0x01000000
98 extra.o-$(CONFIG_OCOTEA) := pibs.o
99
100 zimage-$(CONFIG_SYCAMORE) := zImage-TREE
101zimageinitrd-$(CONFIG_SYCAMORE) := zImage.initrd-TREE
102 end-$(CONFIG_SYCAMORE) := sycamore
103 entrypoint-$(CONFIG_SYCAMORE) := 0x01000000
104 extra.o-$(CONFIG_SYCAMORE) := openbios.o
105
106 zimage-$(CONFIG_WALNUT) := zImage-TREE
107zimageinitrd-$(CONFIG_WALNUT) := zImage.initrd-TREE
108 end-$(CONFIG_WALNUT) := walnut
109 entrypoint-$(CONFIG_WALNUT) := 0x01000000
110 extra.o-$(CONFIG_WALNUT) := openbios.o
111
112 extra.o-$(CONFIG_EV64260) := misc-ev64260.o
113 end-$(CONFIG_EV64260) := ev64260
114 cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3)
115
116 extra.o-$(CONFIG_CHESTNUT) := misc-chestnut.o
117 end-$(CONFIG_CHESTNUT) := chestnut
118
119 extra.o-$(CONFIG_KATANA) := misc-katana.o
120 end-$(CONFIG_KATANA) := katana
121 cacheflag-$(CONFIG_KATANA) := -include $(clear_L2_L3)
122
123 extra.o-$(CONFIG_RADSTONE_PPC7D) := misc-radstone_ppc7d.o
124 end-$(CONFIG_RADSTONE_PPC7D) := radstone_ppc7d
125 cacheflag-$(CONFIG_RADSTONE_PPC7D) := -include $(clear_L2_L3)
126
127 extra.o-$(CONFIG_EV64360) := misc-ev64360.o
128 end-$(CONFIG_EV64360) := ev64360
129 cacheflag-$(CONFIG_EV64360) := -include $(clear_L2_L3)
130
131# kconfig 'feature', only one of these will ever be 'y' at a time.
132# The rest will be unset.
133motorola := $(CONFIG_MVME5100)$(CONFIG_PRPMC750) \
134$(CONFIG_PRPMC800)$(CONFIG_LOPEC)$(CONFIG_PPLUS)
135motorola := $(strip $(motorola))
136
137 zimage-$(motorola) := zImage-PPLUS
138zimageinitrd-$(motorola) := zImage.initrd-PPLUS
139 end-$(motorola) := pplus
140
141# Overrides previous assingment
142 extra.o-$(CONFIG_PPLUS) := prepmap.o
143 extra.o-$(CONFIG_LOPEC) := mpc10x_memory.o
144
145# Really only valid if CONFIG_6xx=y
146 zimage-$(CONFIG_PPC_PREP) := zImage-PPLUS
147zimageinitrd-$(CONFIG_PPC_PREP) := zImage.initrd-PPLUS
148ifeq ($(CONFIG_6xx),y)
149 extra.o-$(CONFIG_PPC_PREP) := prepmap.o
150 misc-$(CONFIG_PPC_PREP) += misc-prep.o mpc10x_memory.o
151endif
152 end-$(CONFIG_PPC_PREP) := prep
153
154 end-$(CONFIG_SANDPOINT) := sandpoint
155 cacheflag-$(CONFIG_SANDPOINT) := -include $(clear_L2_L3)
156
157 zimage-$(CONFIG_SPRUCE) := zImage-TREE
158zimageinitrd-$(CONFIG_SPRUCE) := zImage.initrd-TREE
159 end-$(CONFIG_SPRUCE) := spruce
160 entrypoint-$(CONFIG_SPRUCE) := 0x00800000
161 misc-$(CONFIG_SPRUCE) += misc-spruce.o
162
163 zimage-$(CONFIG_LITE5200) := zImage-STRIPELF
164zimageinitrd-$(CONFIG_LITE5200) := zImage.initrd-STRIPELF
165 end-$(CONFIG_LITE5200) := lite5200
166 cacheflag-$(CONFIG_LITE5200) := -include $(clear_L2_L3)
167
168
169# SMP images should have a '.smp' suffix.
170 end-$(CONFIG_SMP) := $(end-y).smp
171
172# This is a treeboot that needs init functions until the
173# boot rom is sorted out (i.e. this is short lived)
174EXTRA_AFLAGS := $(extra-aflags-y)
175# head.o needs to get the cacheflags defined.
176AFLAGS_head.o += $(cacheflag-y)
177
178# Linker args. This specifies where the image will be run at.
179LD_ARGS := -T $(srctree)/$(boot)/ld.script \
180 -Ttext $(CONFIG_BOOT_LOAD) -Bstatic
181OBJCOPY_ARGS := -O elf32-powerpc
182
183# head.o and relocate.o must be at the start.
184boot-y := head.o relocate.o $(extra.o-y) $(misc-y)
185boot-$(CONFIG_REDWOOD_5) += embed_config.o
186boot-$(CONFIG_REDWOOD_6) += embed_config.o
187boot-$(CONFIG_8xx) += embed_config.o
188boot-$(CONFIG_8260) += embed_config.o
189boot-$(CONFIG_EP405) += embed_config.o
190boot-$(CONFIG_XILINX_ML300) += embed_config.o
191boot-$(CONFIG_XILINX_ML403) += embed_config.o
192boot-$(CONFIG_BSEIP) += iic.o
193boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o
194boot-$(CONFIG_MV64X60) += misc-mv64x60.o
195boot-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o
196boot-$(CONFIG_RPXLITE) += iic.o
197# Different boards need different serial implementations.
198ifeq ($(CONFIG_SERIAL_CPM_CONSOLE),y)
199boot-$(CONFIG_8xx) += m8xx_tty.o
200boot-$(CONFIG_8260) += m8260_tty.o
201endif
202boot-$(CONFIG_SERIAL_MPC52xx_CONSOLE) += mpc52xx_tty.o
203boot-$(CONFIG_SERIAL_MPSC_CONSOLE) += mv64x60_tty.o
204boot-$(CONFIG_SERIAL_UARTLITE_CONSOLE) += uartlite_tty.o
205
206LIBS := $(common)/lib.a $(bootlib)/lib.a
207ifeq ($(CONFIG_PPC_PREP),y)
208LIBS += $(of1275)/lib.a
209endif
210
211OBJS := $(addprefix $(obj)/,$(boot-y))
212
213# Tools
214MKBUGBOOT := $(utils)/mkbugboot
215MKPREP := $(utils)/mkprep
216MKTREE := $(utils)/mktree
217
218targets := dummy.o
219
220$(obj)/zvmlinux: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \
221 $(images)/vmlinux.gz $(obj)/dummy.o
222 $(OBJCOPY) $(OBJCOPY_ARGS) \
223 --add-section=.image=$(images)/vmlinux.gz \
224 --set-section-flags=.image=contents,alloc,load,readonly,data \
225 $(obj)/dummy.o $(obj)/image.o
226 $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS)
227 $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \
228 -R .stabstr -R .ramdisk
229
230$(obj)/zvmlinux.initrd: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \
231 $(images)/vmlinux.gz $(obj)/dummy.o
232 $(OBJCOPY) $(OBJCOPY_ARGS) \
233 --add-section=.ramdisk=$(images)/ramdisk.image.gz \
234 --set-section-flags=.ramdisk=contents,alloc,load,readonly,data \
235 --add-section=.image=$(images)/vmlinux.gz \
236 --set-section-flags=.image=contents,alloc,load,readonly,data \
237 $(obj)/dummy.o $(obj)/image.o
238 $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS)
239 $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \
240 -R .stabstr
241
242# Sort-of dummy rules, that let us format the image we want.
243zImage: $(images)/$(zimage-y) $(obj)/zvmlinux
244 cp -f $(obj)/zvmlinux $(images)/zImage.elf
245 rm -f $(obj)/zvmlinux
246
247zImage.initrd: $(images)/$(zimageinitrd-y) $(obj)/zvmlinux.initrd
248 cp -f $(obj)/zvmlinux.initrd $(images)/zImage.initrd.elf
249 rm -f $(obj)/zvmlinux.initrd
250
251znetboot: zImage
252 cp $(images)/zImage.$(end-y) $(tftpboot)/zImage.$(end-y)
253
254znetboot.initrd: zImage.initrd
255 cp $(images)/zImage.initrd.$(end-y) $(tftpboot)/zImage.initrd.$(end-y)
256
257$(images)/zImage-STRIPELF: $(obj)/zvmlinux
258 dd if=$(obj)/zvmlinux of=$(images)/zImage.$(end-y) skip=64 bs=1k
259
260$(images)/zImage.initrd-STRIPELF: $(obj)/zvmlinux.initrd
261 dd if=$(obj)/zvmlinux.initrd of=$(images)/zImage.initrd.$(end-y) \
262 skip=64 bs=1k
263
264$(images)/zImage-TREE: $(obj)/zvmlinux $(MKTREE)
265 $(MKTREE) $(obj)/zvmlinux $(images)/zImage.$(end-y) $(entrypoint-y)
266
267$(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE)
268 $(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \
269 $(entrypoint-y)
270
271$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT)
272 $(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y)
273 $(MKBUGBOOT) $(obj)/zvmlinux $(images)/zImage.bugboot
274
275$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(MKPREP) $(MKBUGBOOT)
276 $(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y)
277 $(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot
diff --git a/arch/ppc/boot/simple/chrpmap.c b/arch/ppc/boot/simple/chrpmap.c
deleted file mode 100644
index 14d9e05d98bb..000000000000
--- a/arch/ppc/boot/simple/chrpmap.c
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * 2004 (C) IBM. This file is licensed under the terms of the GNU General
3 * Public License version 2. This program is licensed "as is" without any
4 * warranty of any kind, whether express or implied.
5 */
6
7#include <nonstdio.h>
8
9void board_isa_init(void)
10{
11 ISA_init(0xFE000000);
12}
diff --git a/arch/ppc/boot/simple/clear.S b/arch/ppc/boot/simple/clear.S
deleted file mode 100644
index 95c5647a0f51..000000000000
--- a/arch/ppc/boot/simple/clear.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Code to call _setup_L2CR to flus, invalidate and disable the L2,
3 * and if present, do the same to the L3.
4 */
5
6#define CLEAR_CACHES \
7 bl _setup_L2CR; \
8 \
9 /* If 745x, turn off L3CR as well */ \
10 mfspr r8,SPRN_PVR; \
11 srwi r8,r8,16; \
12 \
13 cmpli cr0,r8,0x8000; /* 7450 */ \
14 cmpli cr1,r8,0x8001; /* 7455 */ \
15 cmpli cr2,r8,0x8002; /* 7457 */ \
16 /* Now test if any are true. */ \
17 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq; \
18 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq; \
19 beql _setup_L3CR
diff --git a/arch/ppc/boot/simple/cpc700_memory.c b/arch/ppc/boot/simple/cpc700_memory.c
deleted file mode 100644
index d75420a45a59..000000000000
--- a/arch/ppc/boot/simple/cpc700_memory.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Find memory based upon settings in the CPC700 bridge
3 *
4 * Author: Dan Cox
5 *
6 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <asm/types.h>
13#include <asm/io.h>
14#include "cpc700.h"
15
16unsigned long
17cpc700_get_mem_size(void)
18{
19 int i;
20 unsigned long len, amt;
21
22 /* Start at MB1EA, since MB0EA will most likely be the ending address
23 for ROM space. */
24 for(len = 0, i = CPC700_MB1EA; i <= CPC700_MB4EA; i+=4) {
25 amt = cpc700_read_memreg(i);
26 if (amt == 0)
27 break;
28 len = amt;
29 }
30
31 return len;
32}
33
34
diff --git a/arch/ppc/boot/simple/dummy.c b/arch/ppc/boot/simple/dummy.c
deleted file mode 100644
index 31dbf45bf99c..000000000000
--- a/arch/ppc/boot/simple/dummy.c
+++ /dev/null
@@ -1,4 +0,0 @@
1int main(void)
2{
3 return 0;
4}
diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c
deleted file mode 100644
index 3b46792d7b8b..000000000000
--- a/arch/ppc/boot/simple/embed_config.c
+++ /dev/null
@@ -1,938 +0,0 @@
1/* Board specific functions for those embedded 8xx boards that do
2 * not have boot monitor support for board information.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/types.h>
11#include <linux/string.h>
12#include <asm/reg.h>
13#ifdef CONFIG_8xx
14#include <asm/mpc8xx.h>
15#endif
16#ifdef CONFIG_8260
17#include <asm/mpc8260.h>
18#include <asm/immap_cpm2.h>
19#endif
20#ifdef CONFIG_40x
21#include <asm/io.h>
22#endif
23#ifdef CONFIG_XILINX_VIRTEX
24#include <platforms/4xx/xparameters/xparameters.h>
25#endif
26extern unsigned long timebase_period_ns;
27
28/* For those boards that don't provide one.
29*/
30#if !defined(CONFIG_MBX)
31static bd_t bdinfo;
32#endif
33
34/* IIC functions.
35 * These are just the basic master read/write operations so we can
36 * examine serial EEPROM.
37 */
38extern void iic_read(uint devaddr, u_char *buf, uint offset, uint count);
39
40/* Supply a default Ethernet address for those eval boards that don't
41 * ship with one. This is an address from the MBX board I have, so
42 * it is unlikely you will find it on your network.
43 */
44static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };
45
46#if defined(CONFIG_MBX)
47
48/* The MBX hands us a pretty much ready to go board descriptor. This
49 * is where the idea started in the first place.
50 */
51void
52embed_config(bd_t **bdp)
53{
54 u_char *mp;
55 u_char eebuf[128];
56 int i = 8;
57 bd_t *bd;
58
59 bd = *bdp;
60
61 /* Read the first 128 bytes of the EEPROM. There is more,
62 * but this is all we need.
63 */
64 iic_read(0xa4, eebuf, 0, 128);
65
66 /* All we are looking for is the Ethernet MAC address. The
67 * first 8 bytes are 'MOTOROLA', so check for part of that.
68 * Next, the VPD describes a MAC 'packet' as being of type 08
69 * and size 06. So we look for that and the MAC must follow.
70 * If there are more than one, we still only care about the first.
71 * If it's there, assume we have a valid MAC address. If not,
72 * grab our default one.
73 */
74 if ((*(uint *)eebuf) == 0x4d4f544f) {
75 while (i < 127 && !(eebuf[i] == 0x08 && eebuf[i + 1] == 0x06))
76 i += eebuf[i + 1] + 2; /* skip this packet */
77
78 if (i == 127) /* Couldn't find. */
79 mp = (u_char *)def_enet_addr;
80 else
81 mp = &eebuf[i + 2];
82 }
83 else
84 mp = (u_char *)def_enet_addr;
85
86 for (i=0; i<6; i++)
87 bd->bi_enetaddr[i] = *mp++;
88
89 /* The boot rom passes these to us in MHz. Linux now expects
90 * them to be in Hz.
91 */
92 bd->bi_intfreq *= 1000000;
93 bd->bi_busfreq *= 1000000;
94
95 /* Stuff a baud rate here as well.
96 */
97 bd->bi_baudrate = 9600;
98}
99#endif /* CONFIG_MBX */
100
101#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || \
102 defined(CONFIG_RPX8260) || defined(CONFIG_EP405)
103/* Helper functions for Embedded Planet boards.
104*/
105/* Because I didn't find anything that would do this.......
106*/
107u_char
108aschex_to_byte(u_char *cp)
109{
110 u_char byte, c;
111
112 c = *cp++;
113
114 if ((c >= 'A') && (c <= 'F')) {
115 c -= 'A';
116 c += 10;
117 } else if ((c >= 'a') && (c <= 'f')) {
118 c -= 'a';
119 c += 10;
120 } else
121 c -= '0';
122
123 byte = c * 16;
124
125 c = *cp;
126
127 if ((c >= 'A') && (c <= 'F')) {
128 c -= 'A';
129 c += 10;
130 } else if ((c >= 'a') && (c <= 'f')) {
131 c -= 'a';
132 c += 10;
133 } else
134 c -= '0';
135
136 byte += c;
137
138 return(byte);
139}
140
141static void
142rpx_eth(bd_t *bd, u_char *cp)
143{
144 int i;
145
146 for (i=0; i<6; i++) {
147 bd->bi_enetaddr[i] = aschex_to_byte(cp);
148 cp += 2;
149 }
150}
151
152#ifdef CONFIG_RPX8260
153static uint
154rpx_baseten(u_char *cp)
155{
156 uint retval;
157
158 retval = 0;
159
160 while (*cp != '\n') {
161 retval *= 10;
162 retval += (*cp) - '0';
163 cp++;
164 }
165 return(retval);
166}
167#endif
168
169#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
170static void
171rpx_brate(bd_t *bd, u_char *cp)
172{
173 uint rate;
174
175 rate = 0;
176
177 while (*cp != '\n') {
178 rate *= 10;
179 rate += (*cp) - '0';
180 cp++;
181 }
182
183 bd->bi_baudrate = rate * 100;
184}
185
186static void
187rpx_cpuspeed(bd_t *bd, u_char *cp)
188{
189 uint num, den;
190
191 num = den = 0;
192
193 while (*cp != '\n') {
194 num *= 10;
195 num += (*cp) - '0';
196 cp++;
197 if (*cp == '/') {
198 cp++;
199 den = (*cp) - '0';
200 break;
201 }
202 }
203
204 /* I don't know why the RPX just can't state the actual
205 * CPU speed.....
206 */
207 if (den) {
208 num /= den;
209 num *= den;
210 }
211 bd->bi_intfreq = bd->bi_busfreq = num * 1000000;
212
213 /* The 8xx can only run a maximum 50 MHz bus speed (until
214 * Motorola changes this :-). Greater than 50 MHz parts
215 * run internal/2 for bus speed.
216 */
217 if (num > 50)
218 bd->bi_busfreq /= 2;
219}
220#endif
221
222#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405)
223static void
224rpx_memsize(bd_t *bd, u_char *cp)
225{
226 uint size;
227
228 size = 0;
229
230 while (*cp != '\n') {
231 size *= 10;
232 size += (*cp) - '0';
233 cp++;
234 }
235
236 bd->bi_memsize = size * 1024 * 1024;
237}
238#endif /* LITE || CLASSIC || EP405 */
239#if defined(CONFIG_EP405)
240static void
241rpx_nvramsize(bd_t *bd, u_char *cp)
242{
243 uint size;
244
245 size = 0;
246
247 while (*cp != '\n') {
248 size *= 10;
249 size += (*cp) - '0';
250 cp++;
251 }
252
253 bd->bi_nvramsize = size * 1024;
254}
255#endif /* CONFIG_EP405 */
256
257#endif /* Embedded Planet boards */
258
259#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
260
261/* Read the EEPROM on the RPX-Lite board.
262*/
263void
264embed_config(bd_t **bdp)
265{
266 u_char eebuf[256], *cp;
267 bd_t *bd;
268
269 /* Read the first 256 bytes of the EEPROM. I think this
270 * is really all there is, and I hope if it gets bigger the
271 * info we want is still up front.
272 */
273 bd = &bdinfo;
274 *bdp = bd;
275
276#if 1
277 iic_read(0xa8, eebuf, 0, 128);
278 iic_read(0xa8, &eebuf[128], 128, 128);
279
280 /* We look for two things, the Ethernet address and the
281 * serial baud rate. The records are separated by
282 * newlines.
283 */
284 cp = eebuf;
285 for (;;) {
286 if (*cp == 'E') {
287 cp++;
288 if (*cp == 'A') {
289 cp += 2;
290 rpx_eth(bd, cp);
291 }
292 }
293 if (*cp == 'S') {
294 cp++;
295 if (*cp == 'B') {
296 cp += 2;
297 rpx_brate(bd, cp);
298 }
299 }
300 if (*cp == 'D') {
301 cp++;
302 if (*cp == '1') {
303 cp += 2;
304 rpx_memsize(bd, cp);
305 }
306 }
307 if (*cp == 'H') {
308 cp++;
309 if (*cp == 'Z') {
310 cp += 2;
311 rpx_cpuspeed(bd, cp);
312 }
313 }
314
315 /* Scan to the end of the record.
316 */
317 while ((*cp != '\n') && (*cp != 0xff))
318 cp++;
319
320 /* If the next character is a 0 or ff, we are done.
321 */
322 cp++;
323 if ((*cp == 0) || (*cp == 0xff))
324 break;
325 }
326 bd->bi_memstart = 0;
327#else
328 /* For boards without initialized EEPROM.
329 */
330 bd->bi_memstart = 0;
331 bd->bi_memsize = (8 * 1024 * 1024);
332 bd->bi_intfreq = 48000000;
333 bd->bi_busfreq = 48000000;
334 bd->bi_baudrate = 9600;
335#endif
336}
337#endif /* RPXLITE || RPXCLASSIC */
338
339#ifdef CONFIG_BSEIP
340/* Build a board information structure for the BSE ip-Engine.
341 * There is more to come since we will add some environment
342 * variables and a function to read them.
343 */
344void
345embed_config(bd_t **bdp)
346{
347 u_char *cp;
348 int i;
349 bd_t *bd;
350
351 bd = &bdinfo;
352 *bdp = bd;
353
354 /* Baud rate and processor speed will eventually come
355 * from the environment variables.
356 */
357 bd->bi_baudrate = 9600;
358
359 /* Get the Ethernet station address from the Flash ROM.
360 */
361 cp = (u_char *)0xfe003ffa;
362 for (i=0; i<6; i++) {
363 bd->bi_enetaddr[i] = *cp++;
364 }
365
366 /* The rest of this should come from the environment as well.
367 */
368 bd->bi_memstart = 0;
369 bd->bi_memsize = (16 * 1024 * 1024);
370 bd->bi_intfreq = 48000000;
371 bd->bi_busfreq = 48000000;
372}
373#endif /* BSEIP */
374
375#ifdef CONFIG_FADS
376/* Build a board information structure for the FADS.
377 */
378void
379embed_config(bd_t **bdp)
380{
381 u_char *cp;
382 int i;
383 bd_t *bd;
384
385 bd = &bdinfo;
386 *bdp = bd;
387
388 /* Just fill in some known values.
389 */
390 bd->bi_baudrate = 9600;
391
392 /* Use default enet.
393 */
394 cp = (u_char *)def_enet_addr;
395 for (i=0; i<6; i++) {
396 bd->bi_enetaddr[i] = *cp++;
397 }
398
399 bd->bi_memstart = 0;
400 bd->bi_memsize = (8 * 1024 * 1024);
401 bd->bi_intfreq = 40000000;
402 bd->bi_busfreq = 40000000;
403}
404#endif /* FADS */
405
406#ifdef CONFIG_8260
407/* Compute 8260 clock values if the rom doesn't provide them.
408 */
409static unsigned char bus2core_8260[] = {
410/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
411 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2,
412 6, 5, 13, 2, 14, 4, 15, 2, 3, 11, 8, 10, 16, 12, 7, 2,
413};
414
415static void
416clk_8260(bd_t *bd)
417{
418 uint scmr, vco_out, clkin;
419 uint plldf, pllmf, corecnf;
420 volatile cpm2_map_t *ip;
421
422 ip = (cpm2_map_t *)CPM_MAP_ADDR;
423 scmr = ip->im_clkrst.car_scmr;
424
425 /* The clkin is always bus frequency.
426 */
427 clkin = bd->bi_busfreq;
428
429 /* Collect the bits from the scmr.
430 */
431 plldf = (scmr >> 12) & 1;
432 pllmf = scmr & 0xfff;
433 corecnf = (scmr >> 24) &0x1f;
434
435 /* This is arithmetic from the 8260 manual.
436 */
437 vco_out = clkin / (plldf + 1);
438 vco_out *= 2 * (pllmf + 1);
439 bd->bi_vco = vco_out; /* Save for later */
440
441 bd->bi_cpmfreq = vco_out / 2; /* CPM Freq, in MHz */
442 bd->bi_intfreq = bd->bi_busfreq * bus2core_8260[corecnf] / 2;
443
444 /* Set Baud rate divisor. The power up default is divide by 16,
445 * but we set it again here in case it was changed.
446 */
447 ip->im_clkrst.car_sccr = 1; /* DIV 16 BRG */
448 bd->bi_brgfreq = vco_out / 16;
449}
450
451static unsigned char bus2core_8280[] = {
452/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
453 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2,
454 6, 5, 13, 2, 14, 2, 15, 2, 3, 2, 2, 2, 16, 2, 2, 2,
455};
456
457static void
458clk_8280(bd_t *bd)
459{
460 uint scmr, main_clk, clkin;
461 uint pllmf, corecnf;
462 volatile cpm2_map_t *ip;
463
464 ip = (cpm2_map_t *)CPM_MAP_ADDR;
465 scmr = ip->im_clkrst.car_scmr;
466
467 /* The clkin is always bus frequency.
468 */
469 clkin = bd->bi_busfreq;
470
471 /* Collect the bits from the scmr.
472 */
473 pllmf = scmr & 0xf;
474 corecnf = (scmr >> 24) & 0x1f;
475
476 /* This is arithmetic from the 8280 manual.
477 */
478 main_clk = clkin * (pllmf + 1);
479
480 bd->bi_cpmfreq = main_clk / 2; /* CPM Freq, in MHz */
481 bd->bi_intfreq = bd->bi_busfreq * bus2core_8280[corecnf] / 2;
482
483 /* Set Baud rate divisor. The power up default is divide by 16,
484 * but we set it again here in case it was changed.
485 */
486 ip->im_clkrst.car_sccr = (ip->im_clkrst.car_sccr & 0x3) | 0x1;
487 bd->bi_brgfreq = main_clk / 16;
488}
489#endif
490
491#ifdef CONFIG_SBC82xx
492void
493embed_config(bd_t **bdp)
494{
495 u_char *cp;
496 int i;
497 bd_t *bd;
498 unsigned long pvr;
499
500 bd = *bdp;
501
502 bd = &bdinfo;
503 *bdp = bd;
504 bd->bi_baudrate = 9600;
505 bd->bi_memsize = 256 * 1024 * 1024; /* just a guess */
506
507 cp = (void*)SBC82xx_MACADDR_NVRAM_SCC1;
508 memcpy(bd->bi_enetaddr, cp, 6);
509
510 /* can busfreq be calculated? */
511 pvr = mfspr(SPRN_PVR);
512 if ((pvr & 0xffff0000) == 0x80820000) {
513 bd->bi_busfreq = 100000000;
514 clk_8280(bd);
515 } else {
516 bd->bi_busfreq = 66000000;
517 clk_8260(bd);
518 }
519
520}
521#endif /* SBC82xx */
522
523#if defined(CONFIG_EST8260) || defined(CONFIG_TQM8260)
524void
525embed_config(bd_t **bdp)
526{
527 u_char *cp;
528 int i;
529 bd_t *bd;
530
531 bd = *bdp;
532#if 0
533 /* This is actually provided by my boot rom. I have it
534 * here for those people that may load the kernel with
535 * a JTAG/COP tool and not the rom monitor.
536 */
537 bd->bi_baudrate = 115200;
538 bd->bi_intfreq = 200000000;
539 bd->bi_busfreq = 66666666;
540 bd->bi_cpmfreq = 66666666;
541 bd->bi_brgfreq = 33333333;
542 bd->bi_memsize = 16 * 1024 * 1024;
543#else
544 /* The boot rom passes these to us in MHz. Linux now expects
545 * them to be in Hz.
546 */
547 bd->bi_intfreq *= 1000000;
548 bd->bi_busfreq *= 1000000;
549 bd->bi_cpmfreq *= 1000000;
550 bd->bi_brgfreq *= 1000000;
551#endif
552
553 cp = (u_char *)def_enet_addr;
554 for (i=0; i<6; i++) {
555 bd->bi_enetaddr[i] = *cp++;
556 }
557}
558#endif /* EST8260 */
559
560#ifdef CONFIG_SBS8260
561void
562embed_config(bd_t **bdp)
563{
564 u_char *cp;
565 int i;
566 bd_t *bd;
567
568 /* This should provided by the boot rom.
569 */
570 bd = &bdinfo;
571 *bdp = bd;
572 bd->bi_baudrate = 9600;
573 bd->bi_memsize = 64 * 1024 * 1024;
574
575 /* Set all of the clocks. We have to know the speed of the
576 * external clock. The development board had 66 MHz.
577 */
578 bd->bi_busfreq = 66666666;
579 clk_8260(bd);
580
581 /* I don't know how to compute this yet.
582 */
583 bd->bi_intfreq = 133000000;
584
585
586 cp = (u_char *)def_enet_addr;
587 for (i=0; i<6; i++) {
588 bd->bi_enetaddr[i] = *cp++;
589 }
590}
591#endif /* SBS8260 */
592
593#ifdef CONFIG_RPX8260
594void
595embed_config(bd_t **bdp)
596{
597 u_char *cp, *keyvals;
598 int i;
599 bd_t *bd;
600
601 keyvals = (u_char *)*bdp;
602
603 bd = &bdinfo;
604 *bdp = bd;
605
606 /* This is almost identical to the RPX-Lite/Classic functions
607 * on the 8xx boards. It would be nice to have a key lookup
608 * function in a string, but the format of all of the fields
609 * is slightly different.
610 */
611 cp = keyvals;
612 for (;;) {
613 if (*cp == 'E') {
614 cp++;
615 if (*cp == 'A') {
616 cp += 2;
617 rpx_eth(bd, cp);
618 }
619 }
620 if (*cp == 'S') {
621 cp++;
622 if (*cp == 'B') {
623 cp += 2;
624 bd->bi_baudrate = rpx_baseten(cp);
625 }
626 }
627 if (*cp == 'D') {
628 cp++;
629 if (*cp == '1') {
630 cp += 2;
631 bd->bi_memsize = rpx_baseten(cp) * 1024 * 1024;
632 }
633 }
634 if (*cp == 'X') {
635 cp++;
636 if (*cp == 'T') {
637 cp += 2;
638 bd->bi_busfreq = rpx_baseten(cp);
639 }
640 }
641 if (*cp == 'N') {
642 cp++;
643 if (*cp == 'V') {
644 cp += 2;
645 bd->bi_nvsize = rpx_baseten(cp) * 1024 * 1024;
646 }
647 }
648
649 /* Scan to the end of the record.
650 */
651 while ((*cp != '\n') && (*cp != 0xff))
652 cp++;
653
654 /* If the next character is a 0 or ff, we are done.
655 */
656 cp++;
657 if ((*cp == 0) || (*cp == 0xff))
658 break;
659 }
660 bd->bi_memstart = 0;
661
662 /* The memory size includes both the 60x and local bus DRAM.
663 * I don't want to use the local bus DRAM for real memory,
664 * so subtract it out. It would be nice if they were separate
665 * keys.
666 */
667 bd->bi_memsize -= 32 * 1024 * 1024;
668
669 /* Set all of the clocks. We have to know the speed of the
670 * external clock.
671 */
672 clk_8260(bd);
673
674 /* I don't know how to compute this yet.
675 */
676 bd->bi_intfreq = 200000000;
677}
678#endif /* RPX6 for testing */
679
680#ifdef CONFIG_ADS8260
681void
682embed_config(bd_t **bdp)
683{
684 u_char *cp;
685 int i;
686 bd_t *bd;
687
688 /* This should provided by the boot rom.
689 */
690 bd = &bdinfo;
691 *bdp = bd;
692 bd->bi_baudrate = 9600;
693 bd->bi_memsize = 16 * 1024 * 1024;
694
695 /* Set all of the clocks. We have to know the speed of the
696 * external clock. The development board had 66 MHz.
697 */
698 bd->bi_busfreq = 66666666;
699 clk_8260(bd);
700
701 /* I don't know how to compute this yet.
702 */
703 bd->bi_intfreq = 200000000;
704
705
706 cp = (u_char *)def_enet_addr;
707 for (i=0; i<6; i++) {
708 bd->bi_enetaddr[i] = *cp++;
709 }
710}
711#endif /* ADS8260 */
712
713#ifdef CONFIG_WILLOW
714void
715embed_config(bd_t **bdp)
716{
717 u_char *cp;
718 int i;
719 bd_t *bd;
720
721 /* Willow has Open Firmware....I should learn how to get this
722 * information from it.
723 */
724 bd = &bdinfo;
725 *bdp = bd;
726 bd->bi_baudrate = 9600;
727 bd->bi_memsize = 32 * 1024 * 1024;
728
729 /* Set all of the clocks. We have to know the speed of the
730 * external clock. The development board had 66 MHz.
731 */
732 bd->bi_busfreq = 66666666;
733 clk_8260(bd);
734
735 /* I don't know how to compute this yet.
736 */
737 bd->bi_intfreq = 200000000;
738
739
740 cp = (u_char *)def_enet_addr;
741 for (i=0; i<6; i++) {
742 bd->bi_enetaddr[i] = *cp++;
743 }
744}
745#endif /* WILLOW */
746
747#if defined(CONFIG_XILINX_ML300) || defined(CONFIG_XILINX_ML403)
748void
749embed_config(bd_t ** bdp)
750{
751 static const unsigned long line_size = 32;
752 static const unsigned long congruence_classes = 256;
753 unsigned long addr;
754 unsigned long dccr;
755 uint8_t* cp;
756 bd_t *bd;
757 int i;
758
759 /*
760 * Invalidate the data cache if the data cache is turned off.
761 * - The 405 core does not invalidate the data cache on power-up
762 * or reset but does turn off the data cache. We cannot assume
763 * that the cache contents are valid.
764 * - If the data cache is turned on this must have been done by
765 * a bootloader and we assume that the cache contents are
766 * valid.
767 */
768 __asm__("mfdccr %0": "=r" (dccr));
769 if (dccr == 0) {
770 for (addr = 0;
771 addr < (congruence_classes * line_size);
772 addr += line_size) {
773 __asm__("dccci 0,%0": :"b"(addr));
774 }
775 }
776
777 bd = &bdinfo;
778 *bdp = bd;
779 bd->bi_memsize = XPAR_DDR_0_SIZE;
780 bd->bi_intfreq = XPAR_CORE_CLOCK_FREQ_HZ;
781 bd->bi_busfreq = XPAR_PLB_CLOCK_FREQ_HZ;
782 bd->bi_pci_busfreq = XPAR_PCI_0_CLOCK_FREQ_HZ;
783
784 /* Copy the default ethernet address */
785 cp = (u_char *)def_enet_addr;
786 for (i=0; i<6; i++)
787 bd->bi_enetaddr[i] = *cp++;
788
789 timebase_period_ns = 1000000000 / bd->bi_tbfreq;
790 /* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */
791}
792#endif /* CONFIG_XILINX_ML300 || CONFIG_XILINX_ML403 */
793
794#ifdef CONFIG_IBM_OPENBIOS
795/* This could possibly work for all treeboot roms.
796*/
797#if defined(CONFIG_BUBINGA)
798#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */
799#else
800#define BOARD_INFO_VECTOR 0xFFFE0B50
801#endif
802
803void
804embed_config(bd_t **bdp)
805{
806 u_char *cp;
807 int i;
808 bd_t *bd, *treeboot_bd;
809 bd_t *(*get_board_info)(void) =
810 (bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR);
811#if !defined(CONFIG_STB03xxx)
812
813 /* shut down the Ethernet controller that the boot rom
814 * sometimes leaves running.
815 */
816 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
817 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
818 out_be32((volatile u32*)EMAC0_BASE,0x20000000); /* then reset EMAC */
819#endif
820
821 bd = &bdinfo;
822 *bdp = bd;
823 if ((treeboot_bd = get_board_info()) != NULL) {
824 memcpy(bd, treeboot_bd, sizeof(bd_t));
825 }
826 else {
827 /* Hmmm...better try to stuff some defaults.
828 */
829 bd->bi_memsize = 16 * 1024 * 1024;
830 cp = (u_char *)def_enet_addr;
831 for (i=0; i<6; i++) {
832 /* I should probably put different ones here,
833 * hopefully only one is used.
834 */
835 bd->BD_EMAC_ADDR(0,i) = *cp;
836
837#ifdef CONFIG_PCI
838 bd->bi_pci_enetaddr[i] = *cp++;
839#endif
840 }
841 bd->bi_tbfreq = 200 * 1000 * 1000;
842 bd->bi_intfreq = 200000000;
843 bd->bi_busfreq = 100000000;
844#ifdef CONFIG_PCI
845 bd->bi_pci_busfreq = 66666666;
846#endif
847 }
848 /* Yeah, this look weird, but on Redwood 4 they are
849 * different object in the structure. Sincr Redwwood 5
850 * and Redwood 6 use OpenBIOS, it requires a special value.
851 */
852#if defined(CONFIG_REDWOOD_5) || defined (CONFIG_REDWOOD_6)
853 bd->bi_tbfreq = 27 * 1000 * 1000;
854#endif
855 timebase_period_ns = 1000000000 / bd->bi_tbfreq;
856}
857#endif /* CONFIG_IBM_OPENBIOS */
858
859#ifdef CONFIG_EP405
860#include <linux/serial_reg.h>
861
862void
863embed_config(bd_t **bdp)
864{
865 u32 chcr0;
866 u_char *cp;
867 bd_t *bd;
868
869 /* Different versions of the PlanetCore firmware vary in how
870 they set up the serial port - in particular whether they
871 use the internal or external serial clock for UART0. Make
872 sure the UART is in a known state. */
873 /* FIXME: We should use the board's 11.0592MHz external serial
874 clock - it will be more accurate for serial rates. For
875 now, however the baud rates in ep405.h are for the internal
876 clock. */
877 chcr0 = mfdcr(DCRN_CHCR0);
878 if ( (chcr0 & 0x1fff) != 0x103e ) {
879 mtdcr(DCRN_CHCR0, (chcr0 & 0xffffe000) | 0x103e);
880 /* The following tricks serial_init() into resetting the baud rate */
881 writeb(0, UART0_IO_BASE + UART_LCR);
882 }
883
884 /* We haven't seen actual problems with the EP405 leaving the
885 * EMAC running (as we have on Walnut). But the registers
886 * suggest it may not be left completely quiescent. Reset it
887 * just to be sure. */
888 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
889 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
890 out_be32((unsigned *)EMAC0_BASE,0x20000000); /* then reset EMAC */
891
892 bd = &bdinfo;
893 *bdp = bd;
894#if 1
895 cp = (u_char *)0xF0000EE0;
896 for (;;) {
897 if (*cp == 'E') {
898 cp++;
899 if (*cp == 'A') {
900 cp += 2;
901 rpx_eth(bd, cp);
902 }
903 }
904
905 if (*cp == 'D') {
906 cp++;
907 if (*cp == '1') {
908 cp += 2;
909 rpx_memsize(bd, cp);
910 }
911 }
912
913 if (*cp == 'N') {
914 cp++;
915 if (*cp == 'V') {
916 cp += 2;
917 rpx_nvramsize(bd, cp);
918 }
919 }
920 while ((*cp != '\n') && (*cp != 0xff))
921 cp++;
922
923 cp++;
924 if ((*cp == 0) || (*cp == 0xff))
925 break;
926 }
927 bd->bi_intfreq = 200000000;
928 bd->bi_busfreq = 100000000;
929 bd->bi_pci_busfreq= 33000000 ;
930#else
931
932 bd->bi_memsize = 64000000;
933 bd->bi_intfreq = 200000000;
934 bd->bi_busfreq = 100000000;
935 bd->bi_pci_busfreq= 33000000 ;
936#endif
937}
938#endif
diff --git a/arch/ppc/boot/simple/head.S b/arch/ppc/boot/simple/head.S
deleted file mode 100644
index 1b4d7b1d4ec1..000000000000
--- a/arch/ppc/boot/simple/head.S
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Initial board bringup code for many different boards.
3 *
4 * Author: Tom Rini
5 * trini@mvista.com
6 * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
7 *
8 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <asm/reg.h>
15#include <asm/cache.h>
16#include <asm/ppc_asm.h>
17
18 .text
19
20/*
21 * Begin at some arbitrary location in RAM or Flash
22 * Initialize core registers
23 * Configure memory controller (Not executing from RAM)
24 * Move the boot code to the link address (8M)
25 * Setup C stack
26 * Initialize UART
27 * Decompress the kernel to 0x0
28 * Jump to the kernel entry
29 *
30 */
31
32 .globl start
33start:
34 bl start_
35#ifdef CONFIG_IBM_OPENBIOS
36 /* The IBM "Tree" bootrom knows that the address of the bootrom
37 * read only structure is 4 bytes after _start.
38 */
39 .long 0x62726f6d # structure ID - "brom"
40 .long 0x5f726f00 # - "_ro\0"
41 .long 1 # structure version
42 .long bootrom_cmdline # address of *bootrom_cmdline
43#endif
44
45start_:
46#ifdef CONFIG_FORCE
47 /* We have some really bad firmware. We must disable the L1
48 * icache/dcache now or the board won't boot.
49 */
50 li r4,0x0000
51 isync
52 mtspr SPRN_HID0,r4
53 sync
54 isync
55#endif
56
57#if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP)
58 mr r29,r3 /* On the MBX860, r3 is the board info pointer.
59 * On the RPXSUPER, r3 points to the NVRAM
60 * configuration keys.
61 * On PReP, r3 is the pointer to the residual data.
62 */
63#endif
64
65#if defined(CONFIG_XILINX_VIRTEX_4_FX)
66 /* PPC errata 213: only for Virtex-4 FX */
67 mfccr0 0
68 oris 0,0,0x50000000@h
69 mtccr0 0
70#endif
71
72 mflr r3 /* Save our actual starting address. */
73
74 /* The following functions we call must not modify r3 or r4.....
75 */
76#ifdef CONFIG_6xx
77 /* On PReP we must look at the OpenFirmware pointer and sanity
78 * test it. On other platforms, we disable the MMU right now
79 * and other bits.
80 */
81#ifdef CONFIG_PPC_PREP
82/*
83 * Save the OF pointer to r25, but only if the entry point is in a sane
84 * location; if not we store 0. If there is no entry point, or it is
85 * invalid, we establish the default MSR value immediately. Otherwise,
86 * we defer doing that, to allow OF functions to be called, until we
87 * begin uncompressing the kernel.
88 */
89 lis r8,0x0fff /* r8 = 0x0fffffff */
90 ori r8,r8,0xffff
91
92 subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */
93 subfe r8,r8,r8
94 nand r8,r8,r8
95
96 and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */
97 bne+ haveOF
98
99 li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
100 mtmsr r8
101 isync
102haveOF:
103 mr r25,r5
104#else
105 bl disable_6xx_mmu
106#endif
107 bl disable_6xx_l1cache
108
109 CLEAR_CACHES
110#endif
111
112#ifdef CONFIG_8xx
113 mfmsr r8 /* Turn off interrupts */
114 li r9,0
115 ori r9,r9,MSR_EE
116 andc r8,r8,r9
117 mtmsr r8
118
119 /* We do this because some boot roms don't initialize the
120 * processor correctly. Don't do this if you want to debug
121 * using a BDM device.
122 */
123 li r4,0 /* Zero DER to prevent FRZ */
124 mtspr SPRN_DER,r4
125#endif
126
127#if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP)
128 mr r4,r29 /* put the board info pointer where the relocate
129 * routine will find it
130 */
131#endif
132
133 /* Get the load address.
134 */
135 subi r3, r3, 4 /* Get the actual IP, not NIP */
136 b relocate
137
diff --git a/arch/ppc/boot/simple/iic.c b/arch/ppc/boot/simple/iic.c
deleted file mode 100644
index 5e91489426b4..000000000000
--- a/arch/ppc/boot/simple/iic.c
+++ /dev/null
@@ -1,214 +0,0 @@
1/* Minimal support functions to read configuration from IIC EEPROMS
2 * on MPC8xx boards. Originally written for RPGC RPX-Lite.
3 * Dan Malek (dmalek@jlc.net).
4 */
5#include <linux/types.h>
6#include <asm/uaccess.h>
7#include <asm/mpc8xx.h>
8#include <asm/cpm1.h>
9
10
11/* IIC functions.
12 * These are just the basic master read/write operations so we can
13 * examine serial EEPROM.
14 */
15void iic_read(uint devaddr, u_char *buf, uint offset, uint count);
16
17static int iic_init_done;
18
19static void
20iic_init(void)
21{
22 volatile iic_t *iip;
23 volatile i2c8xx_t *i2c;
24 volatile cpm8xx_t *cp;
25 volatile immap_t *immap;
26 uint dpaddr;
27
28 immap = (immap_t *)IMAP_ADDR;
29 cp = (cpm8xx_t *)&(immap->im_cpm);
30
31 /* Reset the CPM. This is necessary on the 860 processors
32 * that may have started the SCC1 ethernet without relocating
33 * the IIC.
34 * This also stops the Ethernet in case we were loaded by a
35 * BOOTP rom monitor.
36 */
37 cp->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
38
39 /* Wait for it.
40 */
41 while (cp->cp_cpcr & (CPM_CR_RST | CPM_CR_FLG));
42
43 /* Remove any microcode patches. We will install our own
44 * later.
45 */
46 cp->cp_cpmcr1 = 0;
47 cp->cp_cpmcr2 = 0;
48 cp->cp_cpmcr3 = 0;
49 cp->cp_cpmcr4 = 0;
50 cp->cp_rccr = 0;
51
52 iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
53 i2c = (i2c8xx_t *)&(immap->im_i2c);
54
55 /* Initialize Port B IIC pins.
56 */
57 cp->cp_pbpar |= 0x00000030;
58 cp->cp_pbdir |= 0x00000030;
59 cp->cp_pbodr |= 0x00000030;
60
61 /* Initialize the parameter ram.
62 */
63
64 /* Allocate space for a two transmit and one receive buffer
65 * descriptor in the DP ram.
66 * For now, this address seems OK, but it may have to
67 * change with newer versions of the firmware.
68 */
69 dpaddr = 0x0840;
70
71 /* Set up the IIC parameters in the parameter ram.
72 */
73 iip->iic_tbase = dpaddr;
74 iip->iic_rbase = dpaddr + (2 * sizeof(cbd_t));
75
76 iip->iic_tfcr = SMC_EB;
77 iip->iic_rfcr = SMC_EB;
78
79 /* This should really be done by the reader/writer.
80 */
81 iip->iic_mrblr = 128;
82
83 /* Initialize Tx/Rx parameters.
84 */
85 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
86 while (cp->cp_cpcr & CPM_CR_FLG);
87
88 /* Select an arbitrary address. Just make sure it is unique.
89 */
90 i2c->i2c_i2add = 0x34;
91
92 /* Make clock run maximum slow.
93 */
94 i2c->i2c_i2brg = 7;
95
96 /* Disable interrupts.
97 */
98 i2c->i2c_i2cmr = 0;
99 i2c->i2c_i2cer = 0xff;
100
101 /* Enable SDMA.
102 */
103 immap->im_siu_conf.sc_sdcr = 1;
104
105 iic_init_done = 1;
106}
107
108/* Read from IIC.
109 * Caller provides device address, memory buffer, and byte count.
110 */
111static u_char iitemp[32];
112
113void
114iic_read(uint devaddr, u_char *buf, uint offset, uint count)
115{
116 volatile iic_t *iip;
117 volatile i2c8xx_t *i2c;
118 volatile cbd_t *tbdf, *rbdf;
119 volatile cpm8xx_t *cp;
120 volatile immap_t *immap;
121 u_char *tb;
122 uint temp;
123
124 /* If the interface has not been initialized, do that now.
125 */
126 if (!iic_init_done)
127 iic_init();
128
129 immap = (immap_t *)IMAP_ADDR;
130 cp = (cpm8xx_t *)&(immap->im_cpm);
131
132 iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
133 i2c = (i2c8xx_t *)&(immap->im_i2c);
134
135 tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
136 rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
137
138 /* Send a "dummy write" operation. This is a write request with
139 * only the offset sent, followed by another start condition.
140 * This will ensure we start reading from the first location
141 * of the EEPROM.
142 */
143 tb = iitemp;
144 tb = (u_char *)(((uint)tb + 15) & ~15);
145 tbdf->cbd_bufaddr = (int)tb;
146 *tb = devaddr & 0xfe; /* Device address */
147 *(tb+1) = offset; /* Offset */
148 tbdf->cbd_datlen = 2; /* Length */
149 tbdf->cbd_sc =
150 BD_SC_READY | BD_SC_LAST | BD_SC_WRAP | BD_IIC_START;
151
152 i2c->i2c_i2mod = 1; /* Enable */
153 i2c->i2c_i2cer = 0xff;
154 i2c->i2c_i2com = 0x81; /* Start master */
155
156 /* Wait for IIC transfer.
157 */
158#if 0
159 while ((i2c->i2c_i2cer & 3) == 0);
160
161 if (tbdf->cbd_sc & BD_SC_READY)
162 printf("IIC ra complete but tbuf ready\n");
163#else
164 temp = 10000000;
165 while ((tbdf->cbd_sc & BD_SC_READY) && (temp != 0))
166 temp--;
167#if 0
168 /* We can't do this...there is no serial port yet!
169 */
170 if (temp == 0) {
171 printf("Timeout reading EEPROM\n");
172 return;
173 }
174#endif
175#endif
176
177 /* Chip errata, clear enable.
178 */
179 i2c->i2c_i2mod = 0;
180
181 /* To read, we need an empty buffer of the proper length.
182 * All that is used is the first byte for address, the remainder
183 * is just used for timing (and doesn't really have to exist).
184 */
185 tbdf->cbd_bufaddr = (int)tb;
186 *tb = devaddr | 1; /* Device address */
187 rbdf->cbd_bufaddr = (uint)buf; /* Desination buffer */
188 tbdf->cbd_datlen = rbdf->cbd_datlen = count + 1; /* Length */
189 tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP | BD_IIC_START;
190 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
191
192 /* Chip bug, set enable here.
193 */
194 i2c->i2c_i2mod = 1; /* Enable */
195 i2c->i2c_i2cer = 0xff;
196 i2c->i2c_i2com = 0x81; /* Start master */
197
198 /* Wait for IIC transfer.
199 */
200#if 0
201 while ((i2c->i2c_i2cer & 1) == 0);
202
203 if (rbdf->cbd_sc & BD_SC_EMPTY)
204 printf("IIC read complete but rbuf empty\n");
205#else
206 temp = 10000000;
207 while ((tbdf->cbd_sc & BD_SC_READY) && (temp != 0))
208 temp--;
209#endif
210
211 /* Chip errata, clear enable.
212 */
213 i2c->i2c_i2mod = 0;
214}
diff --git a/arch/ppc/boot/simple/m8260_tty.c b/arch/ppc/boot/simple/m8260_tty.c
deleted file mode 100644
index d770947e9b8f..000000000000
--- a/arch/ppc/boot/simple/m8260_tty.c
+++ /dev/null
@@ -1,325 +0,0 @@
1/* Minimal serial functions needed to send messages out the serial
2 * port on SMC1.
3 */
4#include <linux/types.h>
5#include <asm/mpc8260.h>
6#include <asm/cpm2.h>
7#include <asm/immap_cpm2.h>
8
9uint no_print;
10extern char *params[];
11extern int nparams;
12static u_char cons_hold[128], *sgptr;
13static int cons_hold_cnt;
14
15/* If defined, enables serial console. The value (1 through 4)
16 * should designate which SCC is used, but this isn't complete. Only
17 * SCC1 is known to work at this time.
18 * We're only linked if SERIAL_CPM_CONSOLE=y, so we only need to test
19 * SERIAL_CPM_SCC1.
20 */
21#ifdef CONFIG_SERIAL_CPM_SCC1
22#define SCC_CONSOLE 1
23#endif
24
25unsigned long
26serial_init(int ignored, bd_t *bd)
27{
28#ifdef SCC_CONSOLE
29 volatile scc_t *sccp;
30 volatile scc_uart_t *sup;
31#else
32 volatile smc_t *sp;
33 volatile smc_uart_t *up;
34#endif
35 volatile cbd_t *tbdf, *rbdf;
36 volatile cpm2_map_t *ip;
37 volatile iop_cpm2_t *io;
38 volatile cpm_cpm2_t *cp;
39 uint dpaddr, memaddr;
40
41 ip = (cpm2_map_t *)CPM_MAP_ADDR;
42 cp = &ip->im_cpm;
43 io = &ip->im_ioport;
44
45 /* Perform a reset.
46 */
47 cp->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
48
49 /* Wait for it.
50 */
51 while (cp->cp_cpcr & CPM_CR_FLG);
52
53#ifdef CONFIG_ADS8260
54 /* Enable the RS-232 transceivers.
55 */
56 *(volatile uint *)(BCSR_ADDR + 4) &=
57 ~(BCSR1_RS232_EN1 | BCSR1_RS232_EN2);
58#endif
59
60#ifdef SCC_CONSOLE
61 sccp = (scc_t *)&(ip->im_scc[SCC_CONSOLE-1]);
62 sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
63 sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
64 sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
65
66 /* Use Port D for SCC1 instead of other functions.
67 */
68 io->iop_ppard |= 0x00000003;
69 io->iop_psord &= ~0x00000001; /* Rx */
70 io->iop_psord |= 0x00000002; /* Tx */
71 io->iop_pdird &= ~0x00000001; /* Rx */
72 io->iop_pdird |= 0x00000002; /* Tx */
73
74#else
75 sp = (smc_t*)&(ip->im_smc[0]);
76 *(ushort *)(&ip->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
77 up = (smc_uart_t *)&ip->im_dprambase[PROFF_SMC1];
78
79 /* Disable transmitter/receiver.
80 */
81 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
82
83 /* Use Port D for SMC1 instead of other functions.
84 */
85 io->iop_ppard |= 0x00c00000;
86 io->iop_pdird |= 0x00400000;
87 io->iop_pdird &= ~0x00800000;
88 io->iop_psord &= ~0x00c00000;
89#endif
90
91 /* Allocate space for two buffer descriptors in the DP ram.
92 * For now, this address seems OK, but it may have to
93 * change with newer versions of the firmware.
94 */
95 dpaddr = 0x0800;
96
97 /* Grab a few bytes from the top of memory.
98 */
99 memaddr = (bd->bi_memsize - 256) & ~15;
100
101 /* Set the physical address of the host memory buffers in
102 * the buffer descriptors.
103 */
104 rbdf = (cbd_t *)&ip->im_dprambase[dpaddr];
105 rbdf->cbd_bufaddr = memaddr;
106 rbdf->cbd_sc = 0;
107 tbdf = rbdf + 1;
108 tbdf->cbd_bufaddr = memaddr+128;
109 tbdf->cbd_sc = 0;
110
111 /* Set up the uart parameters in the parameter ram.
112 */
113#ifdef SCC_CONSOLE
114 sup->scc_genscc.scc_rbase = dpaddr;
115 sup->scc_genscc.scc_tbase = dpaddr + sizeof(cbd_t);
116
117 /* Set up the uart parameters in the
118 * parameter ram.
119 */
120 sup->scc_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB;
121 sup->scc_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB;
122
123 sup->scc_genscc.scc_mrblr = 128;
124 sup->scc_maxidl = 8;
125 sup->scc_brkcr = 1;
126 sup->scc_parec = 0;
127 sup->scc_frmec = 0;
128 sup->scc_nosec = 0;
129 sup->scc_brkec = 0;
130 sup->scc_uaddr1 = 0;
131 sup->scc_uaddr2 = 0;
132 sup->scc_toseq = 0;
133 sup->scc_char1 = 0x8000;
134 sup->scc_char2 = 0x8000;
135 sup->scc_char3 = 0x8000;
136 sup->scc_char4 = 0x8000;
137 sup->scc_char5 = 0x8000;
138 sup->scc_char6 = 0x8000;
139 sup->scc_char7 = 0x8000;
140 sup->scc_char8 = 0x8000;
141 sup->scc_rccm = 0xc0ff;
142
143 /* Send the CPM an initialize command.
144 */
145 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
146 CPM_CR_INIT_TRX) | CPM_CR_FLG;
147 while (cp->cp_cpcr & CPM_CR_FLG);
148
149 /* Set UART mode, 8 bit, no parity, one stop.
150 * Enable receive and transmit.
151 */
152 sccp->scc_gsmrh = 0;
153 sccp->scc_gsmrl =
154 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
155
156 /* Disable all interrupts and clear all pending
157 * events.
158 */
159 sccp->scc_sccm = 0;
160 sccp->scc_scce = 0xffff;
161 sccp->scc_dsr = 0x7e7e;
162 sccp->scc_psmr = 0x3000;
163
164 /* Wire BRG1 to SCC1. The console driver will take care of
165 * others.
166 */
167 ip->im_cpmux.cmx_scr = 0;
168#else
169 up->smc_rbase = dpaddr;
170 up->smc_tbase = dpaddr+sizeof(cbd_t);
171 up->smc_rfcr = CPMFCR_EB;
172 up->smc_tfcr = CPMFCR_EB;
173 up->smc_brklen = 0;
174 up->smc_brkec = 0;
175 up->smc_brkcr = 0;
176 up->smc_mrblr = 128;
177 up->smc_maxidl = 8;
178
179 /* Set UART mode, 8 bit, no parity, one stop.
180 * Enable receive and transmit.
181 */
182 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
183
184 /* Mask all interrupts and remove anything pending.
185 */
186 sp->smc_smcm = 0;
187 sp->smc_smce = 0xff;
188
189 /* Set up the baud rate generator.
190 */
191 ip->im_cpmux.cmx_smr = 0;
192#endif
193
194 /* The baud rate divisor needs to be coordinated with clk_8260().
195 */
196 ip->im_brgc1 =
197 (((bd->bi_brgfreq/16) / bd->bi_baudrate) << 1) |
198 CPM_BRG_EN;
199
200 /* Make the first buffer the only buffer.
201 */
202 tbdf->cbd_sc |= BD_SC_WRAP;
203 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
204
205 /* Initialize Tx/Rx parameters.
206 */
207#ifdef SCC_CONSOLE
208 sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
209#else
210 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
211 while (cp->cp_cpcr & CPM_CR_FLG);
212
213 /* Enable transmitter/receiver.
214 */
215 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
216#endif
217
218 /* This is ignored.
219 */
220 return 0;
221}
222
223int
224serial_readbuf(u_char *cbuf)
225{
226 volatile cbd_t *rbdf;
227 volatile char *buf;
228#ifdef SCC_CONSOLE
229 volatile scc_uart_t *sup;
230#else
231 volatile smc_uart_t *up;
232#endif
233 volatile cpm2_map_t *ip;
234 int i, nc;
235
236 ip = (cpm2_map_t *)CPM_MAP_ADDR;
237
238#ifdef SCC_CONSOLE
239 sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
240 rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];
241#else
242 up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
243 rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase];
244#endif
245
246 /* Wait for character to show up.
247 */
248 buf = (char *)rbdf->cbd_bufaddr;
249 while (rbdf->cbd_sc & BD_SC_EMPTY);
250 nc = rbdf->cbd_datlen;
251 for (i=0; i<nc; i++)
252 *cbuf++ = *buf++;
253 rbdf->cbd_sc |= BD_SC_EMPTY;
254
255 return(nc);
256}
257
258void
259serial_putc(void *ignored, const char c)
260{
261 volatile cbd_t *tbdf;
262 volatile char *buf;
263#ifdef SCC_CONSOLE
264 volatile scc_uart_t *sup;
265#else
266 volatile smc_uart_t *up;
267#endif
268 volatile cpm2_map_t *ip;
269
270 ip = (cpm2_map_t *)CPM_MAP_ADDR;
271#ifdef SCC_CONSOLE
272 sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
273 tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase];
274#else
275 up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
276 tbdf = (cbd_t *)&ip->im_dprambase[up->smc_tbase];
277#endif
278
279 /* Wait for last character to go.
280 */
281 buf = (char *)tbdf->cbd_bufaddr;
282 while (tbdf->cbd_sc & BD_SC_READY);
283
284 *buf = c;
285 tbdf->cbd_datlen = 1;
286 tbdf->cbd_sc |= BD_SC_READY;
287}
288
289char
290serial_getc(void *ignored)
291{
292 char c;
293
294 if (cons_hold_cnt <= 0) {
295 cons_hold_cnt = serial_readbuf(cons_hold);
296 sgptr = cons_hold;
297 }
298 c = *sgptr++;
299 cons_hold_cnt--;
300
301 return(c);
302}
303
304int
305serial_tstc(void *ignored)
306{
307 volatile cbd_t *rbdf;
308#ifdef SCC_CONSOLE
309 volatile scc_uart_t *sup;
310#else
311 volatile smc_uart_t *up;
312#endif
313 volatile cpm2_map_t *ip;
314
315 ip = (cpm2_map_t *)CPM_MAP_ADDR;
316#ifdef SCC_CONSOLE
317 sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
318 rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];
319#else
320 up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]);
321 rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase];
322#endif
323
324 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
325}
diff --git a/arch/ppc/boot/simple/m8xx_tty.c b/arch/ppc/boot/simple/m8xx_tty.c
deleted file mode 100644
index f28924e6aeb4..000000000000
--- a/arch/ppc/boot/simple/m8xx_tty.c
+++ /dev/null
@@ -1,289 +0,0 @@
1/* Minimal serial functions needed to send messages out the serial
2 * port on the MBX console.
3 *
4 * The MBX uses SMC1 for the serial port. We reset the port and use
5 * only the first BD that EPPC-Bug set up as a character FIFO.
6 *
7 * Later versions (at least 1.4, maybe earlier) of the MBX EPPC-Bug
8 * use COM1 instead of SMC1 as the console port. This kinda sucks
9 * for the rest of the kernel, so here we force the use of SMC1 again.
10 */
11#include <linux/types.h>
12#include <asm/uaccess.h>
13#include <asm/mpc8xx.h>
14#include <asm/cpm1.h>
15
16#ifdef CONFIG_MBX
17#define MBX_CSR1 ((volatile u_char *)0xfa100000)
18#define CSR1_COMEN (u_char)0x02
19#endif
20
21#ifdef TQM_SMC2_CONSOLE
22#define PROFF_CONS PROFF_SMC2
23#define CPM_CR_CH_CONS CPM_CR_CH_SMC2
24#define SMC_INDEX 1
25static volatile iop8xx_t *iopp = (iop8xx_t *)&(((immap_t *)IMAP_ADDR)->im_ioport);
26#else
27#define PROFF_CONS PROFF_SMC1
28#define CPM_CR_CH_CONS CPM_CR_CH_SMC1
29#define SMC_INDEX 0
30#endif
31
32static cpm8xx_t *cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
33
34unsigned long
35serial_init(int ignored, bd_t *bd)
36{
37 volatile smc_t *sp;
38 volatile smc_uart_t *up;
39 volatile cbd_t *tbdf, *rbdf;
40 volatile cpm8xx_t *cp;
41 uint dpaddr, memaddr;
42#ifndef CONFIG_MBX
43 uint ui;
44#endif
45
46 cp = cpmp;
47 sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]);
48 up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS];
49
50 /* Disable transmitter/receiver.
51 */
52 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
53
54#ifdef CONFIG_FADS
55 /* Enable SMC1/2 transceivers.
56 */
57 *((volatile uint *)BCSR1) &= ~(BCSR1_RS232EN_1|BCSR1_RS232EN_2);
58#endif
59
60#ifndef CONFIG_MBX
61 {
62 /* Initialize SMCx and use it for the console port.
63 */
64
65 /* Enable SDMA.
66 */
67 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1;
68
69#ifdef TQM_SMC2_CONSOLE
70 /* Use Port A for SMC2 instead of other functions.
71 */
72 iopp->iop_papar |= 0x00c0;
73 iopp->iop_padir &= ~0x00c0;
74 iopp->iop_paodr &= ~0x00c0;
75#else
76 /* Use Port B for SMCs instead of other functions.
77 */
78 cp->cp_pbpar |= 0x00000cc0;
79 cp->cp_pbdir &= ~0x00000cc0;
80 cp->cp_pbodr &= ~0x00000cc0;
81#endif
82
83 /* Allocate space for two buffer descriptors in the DP ram.
84 * For now, this address seems OK, but it may have to
85 * change with newer versions of the firmware.
86 */
87 dpaddr = 0x0800;
88
89 /* Grab a few bytes from the top of memory for SMC FIFOs.
90 */
91 memaddr = (bd->bi_memsize - 32) & ~15;
92
93 /* Set the physical address of the host memory buffers in
94 * the buffer descriptors.
95 */
96 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
97 rbdf->cbd_bufaddr = memaddr;
98 rbdf->cbd_sc = 0;
99 tbdf = rbdf + 1;
100 tbdf->cbd_bufaddr = memaddr+4;
101 tbdf->cbd_sc = 0;
102
103 /* Set up the uart parameters in the parameter ram.
104 */
105 up->smc_rbase = dpaddr;
106 up->smc_tbase = dpaddr+sizeof(cbd_t);
107 up->smc_rfcr = SMC_EB;
108 up->smc_tfcr = SMC_EB;
109
110 /* Set UART mode, 8 bit, no parity, one stop.
111 * Enable receive and transmit.
112 */
113 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
114
115 /* Mask all interrupts and remove anything pending.
116 */
117 sp->smc_smcm = 0;
118 sp->smc_smce = 0xff;
119
120 /* Set up the baud rate generator.
121 * See 8xx_io/commproc.c for details.
122 * This wires BRG1 to SMC1 and BRG2 to SMC2;
123 */
124 cp->cp_simode = 0x10000000;
125 ui = bd->bi_intfreq / 16 / bd->bi_baudrate;
126#ifdef TQM_SMC2_CONSOLE
127 cp->cp_brgc2 =
128#else
129 cp->cp_brgc1 =
130#endif
131 ((ui - 1) < 4096)
132 ? (((ui - 1) << 1) | CPM_BRG_EN)
133 : ((((ui / 16) - 1) << 1) | CPM_BRG_EN | CPM_BRG_DIV16);
134
135#else /* CONFIG_MBX */
136 if (*MBX_CSR1 & CSR1_COMEN) {
137 /* COM1 is enabled. Initialize SMC1 and use it for
138 * the console port.
139 */
140
141 /* Enable SDMA.
142 */
143 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1;
144
145 /* Use Port B for SMCs instead of other functions.
146 */
147 cp->cp_pbpar |= 0x00000cc0;
148 cp->cp_pbdir &= ~0x00000cc0;
149 cp->cp_pbodr &= ~0x00000cc0;
150
151 /* Allocate space for two buffer descriptors in the DP ram.
152 * For now, this address seems OK, but it may have to
153 * change with newer versions of the firmware.
154 */
155 dpaddr = 0x0800;
156
157 /* Grab a few bytes from the top of memory. EPPC-Bug isn't
158 * running any more, so we can do this.
159 */
160 memaddr = (bd->bi_memsize - 32) & ~15;
161
162 /* Set the physical address of the host memory buffers in
163 * the buffer descriptors.
164 */
165 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
166 rbdf->cbd_bufaddr = memaddr;
167 rbdf->cbd_sc = 0;
168 tbdf = rbdf + 1;
169 tbdf->cbd_bufaddr = memaddr+4;
170 tbdf->cbd_sc = 0;
171
172 /* Set up the uart parameters in the parameter ram.
173 */
174 up->smc_rbase = dpaddr;
175 up->smc_tbase = dpaddr+sizeof(cbd_t);
176 up->smc_rfcr = SMC_EB;
177 up->smc_tfcr = SMC_EB;
178
179 /* Set UART mode, 8 bit, no parity, one stop.
180 * Enable receive and transmit.
181 */
182 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
183
184 /* Mask all interrupts and remove anything pending.
185 */
186 sp->smc_smcm = 0;
187 sp->smc_smce = 0xff;
188
189 /* Set up the baud rate generator.
190 * See 8xx_io/commproc.c for details.
191 */
192 cp->cp_simode = 0x10000000;
193 cp->cp_brgc1 =
194 (((bd->bi_intfreq/16) / 9600) << 1) | CPM_BRG_EN;
195
196 /* Enable SMC1 for console output.
197 */
198 *MBX_CSR1 &= ~CSR1_COMEN;
199 }
200 else {
201#endif /* ndef CONFIG_MBX */
202 /* SMCx is used as console port.
203 */
204 tbdf = (cbd_t *)&cp->cp_dpmem[up->smc_tbase];
205 rbdf = (cbd_t *)&cp->cp_dpmem[up->smc_rbase];
206
207 /* Issue a stop transmit, and wait for it.
208 */
209 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS,
210 CPM_CR_STOP_TX) | CPM_CR_FLG;
211 while (cp->cp_cpcr & CPM_CR_FLG);
212 }
213
214 /* Make the first buffer the only buffer.
215 */
216 tbdf->cbd_sc |= BD_SC_WRAP;
217 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
218
219 /* Single character receive.
220 */
221 up->smc_mrblr = 1;
222 up->smc_maxidl = 0;
223
224 /* Initialize Tx/Rx parameters.
225 */
226 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, CPM_CR_INIT_TRX) | CPM_CR_FLG;
227 while (cp->cp_cpcr & CPM_CR_FLG);
228
229 /* Enable transmitter/receiver.
230 */
231 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
232
233 /* This is ignored.
234 */
235 return 0;
236}
237
238void
239serial_putc(void *ignored, const char c)
240{
241 volatile cbd_t *tbdf;
242 volatile char *buf;
243 volatile smc_uart_t *up;
244
245 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS];
246 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
247
248 /* Wait for last character to go.
249 */
250 buf = (char *)tbdf->cbd_bufaddr;
251 while (tbdf->cbd_sc & BD_SC_READY);
252
253 *buf = c;
254 tbdf->cbd_datlen = 1;
255 tbdf->cbd_sc |= BD_SC_READY;
256}
257
258char
259serial_getc(void *ignored)
260{
261 volatile cbd_t *rbdf;
262 volatile char *buf;
263 volatile smc_uart_t *up;
264 char c;
265
266 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS];
267 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
268
269 /* Wait for character to show up.
270 */
271 buf = (char *)rbdf->cbd_bufaddr;
272 while (rbdf->cbd_sc & BD_SC_EMPTY);
273 c = *buf;
274 rbdf->cbd_sc |= BD_SC_EMPTY;
275
276 return(c);
277}
278
279int
280serial_tstc(void *ignored)
281{
282 volatile cbd_t *rbdf;
283 volatile smc_uart_t *up;
284
285 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS];
286 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
287
288 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
289}
diff --git a/arch/ppc/boot/simple/misc-chestnut.c b/arch/ppc/boot/simple/misc-chestnut.c
deleted file mode 100644
index 14a4b56d4f84..000000000000
--- a/arch/ppc/boot/simple/misc-chestnut.c
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Setup for the IBM Chestnut (ibm-750fxgx_eval)
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/types.h>
13#include <asm/io.h>
14#include <asm/mv64x60_defs.h>
15#include <platforms/chestnut.h>
16
17/* Not in the kernel so won't include kernel.h to get its 'max' definition */
18#define max(a,b) (((a) > (b)) ? (a) : (b))
19
20void
21mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
22{
23#ifdef CONFIG_SERIAL_8250_CONSOLE
24 /*
25 * Change device bus 2 window so that bootoader can do I/O thru
26 * 8250/16550 UART that's mapped in that window.
27 */
28 out_le32(new_base + MV64x60_CPU2DEV_2_BASE, CHESTNUT_UART_BASE >> 16);
29 out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, CHESTNUT_UART_SIZE >> 16);
30 __asm__ __volatile__("sync");
31#endif
32}
diff --git a/arch/ppc/boot/simple/misc-cpci690.c b/arch/ppc/boot/simple/misc-cpci690.c
deleted file mode 100644
index 8a8614d11a32..000000000000
--- a/arch/ppc/boot/simple/misc-cpci690.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * Add birec data for Force CPCI690 board.
3 *
4 * Author: Mark A. Greer <source@mvista.com>
5 *
6 * 2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/types.h>
13#include <asm/io.h>
14#include <platforms/cpci690.h>
15
16#define KB (1024UL)
17#define MB (1024UL*KB)
18#define GB (1024UL*MB)
19
20extern u32 mv64x60_console_baud;
21extern u32 mv64x60_mpsc_clk_src;
22extern u32 mv64x60_mpsc_clk_freq;
23
24u32 mag = 0xffff;
25
26unsigned long
27get_mem_size(void)
28{
29 u32 size;
30
31 switch (in_8(((void __iomem *)CPCI690_BR_BASE + CPCI690_BR_MEM_CTLR))
32 & 0x07) {
33 case 0x01:
34 size = 256*MB;
35 break;
36 case 0x02:
37 size = 512*MB;
38 break;
39 case 0x03:
40 size = 768*MB;
41 break;
42 case 0x04:
43 size = 1*GB;
44 break;
45 case 0x05:
46 size = 1*GB + 512*MB;
47 break;
48 case 0x06:
49 size = 2*GB;
50 break;
51 default:
52 size = 0;
53 }
54
55 return size;
56}
57
58void
59mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
60{
61 mv64x60_console_baud = CPCI690_MPSC_BAUD;
62 mv64x60_mpsc_clk_src = CPCI690_MPSC_CLK_SRC;
63 mv64x60_mpsc_clk_freq =
64 (get_mem_size() >= (1*GB)) ? 100000000 : 133333333;
65}
diff --git a/arch/ppc/boot/simple/misc-embedded.c b/arch/ppc/boot/simple/misc-embedded.c
deleted file mode 100644
index d5a00eb0e4eb..000000000000
--- a/arch/ppc/boot/simple/misc-embedded.c
+++ /dev/null
@@ -1,276 +0,0 @@
1/*
2 * Originally adapted by Gary Thomas. Much additional work by
3 * Cort Dougan <cort@fsmlabs.com>. On top of that still more work by
4 * Dan Malek <dmalek@jlc.net>.
5 *
6 * Currently maintained by: Tom Rini <trini@kernel.crashing.org>
7 */
8
9#include <linux/types.h>
10#include <linux/string.h>
11#include <asm/bootinfo.h>
12#include <asm/mmu.h>
13#include <asm/page.h>
14#include <asm/residual.h>
15#if defined(CONFIG_4xx)
16#include <asm/ibm4xx.h>
17#elif defined(CONFIG_8xx)
18#include <asm/mpc8xx.h>
19#elif defined(CONFIG_8260)
20#include <asm/mpc8260.h>
21#endif
22
23#include "nonstdio.h"
24
25/* The linker tells us where the image is. */
26extern char __image_begin, __image_end;
27extern char __ramdisk_begin, __ramdisk_end;
28extern char _end[];
29
30/* Because of the limited amount of memory on embedded, it presents
31 * loading problems. The biggest is that we load this boot program
32 * into a relatively low memory address, and the Linux kernel Bss often
33 * extends into this space when it get loaded. When the kernel starts
34 * and zeros the BSS space, it also writes over the information we
35 * save here and pass to the kernel (usually board info).
36 * On these boards, we grab some known memory holes to hold this information.
37 */
38char cmd_buf[256];
39char *cmd_line = cmd_buf;
40char *avail_ram;
41char *end_avail;
42char *zimage_start;
43
44/* This is for 4xx treeboot. It provides a place for the bootrom
45 * give us a pointer to a rom environment command line.
46 */
47char *bootrom_cmdline = "";
48
49/* This is the default cmdline that will be given to the user at boot time..
50 * If none was specified at compile time, we'll give it one that should work.
51 * -- Tom */
52#ifdef CONFIG_CMDLINE_BOOL
53char compiled_string[] = CONFIG_CMDLINE;
54#endif
55char ramroot_string[] = "root=/dev/ram";
56char netroot_string[] = "root=/dev/nfs rw ip=on";
57
58/* Serial port to use. */
59unsigned long com_port;
60
61/* We need to make sure that this is before the images to ensure
62 * that it's in a mapped location. - Tom */
63bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
64bd_t *hold_residual = &hold_resid_buf;
65
66extern unsigned long serial_init(int chan, bd_t *bp);
67extern void serial_close(unsigned long com_port);
68extern unsigned long start;
69extern void flush_instruction_cache(void);
70extern void gunzip(void *, int, unsigned char *, int *);
71extern void embed_config(bd_t **bp);
72
73/* Weak function for boards which don't need to build the
74 * board info struct because they are using PPCBoot/U-Boot.
75 */
76void __attribute__ ((weak))
77embed_config(bd_t **bdp)
78{
79}
80
81unsigned long
82load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, bd_t *bp)
83{
84 char *cp, ch;
85 int timer = 0, zimage_size;
86 unsigned long initrd_size;
87
88 /* First, capture the embedded board information. Then
89 * initialize the serial console port.
90 */
91 embed_config(&bp);
92#if defined(CONFIG_SERIAL_CPM_CONSOLE) || \
93 defined(CONFIG_SERIAL_8250_CONSOLE) || \
94 defined(CONFIG_SERIAL_UARTLITE_CONSOLE)
95 com_port = serial_init(0, bp);
96#endif
97
98 /* Grab some space for the command line and board info. Since
99 * we no longer use the ELF header, but it was loaded, grab
100 * that space.
101 */
102#ifdef CONFIG_MBX
103 /* Because of the way the MBX loads the ELF image, we can't
104 * tell where we started. We read a magic variable from the NVRAM
105 * that gives us the intermediate buffer load address.
106 */
107 load_addr = *(uint *)0xfa000020;
108 load_addr += 0x10000; /* Skip ELF header */
109#endif
110 /* copy board data */
111 if (bp)
112 memcpy(hold_residual,bp,sizeof(bd_t));
113
114 /* Set end of memory available to us. It is always the highest
115 * memory address provided by the board information.
116 */
117 end_avail = (char *)(bp->bi_memsize);
118
119 puts("\nloaded at: "); puthex(load_addr);
120 puts(" "); puthex((unsigned long)(load_addr + (4*num_words))); puts("\n");
121 if ( (unsigned long)load_addr != (unsigned long)&start ) {
122 puts("relocated to: "); puthex((unsigned long)&start);
123 puts(" ");
124 puthex((unsigned long)((unsigned long)&start + (4*num_words)));
125 puts("\n");
126 }
127
128 if ( bp ) {
129 puts("board data at: "); puthex((unsigned long)bp);
130 puts(" ");
131 puthex((unsigned long)((unsigned long)bp + sizeof(bd_t)));
132 puts("\nrelocated to: ");
133 puthex((unsigned long)hold_residual);
134 puts(" ");
135 puthex((unsigned long)((unsigned long)hold_residual + sizeof(bd_t)));
136 puts("\n");
137 }
138
139 /*
140 * We link ourself to an arbitrary low address. When we run, we
141 * relocate ourself to that address. __image_being points to
142 * the part of the image where the zImage is. -- Tom
143 */
144 zimage_start = (char *)(unsigned long)(&__image_begin);
145 zimage_size = (unsigned long)(&__image_end) -
146 (unsigned long)(&__image_begin);
147
148 initrd_size = (unsigned long)(&__ramdisk_end) -
149 (unsigned long)(&__ramdisk_begin);
150
151 /*
152 * The zImage and initrd will be between start and _end, so they've
153 * already been moved once. We're good to go now. -- Tom
154 */
155 puts("zimage at: "); puthex((unsigned long)zimage_start);
156 puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
157 puts("\n");
158
159 if ( initrd_size ) {
160 puts("initrd at: ");
161 puthex((unsigned long)(&__ramdisk_begin));
162 puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
163 }
164
165 /*
166 * setup avail_ram - this is the first part of ram usable
167 * by the uncompress code. Anything after this program in RAM
168 * is now fair game. -- Tom
169 */
170 avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
171
172 puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
173 puthex((unsigned long)end_avail); puts("\n");
174 puts("\nLinux/PPC load: ");
175 cp = cmd_line;
176 /* This is where we try and pick the right command line for booting.
177 * If we were given one at compile time, use it. It Is Right.
178 * If we weren't, see if we have a ramdisk. If so, thats root.
179 * When in doubt, give them the netroot (root=/dev/nfs rw) -- Tom
180 */
181#ifdef CONFIG_CMDLINE_BOOL
182 memcpy (cmd_line, compiled_string, sizeof(compiled_string));
183#else
184 if ( initrd_size )
185 memcpy (cmd_line, ramroot_string, sizeof(ramroot_string));
186 else
187 memcpy (cmd_line, netroot_string, sizeof(netroot_string));
188#endif
189 while ( *cp )
190 putc(*cp++);
191 while (timer++ < 5*1000) {
192 if (tstc()) {
193 while ((ch = getc()) != '\n' && ch != '\r') {
194 if (ch == '\b' || ch == '\177') {
195 if (cp != cmd_line) {
196 cp--;
197 puts("\b \b");
198 }
199 } else if (ch == '\030' /* ^x */
200 || ch == '\025') { /* ^u */
201 while (cp != cmd_line) {
202 cp--;
203 puts("\b \b");
204 }
205 } else {
206 *cp++ = ch;
207 putc(ch);
208 }
209 }
210 break; /* Exit 'timer' loop */
211 }
212 udelay(1000); /* 1 msec */
213 }
214 *cp = 0;
215 puts("\nUncompressing Linux...");
216
217 gunzip(0, 0x400000, zimage_start, &zimage_size);
218 flush_instruction_cache();
219 puts("done.\n");
220 {
221 struct bi_record *rec;
222 unsigned long initrd_loc = 0;
223 unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) +
224 (1 << 20) - 1, (1 << 20));
225 rec = (struct bi_record *)rec_loc;
226
227 /* We need to make sure that the initrd and bi_recs do not
228 * overlap. */
229 if ( initrd_size ) {
230 initrd_loc = (unsigned long)(&__ramdisk_begin);
231 /* If the bi_recs are in the middle of the current
232 * initrd, move the initrd to the next MB
233 * boundary. */
234 if ((rec_loc > initrd_loc) &&
235 ((initrd_loc + initrd_size)
236 > rec_loc)) {
237 initrd_loc = _ALIGN((unsigned long)(zimage_size)
238 + (2 << 20) - 1, (2 << 20));
239 memmove((void *)initrd_loc, &__ramdisk_begin,
240 initrd_size);
241 puts("initrd moved: "); puthex(initrd_loc);
242 puts(" "); puthex(initrd_loc + initrd_size);
243 puts("\n");
244 }
245 }
246
247 rec->tag = BI_FIRST;
248 rec->size = sizeof(struct bi_record);
249 rec = (struct bi_record *)((unsigned long)rec + rec->size);
250
251 rec->tag = BI_CMD_LINE;
252 memcpy( (char *)rec->data, cmd_line, strlen(cmd_line)+1);
253 rec->size = sizeof(struct bi_record) + strlen(cmd_line) + 1;
254 rec = (struct bi_record *)((unsigned long)rec + rec->size);
255
256 if ( initrd_size ) {
257 rec->tag = BI_INITRD;
258 rec->data[0] = initrd_loc;
259 rec->data[1] = initrd_size;
260 rec->size = sizeof(struct bi_record) + 2 *
261 sizeof(unsigned long);
262 rec = (struct bi_record *)((unsigned long)rec +
263 rec->size);
264 }
265
266 rec->tag = BI_LAST;
267 rec->size = sizeof(struct bi_record);
268 rec = (struct bi_record *)((unsigned long)rec + rec->size);
269 }
270 puts("Now booting the kernel\n");
271#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE)
272 serial_close(com_port);
273#endif
274
275 return (unsigned long)hold_residual;
276}
diff --git a/arch/ppc/boot/simple/misc-ev64260.c b/arch/ppc/boot/simple/misc-ev64260.c
deleted file mode 100644
index 0b3978632aca..000000000000
--- a/arch/ppc/boot/simple/misc-ev64260.c
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Host bridge init code for the Marvell/Galileo EV-64260-BP evaluation board
3 * with a GT64260 onboard.
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2001 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/types.h>
14#include <asm/reg.h>
15#include <asm/io.h>
16#include <asm/mv64x60_defs.h>
17#include <platforms/ev64260.h>
18
19#ifdef CONFIG_SERIAL_MPSC_CONSOLE
20extern u32 mv64x60_console_baud;
21extern u32 mv64x60_mpsc_clk_src;
22extern u32 mv64x60_mpsc_clk_freq;
23#endif
24
25void
26mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
27{
28 u32 p, v;
29
30 /* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */
31 p = mfspr(SPRN_PVR);
32 p >>= 16;
33
34 /* Reasonable SWAG at a 745x PVR value */
35 if (((p & 0xfff0) == 0x8000) && (p != 0x800c)) {
36 v = mfspr(SPRN_HID0);
37 v |= HID0_TBEN;
38 mtspr(SPRN_HID0, v);
39 }
40
41#ifdef CONFIG_SERIAL_8250_CONSOLE
42 /*
43 * Change device bus 2 window so that bootoader can do I/O thru
44 * 8250/16550 UART that's mapped in that window.
45 */
46 out_le32(new_base + MV64x60_CPU2DEV_2_BASE, EV64260_UART_BASE >> 20);
47 out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, EV64260_UART_END >> 20);
48 __asm__ __volatile__("sync");
49#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
50 mv64x60_console_baud = EV64260_DEFAULT_BAUD;
51 mv64x60_mpsc_clk_src = EV64260_MPSC_CLK_SRC;
52 mv64x60_mpsc_clk_freq = EV64260_MPSC_CLK_FREQ;
53#endif
54}
diff --git a/arch/ppc/boot/simple/misc-ev64360.c b/arch/ppc/boot/simple/misc-ev64360.c
deleted file mode 100644
index 96eaebb78df5..000000000000
--- a/arch/ppc/boot/simple/misc-ev64360.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (C) 2005 Lee Nicks <allinux@gmail.com>
3 *
4 * Based on arch/ppc/boot/simple/misc-katana.c from:
5 * Mark A. Greer <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include <linux/types.h>
23#include <asm/io.h>
24#include <asm/mv64x60_defs.h>
25#include <platforms/ev64360.h>
26
27extern u32 mv64x60_console_baud;
28extern u32 mv64x60_mpsc_clk_src;
29extern u32 mv64x60_mpsc_clk_freq;
30
31/* Not in the kernel so won't include kernel.h to get its 'min' definition */
32#ifndef min
33#define min(a,b) (((a) < (b)) ? (a) : (b))
34#endif
35
36void
37mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
38{
39 mv64x60_console_baud = EV64360_DEFAULT_BAUD;
40 mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC;
41 mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ;
42}
diff --git a/arch/ppc/boot/simple/misc-katana.c b/arch/ppc/boot/simple/misc-katana.c
deleted file mode 100644
index 79a1bbcbc6c5..000000000000
--- a/arch/ppc/boot/simple/misc-katana.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Set up MPSC values to bootwrapper can prompt user.
3 *
4 * Author: Mark A. Greer <source@mvista.com>
5 *
6 * 2004 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/types.h>
13#include <asm/io.h>
14#include <asm/mv64x60_defs.h>
15#include <platforms/katana.h>
16
17extern u32 mv64x60_console_baud;
18extern u32 mv64x60_mpsc_clk_src;
19extern u32 mv64x60_mpsc_clk_freq;
20
21/* Not in the kernel so won't include kernel.h to get its 'min' definition */
22#ifndef min
23#define min(a,b) (((a) < (b)) ? (a) : (b))
24#endif
25
26unsigned long mv64360_get_mem_size(void);
27
28void
29mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
30{
31 mv64x60_console_baud = KATANA_DEFAULT_BAUD;
32 mv64x60_mpsc_clk_src = KATANA_MPSC_CLK_SRC;
33 mv64x60_mpsc_clk_freq =
34 min(katana_bus_freq((void __iomem *)KATANA_CPLD_BASE),
35 MV64x60_TCLK_FREQ_MAX);
36}
37
38unsigned long
39get_mem_size(void)
40{
41 return mv64360_get_mem_size();
42}
diff --git a/arch/ppc/boot/simple/misc-mv64x60.c b/arch/ppc/boot/simple/misc-mv64x60.c
deleted file mode 100644
index 28b3108083ed..000000000000
--- a/arch/ppc/boot/simple/misc-mv64x60.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Relocate bridge's register base and call board specific routine.
3 *
4 * Author: Mark A. Greer <source@mvista.com>
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/types.h>
13#include <asm/io.h>
14#include <asm/mv64x60_defs.h>
15
16extern struct bi_record *decompress_kernel(unsigned long load_addr,
17 int num_words, unsigned long cksum);
18
19
20u32 size_reg[MV64x60_CPU2MEM_WINDOWS] = {
21 MV64x60_CPU2MEM_0_SIZE, MV64x60_CPU2MEM_1_SIZE,
22 MV64x60_CPU2MEM_2_SIZE, MV64x60_CPU2MEM_3_SIZE
23};
24
25/* Read mem ctlr to get the amount of mem in system */
26unsigned long
27mv64360_get_mem_size(void)
28{
29 u32 enables, i, v;
30 u32 mem = 0;
31
32 enables = in_le32((void __iomem *)CONFIG_MV64X60_NEW_BASE +
33 MV64360_CPU_BAR_ENABLE) & 0xf;
34
35 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
36 if (!(enables & (1<<i))) {
37 v = in_le32((void __iomem *)CONFIG_MV64X60_NEW_BASE
38 + size_reg[i]) & 0xffff;
39 v = (v + 1) << 16;
40 mem += v;
41 }
42
43 return mem;
44}
45
46void
47mv64x60_move_base(void __iomem *old_base, void __iomem *new_base)
48{
49 u32 bits, mask, b;
50
51 if (old_base != new_base) {
52#ifdef CONFIG_GT64260
53 bits = 12;
54 mask = 0x07000000;
55#else /* Must be mv64[34]60 */
56 bits = 16;
57 mask = 0x03000000;
58#endif
59 b = in_le32(old_base + MV64x60_INTERNAL_SPACE_DECODE);
60 b &= mask;
61 b |= ((u32)new_base >> (32 - bits));
62 out_le32(old_base + MV64x60_INTERNAL_SPACE_DECODE, b);
63
64 __asm__ __volatile__("sync");
65
66 /* Wait for change to happen (in accordance with the manual) */
67 while (in_le32(new_base + MV64x60_INTERNAL_SPACE_DECODE) != b);
68 }
69}
70
71void __attribute__ ((weak))
72mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
73{
74}
75
76void *
77load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
78 void *ign1, void *ign2)
79{
80 mv64x60_move_base((void __iomem *)CONFIG_MV64X60_BASE,
81 (void __iomem *)CONFIG_MV64X60_NEW_BASE);
82 mv64x60_board_init((void __iomem *)CONFIG_MV64X60_BASE,
83 (void __iomem *)CONFIG_MV64X60_NEW_BASE);
84 return decompress_kernel(load_addr, num_words, cksum);
85}
diff --git a/arch/ppc/boot/simple/misc-prep.c b/arch/ppc/boot/simple/misc-prep.c
deleted file mode 100644
index 0086e1cfb48c..000000000000
--- a/arch/ppc/boot/simple/misc-prep.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Maintainer: Tom Rini <trini@kernel.crashing.org>
3 *
4 * In the past: Gary Thomas, Cort Dougan <cort@cs.nmt.edu>
5 */
6
7#include <linux/pci_ids.h>
8#include <linux/types.h>
9#include <asm/residual.h>
10#include <asm/string.h>
11#include <asm/byteorder.h>
12#include "mpc10x.h"
13#include "of1275.h"
14#include "nonstdio.h"
15
16extern int keyb_present; /* keyboard controller is present by default */
17RESIDUAL hold_resid_buf;
18RESIDUAL *hold_residual = &hold_resid_buf;
19static void *OFW_interface; /* Pointer to OF, if available. */
20
21#ifdef CONFIG_VGA_CONSOLE
22char *vidmem = (char *)0xC00B8000;
23int lines = 25, cols = 80;
24int orig_x, orig_y = 24;
25#endif /* CONFIG_VGA_CONSOLE */
26
27extern int CRT_tstc(void);
28extern int vga_init(unsigned char *ISA_mem);
29extern void gunzip(void *, int, unsigned char *, int *);
30extern unsigned long serial_init(int chan, void *ignored);
31extern void serial_fixups(void);
32extern struct bi_record *decompress_kernel(unsigned long load_addr,
33 int num_words, unsigned long cksum);
34extern void disable_6xx_mmu(void);
35extern unsigned long mpc10x_get_mem_size(void);
36
37static void
38writel(unsigned int val, unsigned int address)
39{
40 /* Ensure I/O operations complete */
41 __asm__ volatile("eieio");
42 *(unsigned int *)address = cpu_to_le32(val);
43}
44
45#define PCI_CFG_ADDR(dev,off) ((0x80<<24) | (dev<<8) | (off&0xfc))
46#define PCI_CFG_DATA(off) (MPC10X_MAPA_CNFG_DATA+(off&3))
47
48static void
49pci_read_config_32(unsigned char devfn,
50 unsigned char offset,
51 unsigned int *val)
52{
53 /* Ensure I/O operations complete */
54 __asm__ volatile("eieio");
55 *(unsigned int *)PCI_CFG_ADDR(devfn,offset) =
56 cpu_to_le32(MPC10X_MAPA_CNFG_ADDR);
57 /* Ensure I/O operations complete */
58 __asm__ volatile("eieio");
59 *val = le32_to_cpu(*(unsigned int *)PCI_CFG_DATA(offset));
60 return;
61}
62
63#ifdef CONFIG_VGA_CONSOLE
64void
65scroll(void)
66{
67 int i;
68
69 memcpy ( vidmem, vidmem + cols * 2, ( lines - 1 ) * cols * 2 );
70 for ( i = ( lines - 1 ) * cols * 2; i < lines * cols * 2; i += 2 )
71 vidmem[i] = ' ';
72}
73#endif /* CONFIG_VGA_CONSOLE */
74
75unsigned long
76load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
77 RESIDUAL *residual, void *OFW)
78{
79 int start_multi = 0;
80 unsigned int pci_viddid, pci_did, tulip_pci_base, tulip_base;
81
82 /* If we have Open Firmware, initialise it immediately */
83 if (OFW) {
84 OFW_interface = OFW;
85 ofinit(OFW_interface);
86 }
87
88 board_isa_init();
89#if defined(CONFIG_VGA_CONSOLE)
90 vga_init((unsigned char *)0xC0000000);
91#endif /* CONFIG_VGA_CONSOLE */
92
93 if (residual) {
94 /* Is this Motorola PPCBug? */
95 if ((1 & residual->VitalProductData.FirmwareSupports) &&
96 (1 == residual->VitalProductData.FirmwareSupplier)) {
97 unsigned char base_mod;
98 unsigned char board_type = inb(0x801) & 0xF0;
99
100 /*
101 * Reset the onboard 21x4x Ethernet
102 * Motorola Ethernet is at IDSEL 14 (devfn 0x70)
103 */
104 pci_read_config_32(0x70, 0x00, &pci_viddid);
105 pci_did = (pci_viddid & 0xffff0000) >> 16;
106 /* Be sure we've really found a 21x4x chip */
107 if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_DEC) &&
108 ((pci_did == PCI_DEVICE_ID_DEC_TULIP_FAST) ||
109 (pci_did == PCI_DEVICE_ID_DEC_TULIP) ||
110 (pci_did == PCI_DEVICE_ID_DEC_TULIP_PLUS) ||
111 (pci_did == PCI_DEVICE_ID_DEC_21142))) {
112 pci_read_config_32(0x70,
113 0x10,
114 &tulip_pci_base);
115 /* Get the physical base address */
116 tulip_base =
117 (tulip_pci_base & ~0x03UL) + 0x80000000;
118 /* Strobe the 21x4x reset bit in CSR0 */
119 writel(0x1, tulip_base);
120 }
121
122 /* If this is genesis 2 board then check for no
123 * keyboard controller and more than one processor.
124 */
125 if (board_type == 0xe0) {
126 base_mod = inb(0x803);
127 /* if a MVME2300/2400 or a Sitka then no keyboard */
128 if((base_mod == 0xFA) || (base_mod == 0xF9) ||
129 (base_mod == 0xE1)) {
130 keyb_present = 0; /* no keyboard */
131 }
132 }
133 /* If this is a multiprocessor system then
134 * park the other processor so that the
135 * kernel knows where to find them.
136 */
137 if (residual->MaxNumCpus > 1)
138 start_multi = 1;
139 }
140 memcpy(hold_residual,residual,sizeof(RESIDUAL));
141 }
142
143 /* Call decompress_kernel */
144 decompress_kernel(load_addr, num_words, cksum);
145
146 if (start_multi) {
147 residual->VitalProductData.SmpIar = (unsigned long)0xc0;
148 residual->Cpus[1].CpuState = CPU_GOOD;
149 hold_residual->VitalProductData.Reserved5 = 0xdeadbeef;
150 }
151
152 /* Now go and clear out the BATs and ensure that our MSR is
153 * correct .*/
154 disable_6xx_mmu();
155
156 /* Make r3 be a pointer to the residual data. */
157 return (unsigned long)hold_residual;
158}
159
160unsigned long
161get_mem_size(void)
162{
163 unsigned int pci_viddid, pci_did;
164
165 /* First, figure out what kind of host bridge we are on. If it's
166 * an MPC10x, we can ask it directly how much memory it has.
167 * Otherwise, see if the residual data has anything. This isn't
168 * the best way, but it can be the only way. If there's nothing,
169 * assume 32MB. -- Tom.
170 */
171 /* See what our host bridge is. */
172 pci_read_config_32(0x00, 0x00, &pci_viddid);
173 pci_did = (pci_viddid & 0xffff0000) >> 16;
174 /* See if we are on an MPC10x. */
175 if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA)
176 && ((pci_did == PCI_DEVICE_ID_MOTOROLA_MPC105)
177 || (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC106)
178 || (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC107)))
179 return mpc10x_get_mem_size();
180 /* If it's not, see if we have anything in the residual data. */
181 else if (hold_residual && hold_residual->TotalMemory)
182 return hold_residual->TotalMemory;
183 else if (OFW_interface) {
184 /*
185 * This is a 'best guess' check. We want to make sure
186 * we don't try this on a PReP box without OF
187 * -- Cort
188 */
189 while (OFW_interface)
190 {
191 phandle dev_handle;
192 int mem_info[2];
193
194 /* get handle to memory description */
195 if (!(dev_handle = finddevice("/memory@0")))
196 break;
197
198 /* get the info */
199 if (getprop(dev_handle, "reg", mem_info,
200 sizeof(mem_info)) != 8)
201 break;
202
203 return mem_info[1];
204 }
205 }
206
207 /* Fall back to hard-coding 32MB. */
208 return 32*1024*1024;
209}
diff --git a/arch/ppc/boot/simple/misc-radstone_ppc7d.c b/arch/ppc/boot/simple/misc-radstone_ppc7d.c
deleted file mode 100644
index 0f302ea9c3d1..000000000000
--- a/arch/ppc/boot/simple/misc-radstone_ppc7d.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Misc data for Radstone PPC7D board.
3 *
4 * Author: James Chapman <jchapman@katalix.com>
5 */
6
7#include <linux/types.h>
8#include <platforms/radstone_ppc7d.h>
9
10#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
11extern u32 mv64x60_console_baud;
12extern u32 mv64x60_mpsc_clk_src;
13extern u32 mv64x60_mpsc_clk_freq;
14#endif
15
16void
17mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
18{
19#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
20 mv64x60_console_baud = PPC7D_DEFAULT_BAUD;
21 mv64x60_mpsc_clk_src = PPC7D_MPSC_CLK_SRC;
22 mv64x60_mpsc_clk_freq = PPC7D_MPSC_CLK_FREQ;
23#endif
24}
diff --git a/arch/ppc/boot/simple/misc-spruce.c b/arch/ppc/boot/simple/misc-spruce.c
deleted file mode 100644
index 5b3a6c6f113b..000000000000
--- a/arch/ppc/boot/simple/misc-spruce.c
+++ /dev/null
@@ -1,271 +0,0 @@
1/*
2 * Misc. bootloader code for IBM Spruce reference platform
3 *
4 * Authors: Johnnie Peters <jpeters@mvista.com>
5 * Matt Porter <mporter@mvista.com>
6 *
7 * Derived from arch/ppc/boot/prep/misc.c
8 *
9 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#include <linux/types.h>
16#include <linux/pci.h>
17
18#include <asm/bootinfo.h>
19
20extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
21 unsigned long cksum);
22
23/* Define some important locations of the Spruce. */
24#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
25#define SPRUCE_PCI_CONFIG_DATA 0xfec00004
26
27/* PCI configuration space access routines. */
28unsigned int *pci_config_address = (unsigned int *)SPRUCE_PCI_CONFIG_ADDR;
29unsigned char *pci_config_data = (unsigned char *)SPRUCE_PCI_CONFIG_DATA;
30
31void cpc700_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
32 unsigned char offset, unsigned char *val)
33{
34 out_le32(pci_config_address,
35 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
36
37 *val= (in_le32((unsigned *)pci_config_data) >> (8 * (offset & 3))) & 0xff;
38}
39
40void cpc700_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
41 unsigned char offset, unsigned char val)
42{
43 out_le32(pci_config_address,
44 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
45
46 out_8(pci_config_data + (offset&3), val);
47}
48
49void cpc700_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
50 unsigned char offset, unsigned short *val)
51{
52 out_le32(pci_config_address,
53 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
54
55 *val= in_le16((unsigned short *)(pci_config_data + (offset&3)));
56}
57
58void cpc700_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
59 unsigned char offset, unsigned short val)
60{
61 out_le32(pci_config_address,
62 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
63
64 out_le16((unsigned short *)(pci_config_data + (offset&3)), val);
65}
66
67void cpc700_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
68 unsigned char offset, unsigned int *val)
69{
70 out_le32(pci_config_address,
71 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
72
73 *val= in_le32((unsigned *)pci_config_data);
74}
75
76void cpc700_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
77 unsigned char offset, unsigned int val)
78{
79 out_le32(pci_config_address,
80 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
81
82 out_le32((unsigned *)pci_config_data, val);
83}
84
85#define PCNET32_WIO_RDP 0x10
86#define PCNET32_WIO_RAP 0x12
87#define PCNET32_WIO_RESET 0x14
88
89#define PCNET32_DWIO_RDP 0x10
90#define PCNET32_DWIO_RAP 0x14
91#define PCNET32_DWIO_RESET 0x18
92
93/* Processor interface config register access */
94#define PIFCFGADDR 0xff500000
95#define PIFCFGDATA 0xff500004
96
97#define PLBMIFOPT 0x18 /* PLB Master Interface Options */
98
99#define MEM_MBEN 0x24
100#define MEM_TYPE 0x28
101#define MEM_B1SA 0x3c
102#define MEM_B1EA 0x5c
103#define MEM_B2SA 0x40
104#define MEM_B2EA 0x60
105
106unsigned long
107get_mem_size(void)
108{
109 int loop;
110 unsigned long mem_size = 0;
111 unsigned long mem_mben;
112 unsigned long mem_type;
113 unsigned long mem_start;
114 unsigned long mem_end;
115 volatile int *mem_addr = (int *)0xff500008;
116 volatile int *mem_data = (int *)0xff50000c;
117
118 /* Get the size of memory from the memory controller. */
119 *mem_addr = MEM_MBEN;
120 asm("sync");
121 mem_mben = *mem_data;
122 asm("sync");
123 for(loop = 0; loop < 1000; loop++);
124
125 *mem_addr = MEM_TYPE;
126 asm("sync");
127 mem_type = *mem_data;
128 asm("sync");
129 for(loop = 0; loop < 1000; loop++);
130
131 *mem_addr = MEM_TYPE;
132 /* Confirm bank 1 has DRAM memory */
133 if ((mem_mben & 0x40000000) &&
134 ((mem_type & 0x30000000) == 0x10000000)) {
135 *mem_addr = MEM_B1SA;
136 asm("sync");
137 mem_start = *mem_data;
138 asm("sync");
139 for(loop = 0; loop < 1000; loop++);
140
141 *mem_addr = MEM_B1EA;
142 asm("sync");
143 mem_end = *mem_data;
144 asm("sync");
145 for(loop = 0; loop < 1000; loop++);
146
147 mem_size = mem_end - mem_start + 0x100000;
148 }
149
150 /* Confirm bank 2 has DRAM memory */
151 if ((mem_mben & 0x20000000) &&
152 ((mem_type & 0xc000000) == 0x4000000)) {
153 *mem_addr = MEM_B2SA;
154 asm("sync");
155 mem_start = *mem_data;
156 asm("sync");
157 for(loop = 0; loop < 1000; loop++);
158
159 *mem_addr = MEM_B2EA;
160 asm("sync");
161 mem_end = *mem_data;
162 asm("sync");
163 for(loop = 0; loop < 1000; loop++);
164
165 mem_size += mem_end - mem_start + 0x100000;
166 }
167 return mem_size;
168}
169
170unsigned long
171load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
172 void *ign1, void *ign2)
173{
174 int csr0;
175 int csr_id;
176 int pci_devfn;
177 int found_multi = 0;
178 unsigned short vendor;
179 unsigned short device;
180 unsigned short command;
181 unsigned char header_type;
182 unsigned int bar0;
183 volatile int *pif_addr = (int *)0xff500000;
184 volatile int *pif_data = (int *)0xff500004;
185
186 /*
187 * Gah, these firmware guys need to learn that hardware
188 * byte swapping is evil! Disable all hardware byte
189 * swapping so it doesn't hurt anyone.
190 */
191 *pif_addr = PLBMIFOPT;
192 asm("sync");
193 *pif_data = 0x00000000;
194 asm("sync");
195
196 /* Search out and turn off the PcNet ethernet boot device. */
197 for (pci_devfn = 1; pci_devfn < 0xff; pci_devfn++) {
198 if (PCI_FUNC(pci_devfn) && !found_multi)
199 continue;
200
201 cpc700_pcibios_read_config_byte(0, pci_devfn,
202 PCI_HEADER_TYPE, &header_type);
203
204 if (!PCI_FUNC(pci_devfn))
205 found_multi = header_type & 0x80;
206
207 cpc700_pcibios_read_config_word(0, pci_devfn, PCI_VENDOR_ID,
208 &vendor);
209
210 if (vendor != 0xffff) {
211 cpc700_pcibios_read_config_word(0, pci_devfn,
212 PCI_DEVICE_ID, &device);
213
214 /* If this PCI device is the Lance PCNet board then turn it off */
215 if ((vendor == PCI_VENDOR_ID_AMD) &&
216 (device == PCI_DEVICE_ID_AMD_LANCE)) {
217
218 /* Turn on I/O Space on the board. */
219 cpc700_pcibios_read_config_word(0, pci_devfn,
220 PCI_COMMAND, &command);
221 command |= 0x1;
222 cpc700_pcibios_write_config_word(0, pci_devfn,
223 PCI_COMMAND, command);
224
225 /* Get the I/O space address */
226 cpc700_pcibios_read_config_dword(0, pci_devfn,
227 PCI_BASE_ADDRESS_0, &bar0);
228 bar0 &= 0xfffffffe;
229
230 /* Reset the PCNet Board */
231 inl (bar0+PCNET32_DWIO_RESET);
232 inw (bar0+PCNET32_WIO_RESET);
233
234 /* First do a work oriented read of csr0. If the value is
235 * 4 then this is the correct mode to access the board.
236 * If not try a double word ortiented read.
237 */
238 outw(0, bar0 + PCNET32_WIO_RAP);
239 csr0 = inw(bar0 + PCNET32_WIO_RDP);
240
241 if (csr0 == 4) {
242 /* Check the Chip id register */
243 outw(88, bar0 + PCNET32_WIO_RAP);
244 csr_id = inw(bar0 + PCNET32_WIO_RDP);
245
246 if (csr_id) {
247 /* This is the valid mode - set the stop bit */
248 outw(0, bar0 + PCNET32_WIO_RAP);
249 outw(csr0, bar0 + PCNET32_WIO_RDP);
250 }
251 } else {
252 outl(0, bar0 + PCNET32_DWIO_RAP);
253 csr0 = inl(bar0 + PCNET32_DWIO_RDP);
254 if (csr0 == 4) {
255 /* Check the Chip id register */
256 outl(88, bar0 + PCNET32_WIO_RAP);
257 csr_id = inl(bar0 + PCNET32_WIO_RDP);
258
259 if (csr_id) {
260 /* This is the valid mode - set the stop bit*/
261 outl(0, bar0 + PCNET32_WIO_RAP);
262 outl(csr0, bar0 + PCNET32_WIO_RDP);
263 }
264 }
265 }
266 }
267 }
268 }
269
270 return decompress_kernel(load_addr, num_words, cksum);
271}
diff --git a/arch/ppc/boot/simple/misc.c b/arch/ppc/boot/simple/misc.c
deleted file mode 100644
index c3d3305eb5ca..000000000000
--- a/arch/ppc/boot/simple/misc.c
+++ /dev/null
@@ -1,278 +0,0 @@
1/*
2 * Misc. bootloader code for many machines. This assumes you have are using
3 * a 6xx/7xx/74xx CPU in your machine. This assumes the chunk of memory
4 * below 8MB is free. Finally, it assumes you have a NS16550-style uart for
5 * your serial console. If a machine meets these requirements, it can quite
6 * likely use this code during boot.
7 *
8 * Author: Matt Porter <mporter@mvista.com>
9 * Derived from arch/ppc/boot/prep/misc.c
10 *
11 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#include <linux/types.h>
18#include <linux/string.h>
19
20#include <asm/page.h>
21#include <asm/mmu.h>
22#include <asm/bootinfo.h>
23#ifdef CONFIG_4xx
24#include <asm/ibm4xx.h>
25#endif
26#include <asm/reg.h>
27
28#include "nonstdio.h"
29
30/* Default cmdline */
31#ifdef CONFIG_CMDLINE
32#define CMDLINE CONFIG_CMDLINE
33#else
34#define CMDLINE ""
35#endif
36
37/* Keyboard (and VGA console)? */
38#ifdef CONFIG_VGA_CONSOLE
39#define HAS_KEYB 1
40#else
41#define HAS_KEYB 0
42#endif
43
44/* Will / Can the user give input?
45 */
46#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
47 || defined(CONFIG_VGA_CONSOLE) \
48 || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
49 || defined(CONFIG_SERIAL_MPSC_CONSOLE))
50#define INTERACTIVE_CONSOLE 1
51#endif
52
53char *avail_ram;
54char *end_avail;
55char *zimage_start;
56char cmd_preset[] = CMDLINE;
57char cmd_buf[256];
58char *cmd_line = cmd_buf;
59int keyb_present = HAS_KEYB;
60int zimage_size;
61
62unsigned long com_port;
63unsigned long initrd_size = 0;
64
65/* The linker tells us various locations in the image */
66extern char __image_begin, __image_end;
67extern char __ramdisk_begin, __ramdisk_end;
68extern char _end[];
69/* Original location */
70extern unsigned long start;
71
72extern int CRT_tstc(void);
73extern unsigned long serial_init(int chan, void *ignored);
74extern void serial_close(unsigned long com_port);
75extern void gunzip(void *, int, unsigned char *, int *);
76extern void serial_fixups(void);
77
78/* Allow get_mem_size to be hooked into. This is the default. */
79unsigned long __attribute__ ((weak))
80get_mem_size(void)
81{
82 return 0;
83}
84
85#if defined(CONFIG_40x)
86#define PPC4xx_EMAC0_MR0 EMAC0_BASE
87#endif
88
89#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0)
90#define PPC4xx_EMAC0_MR0 PPC44x_EMAC0_MR0
91#endif
92
93struct bi_record *
94decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
95{
96#ifdef INTERACTIVE_CONSOLE
97 int timer = 0;
98 char ch;
99#endif
100 char *cp;
101 struct bi_record *rec;
102 unsigned long initrd_loc = 0, TotalMemory = 0;
103
104#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
105 com_port = serial_init(0, NULL);
106#endif
107
108#if defined(PPC4xx_EMAC0_MR0)
109 /* Reset MAL */
110 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
111 /* Wait for reset */
112 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {};
113 /* Reset EMAC */
114 *(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000;
115 __asm__ __volatile__("eieio");
116#endif
117
118 /*
119 * Call get_mem_size(), which is memory controller dependent,
120 * and we must have the correct file linked in here.
121 */
122 TotalMemory = get_mem_size();
123
124 /* assume the chunk below 8M is free */
125 end_avail = (char *)0x00800000;
126
127 /*
128 * Reveal where we were loaded at and where we
129 * were relocated to.
130 */
131 puts("loaded at: "); puthex(load_addr);
132 puts(" "); puthex((unsigned long)(load_addr + (4*num_words)));
133 puts("\n");
134 if ( (unsigned long)load_addr != (unsigned long)&start )
135 {
136 puts("relocated to: "); puthex((unsigned long)&start);
137 puts(" ");
138 puthex((unsigned long)((unsigned long)&start + (4*num_words)));
139 puts("\n");
140 }
141
142 /*
143 * We link ourself to 0x00800000. When we run, we relocate
144 * ourselves there. So we just need __image_begin for the
145 * start. -- Tom
146 */
147 zimage_start = (char *)(unsigned long)(&__image_begin);
148 zimage_size = (unsigned long)(&__image_end) -
149 (unsigned long)(&__image_begin);
150
151 initrd_size = (unsigned long)(&__ramdisk_end) -
152 (unsigned long)(&__ramdisk_begin);
153
154 /*
155 * The zImage and initrd will be between start and _end, so they've
156 * already been moved once. We're good to go now. -- Tom
157 */
158 avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
159 puts("zimage at: "); puthex((unsigned long)zimage_start);
160 puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
161 puts("\n");
162
163 if ( initrd_size ) {
164 puts("initrd at: ");
165 puthex((unsigned long)(&__ramdisk_begin));
166 puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
167 }
168
169#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */
170 avail_ram = (char *)0x00400000;
171#endif
172 end_avail = (char *)0x00800000;
173 puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
174 puthex((unsigned long)end_avail); puts("\n");
175
176 if (keyb_present)
177 CRT_tstc(); /* Forces keyboard to be initialized */
178
179 /* Display standard Linux/PPC boot prompt for kernel args */
180 puts("\nLinux/PPC load: ");
181 cp = cmd_line;
182 memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
183 while ( *cp ) putc(*cp++);
184
185#ifdef INTERACTIVE_CONSOLE
186 /*
187 * If they have a console, allow them to edit the command line.
188 * Otherwise, don't bother wasting the five seconds.
189 */
190 while (timer++ < 5*1000) {
191 if (tstc()) {
192 while ((ch = getc()) != '\n' && ch != '\r') {
193 /* Test for backspace/delete */
194 if (ch == '\b' || ch == '\177') {
195 if (cp != cmd_line) {
196 cp--;
197 puts("\b \b");
198 }
199 /* Test for ^x/^u (and wipe the line) */
200 } else if (ch == '\030' || ch == '\025') {
201 while (cp != cmd_line) {
202 cp--;
203 puts("\b \b");
204 }
205 } else {
206 *cp++ = ch;
207 putc(ch);
208 }
209 }
210 break; /* Exit 'timer' loop */
211 }
212 udelay(1000); /* 1 msec */
213 }
214 *cp = 0;
215#endif
216 puts("\n");
217
218 puts("Uncompressing Linux...");
219 gunzip(NULL, 0x400000, zimage_start, &zimage_size);
220 puts("done.\n");
221
222 /* get the bi_rec address */
223 rec = bootinfo_addr(zimage_size);
224
225 /* We need to make sure that the initrd and bi_recs do not
226 * overlap. */
227 if ( initrd_size ) {
228 unsigned long rec_loc = (unsigned long) rec;
229 initrd_loc = (unsigned long)(&__ramdisk_begin);
230 /* If the bi_recs are in the middle of the current
231 * initrd, move the initrd to the next MB
232 * boundary. */
233 if ((rec_loc > initrd_loc) &&
234 ((initrd_loc + initrd_size) > rec_loc)) {
235 initrd_loc = _ALIGN((unsigned long)(zimage_size)
236 + (2 << 20) - 1, (2 << 20));
237 memmove((void *)initrd_loc, &__ramdisk_begin,
238 initrd_size);
239 puts("initrd moved: "); puthex(initrd_loc);
240 puts(" "); puthex(initrd_loc + initrd_size);
241 puts("\n");
242 }
243 }
244
245 bootinfo_init(rec);
246 if ( TotalMemory )
247 bootinfo_append(BI_MEMSIZE, sizeof(int), (void*)&TotalMemory);
248
249 bootinfo_append(BI_CMD_LINE, strlen(cmd_line)+1, (void*)cmd_line);
250
251 /* add a bi_rec for the initrd if it exists */
252 if (initrd_size) {
253 unsigned long initrd[2];
254
255 initrd[0] = initrd_loc;
256 initrd[1] = initrd_size;
257
258 bootinfo_append(BI_INITRD, sizeof(initrd), &initrd);
259 }
260 puts("Now booting the kernel\n");
261 serial_close(com_port);
262
263 return rec;
264}
265
266void __attribute__ ((weak))
267board_isa_init(void)
268{
269}
270
271/* Allow decompress_kernel to be hooked into. This is the default. */
272void * __attribute__ ((weak))
273load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
274 void *ign1, void *ign2)
275{
276 board_isa_init();
277 return decompress_kernel(load_addr, num_words, cksum);
278}
diff --git a/arch/ppc/boot/simple/mpc10x_memory.c b/arch/ppc/boot/simple/mpc10x_memory.c
deleted file mode 100644
index 8da8f576031d..000000000000
--- a/arch/ppc/boot/simple/mpc10x_memory.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * A routine to find out how much memory the machine has.
3 *
4 * Based on:
5 * arch/ppc/kernel/mpc10x_common.c
6 *
7 * Author: Mark A. Greer
8 * mgreer@mvista.com
9 *
10 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/pci.h>
17#include <asm/types.h>
18#include <asm/io.h>
19#include "mpc10x.h"
20
21/*
22 * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
23 */
24
25/*
26 * PCI config space macros, similar to indirect_xxx and early_xxx macros.
27 * We assume bus 0.
28 */
29#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
30#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
31
32#define MPC10X_PCI_OP(rw, size, type, op, mask) \
33static void \
34mpc10x_##rw##_config_##size(unsigned int __iomem *cfg_addr, \
35 unsigned int *cfg_data, int devfn, int offset, \
36 type val) \
37{ \
38 out_be32(cfg_addr, \
39 ((offset & 0xfc) << 24) | (devfn << 16) \
40 | (0 << 8) | 0x80); \
41 MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
42 return; \
43}
44
45MPC10X_PCI_OP(read, byte, u8 *, in_8, 3)
46MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
47
48/*
49 * Read the memory controller registers to determine the amount of memory in
50 * the system. This assumes that the firmware has correctly set up the memory
51 * controller registers. On CONFIG_PPC_PREP, we know we are being called
52 * under a PReP memory map. On all other machines, we assume we are under
53 * a CHRP memory map. Further, on CONFIG_PPC_PREP we must rename
54 * this function.
55 */
56#ifdef CONFIG_PPC_PREP
57#define get_mem_size mpc10x_get_mem_size
58#endif
59unsigned long
60get_mem_size(void)
61{
62 unsigned int *config_addr, *config_data, val;
63 unsigned long start, end, total, offset;
64 int i;
65 unsigned char bank_enables;
66
67#ifdef CONFIG_PPC_PREP
68 config_addr = (unsigned int *)MPC10X_MAPA_CNFG_ADDR;
69 config_data = (unsigned int *)MPC10X_MAPA_CNFG_DATA;
70#else
71 config_addr = (unsigned int *)MPC10X_MAPB_CNFG_ADDR;
72 config_data = (unsigned int *)MPC10X_MAPB_CNFG_DATA;
73#endif
74
75 mpc10x_read_config_byte(config_addr, config_data, PCI_DEVFN(0,0),
76 MPC10X_MCTLR_MEM_BANK_ENABLES, &bank_enables);
77
78 total = 0;
79
80 for (i = 0; i < 8; i++) {
81 if (bank_enables & (1 << i)) {
82 offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
83 mpc10x_read_config_dword(config_addr, config_data,
84 PCI_DEVFN(0,0), offset, &val);
85 start = (val >> ((i & 3) << 3)) & 0xff;
86
87 offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
88 mpc10x_read_config_dword(config_addr, config_data,
89 PCI_DEVFN(0,0), offset, &val);
90 val = (val >> ((i & 3) << 3)) & 0x03;
91 start = (val << 28) | (start << 20);
92
93 offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
94 mpc10x_read_config_dword(config_addr, config_data,
95 PCI_DEVFN(0,0), offset, &val);
96 end = (val >> ((i & 3) << 3)) & 0xff;
97
98 offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
99 mpc10x_read_config_dword(config_addr, config_data,
100 PCI_DEVFN(0,0), offset, &val);
101 val = (val >> ((i & 3) << 3)) & 0x03;
102 end = (val << 28) | (end << 20) | 0xfffff;
103
104 total += (end - start + 1);
105 }
106 }
107
108 return total;
109}
diff --git a/arch/ppc/boot/simple/mpc52xx_tty.c b/arch/ppc/boot/simple/mpc52xx_tty.c
deleted file mode 100644
index 6955891fb031..000000000000
--- a/arch/ppc/boot/simple/mpc52xx_tty.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Minimal serial functions needed to send messages out a MPC52xx
3 * Programmable Serial Controller (PSC).
4 *
5 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
6 *
7 * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is licensed
9 * "as is" without any warranty of any kind, whether express or implied.
10 */
11
12#include <linux/types.h>
13#include <asm/uaccess.h>
14#include <asm/mpc52xx.h>
15#include <asm/mpc52xx_psc.h>
16#include <asm/serial.h>
17#include <asm/io.h>
18#include <asm/time.h>
19
20
21#ifdef MPC52xx_PF_CONSOLE_PORT
22#define MPC52xx_CONSOLE MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT)
23#define MPC52xx_PSC_CONFIG_SHIFT ((MPC52xx_PF_CONSOLE_PORT-1)<<2)
24#else
25#error "MPC52xx_PF_CONSOLE_PORT not defined"
26#endif
27
28static struct mpc52xx_psc __iomem *psc =
29 (struct mpc52xx_psc __iomem *) MPC52xx_PA(MPC52xx_CONSOLE);
30
31/* The decrementer counts at the system bus clock frequency
32 * divided by four. The most accurate time base is connected to the
33 * rtc. We read the decrementer change during one rtc tick
34 * and multiply by 4 to get the system bus clock frequency. Since a
35 * rtc tick is one seconds, and that's pretty long, we change the rtc
36 * dividers temporarily to set them 64x faster ;)
37 */
38static int
39mpc52xx_ipbfreq(void)
40{
41 struct mpc52xx_rtc __iomem *rtc =
42 (struct mpc52xx_rtc __iomem *) MPC52xx_PA(MPC52xx_RTC_OFFSET);
43 struct mpc52xx_cdm __iomem *cdm =
44 (struct mpc52xx_cdm __iomem *) MPC52xx_PA(MPC52xx_CDM_OFFSET);
45 int current_time, previous_time;
46 int tbl_start, tbl_end;
47 int xlbfreq, ipbfreq;
48
49 out_be32(&rtc->dividers, 0x8f1f0000); /* Set RTC 64x faster */
50 previous_time = in_be32(&rtc->time);
51 while ((current_time = in_be32(&rtc->time)) == previous_time) ;
52 tbl_start = get_tbl();
53 previous_time = current_time;
54 while ((current_time = in_be32(&rtc->time)) == previous_time) ;
55 tbl_end = get_tbl();
56 out_be32(&rtc->dividers, 0xffff0000); /* Restore RTC */
57
58 xlbfreq = (tbl_end - tbl_start) << 8;
59 ipbfreq = (in_8(&cdm->ipb_clk_sel) & 1) ? xlbfreq / 2 : xlbfreq;
60
61 return ipbfreq;
62}
63
64unsigned long
65serial_init(int ignored, void *ignored2)
66{
67 struct mpc52xx_gpio __iomem *gpio =
68 (struct mpc52xx_gpio __iomem *) MPC52xx_PA(MPC52xx_GPIO_OFFSET);
69 int divisor;
70 int mode1;
71 int mode2;
72 u32 val32;
73
74 static int been_here = 0;
75
76 if (been_here)
77 return 0;
78
79 been_here = 1;
80
81 val32 = in_be32(&gpio->port_config);
82 val32 &= ~(0x7 << MPC52xx_PSC_CONFIG_SHIFT);
83 val32 |= MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD
84 << MPC52xx_PSC_CONFIG_SHIFT;
85 out_be32(&gpio->port_config, val32);
86
87 out_8(&psc->command, MPC52xx_PSC_RST_TX
88 | MPC52xx_PSC_RX_DISABLE | MPC52xx_PSC_TX_ENABLE);
89 out_8(&psc->command, MPC52xx_PSC_RST_RX);
90
91 out_be32(&psc->sicr, 0x0);
92 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
93 out_be16(&psc->tfalarm, 0xf8);
94
95 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1
96 | MPC52xx_PSC_RX_ENABLE
97 | MPC52xx_PSC_TX_ENABLE);
98
99 divisor = ((mpc52xx_ipbfreq()
100 / (CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD * 16)) + 1) >> 1;
101
102 mode1 = MPC52xx_PSC_MODE_8_BITS | MPC52xx_PSC_MODE_PARNONE
103 | MPC52xx_PSC_MODE_ERR;
104 mode2 = MPC52xx_PSC_MODE_ONE_STOP;
105
106 out_8(&psc->ctur, divisor>>8);
107 out_8(&psc->ctlr, divisor);
108 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
109 out_8(&psc->mode, mode1);
110 out_8(&psc->mode, mode2);
111
112 return 0; /* ignored */
113}
114
115void
116serial_putc(void *ignored, const char c)
117{
118 serial_init(0, NULL);
119
120 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP)) ;
121 out_8(&psc->mpc52xx_psc_buffer_8, c);
122 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP)) ;
123}
124
125char
126serial_getc(void *ignored)
127{
128 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY)) ;
129
130 return in_8(&psc->mpc52xx_psc_buffer_8);
131}
132
133int
134serial_tstc(void *ignored)
135{
136 return (in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY) != 0;
137}
diff --git a/arch/ppc/boot/simple/mv64x60_tty.c b/arch/ppc/boot/simple/mv64x60_tty.c
deleted file mode 100644
index 8a735787a6e9..000000000000
--- a/arch/ppc/boot/simple/mv64x60_tty.c
+++ /dev/null
@@ -1,364 +0,0 @@
1/*
2 * Bootloader version of the embedded MPSC/UART driver for the Marvell 64x60.
3 * Note: Due to a GT64260A erratum, DMA will be used for UART input (via SDMA).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2001 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/* This code assumes that the data cache has been disabled (L1, L2, L3). */
14
15#include <linux/types.h>
16#include <linux/serial_reg.h>
17#include <asm/serial.h>
18#include <asm/io.h>
19#include <asm/mv64x60_defs.h>
20#include <mpsc_defs.h>
21
22#ifdef CONFIG_EV64360
23#include <platforms/ev64360.h>
24u32 mv64x60_console_baud = EV64360_DEFAULT_BAUD;
25u32 mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; /* TCLK */
26u32 mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ;
27#else
28u32 mv64x60_console_baud = 9600;
29u32 mv64x60_mpsc_clk_src = 8; /* TCLK */
30u32 mv64x60_mpsc_clk_freq = 100000000;
31#endif
32
33extern void udelay(long);
34static void stop_dma(int chan);
35
36static void __iomem *mv64x60_base = (void __iomem *)CONFIG_MV64X60_NEW_BASE;
37
38struct sdma_regs {
39 u32 sdc;
40 u32 sdcm;
41 u32 rx_desc;
42 u32 rx_buf_ptr;
43 u32 scrdp;
44 u32 tx_desc;
45 u32 sctdp;
46 u32 sftdp;
47};
48
49static struct sdma_regs sdma_regs[2];
50
51#define SDMA_REGS_INIT(s, reg_base) { \
52 (s)->sdc = (reg_base) + SDMA_SDC; \
53 (s)->sdcm = (reg_base) + SDMA_SDCM; \
54 (s)->rx_desc = (reg_base) + SDMA_RX_DESC; \
55 (s)->rx_buf_ptr = (reg_base) + SDMA_RX_BUF_PTR; \
56 (s)->scrdp = (reg_base) + SDMA_SCRDP; \
57 (s)->tx_desc = (reg_base) + SDMA_TX_DESC; \
58 (s)->sctdp = (reg_base) + SDMA_SCTDP; \
59 (s)->sftdp = (reg_base) + SDMA_SFTDP; \
60}
61
62static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET };
63
64struct mv64x60_rx_desc {
65 u16 bufsize;
66 u16 bytecnt;
67 u32 cmd_stat;
68 u32 next_desc_ptr;
69 u32 buffer;
70};
71
72struct mv64x60_tx_desc {
73 u16 bytecnt;
74 u16 shadow;
75 u32 cmd_stat;
76 u32 next_desc_ptr;
77 u32 buffer;
78};
79
80#define MAX_RESET_WAIT 10000
81#define MAX_TX_WAIT 10000
82
83#define RX_NUM_DESC 2
84#define TX_NUM_DESC 2
85
86#define RX_BUF_SIZE 32
87#define TX_BUF_SIZE 32
88
89static struct mv64x60_rx_desc rd[2][RX_NUM_DESC] __attribute__ ((aligned(32)));
90static struct mv64x60_tx_desc td[2][TX_NUM_DESC] __attribute__ ((aligned(32)));
91
92static char rx_buf[2][RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
93static char tx_buf[2][TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
94
95static int cur_rd[2] = { 0, 0 };
96static int cur_td[2] = { 0, 0 };
97
98static char chan_initialized[2] = { 0, 0 };
99
100
101#define RX_INIT_RDP(rdp) { \
102 (rdp)->bufsize = 2; \
103 (rdp)->bytecnt = 0; \
104 (rdp)->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F | \
105 SDMA_DESC_CMDSTAT_O; \
106}
107
108#ifdef CONFIG_MV64360
109static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
110 { MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
111 { MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
112 { MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
113 { MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
114};
115
116static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
117 { MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
118 { MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
119 { MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
120 { MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
121};
122
123static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
124#endif
125
126unsigned long
127serial_init(int chan, void *ignored)
128{
129 u32 mpsc_routing_base, sdma_base, brg_bcr, cdv;
130 int i;
131
132 chan = (chan == 1); /* default to chan 0 if anything but 1 */
133
134 if (chan_initialized[chan])
135 return chan;
136
137 chan_initialized[chan] = 1;
138
139 if (chan == 0) {
140 sdma_base = MV64x60_SDMA_0_OFFSET;
141 brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR;
142 SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET);
143 } else {
144 sdma_base = MV64x60_SDMA_1_OFFSET;
145 brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR;
146 SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET);
147 }
148
149 mpsc_routing_base = MV64x60_MPSC_ROUTING_OFFSET;
150
151 stop_dma(chan);
152
153 /* Set up ring buffers */
154 for (i=0; i<RX_NUM_DESC; i++) {
155 RX_INIT_RDP(&rd[chan][i]);
156 rd[chan][i].buffer = (u32)&rx_buf[chan][i * RX_BUF_SIZE];
157 rd[chan][i].next_desc_ptr = (u32)&rd[chan][i+1];
158 }
159 rd[chan][RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[chan][0];
160
161 for (i=0; i<TX_NUM_DESC; i++) {
162 td[chan][i].bytecnt = 0;
163 td[chan][i].shadow = 0;
164 td[chan][i].buffer = (u32)&tx_buf[chan][i * TX_BUF_SIZE];
165 td[chan][i].cmd_stat = SDMA_DESC_CMDSTAT_F|SDMA_DESC_CMDSTAT_L;
166 td[chan][i].next_desc_ptr = (u32)&td[chan][i+1];
167 }
168 td[chan][TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[chan][0];
169
170 /* Set MPSC Routing */
171 out_le32(mv64x60_base + mpsc_routing_base + MPSC_MRR, 0x3ffffe38);
172
173#ifdef CONFIG_GT64260
174 out_le32(mv64x60_base + GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
175#else /* Must be MV64360 or MV64460 */
176 {
177 u32 enables, prot_bits, v;
178
179 /* Set up comm unit to memory mapping windows */
180 /* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */
181
182 enables = in_le32(mv64x60_base + MV64360_CPU_BAR_ENABLE) & 0xf;
183 prot_bits = 0;
184
185 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
186 if (!(enables & (1 << i))) {
187 v = in_le32(mv64x60_base + cpu2mem_tab[i][0]);
188 v = ((v & 0xffff) << 16) | (dram_selects[i] << 8);
189 out_le32(mv64x60_base + com2mem_tab[i][0], v);
190
191 v = in_le32(mv64x60_base + cpu2mem_tab[i][1]);
192 v = (v & 0xffff) << 16;
193 out_le32(mv64x60_base + com2mem_tab[i][1], v);
194
195 prot_bits |= (0x3 << (i << 1)); /* r/w access */
196 }
197 }
198
199 out_le32(mv64x60_base + MV64360_MPSC_0_REMAP, 0);
200 out_le32(mv64x60_base + MV64360_MPSC_1_REMAP, 0);
201 out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
202 out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
203 out_le32(mv64x60_base + MV64360_MPSC2MEM_BAR_ENABLE, enables);
204 }
205#endif
206
207 /* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
208 out_le32(mv64x60_base + mpsc_routing_base + MPSC_RCRR, 0x00000100);
209 out_le32(mv64x60_base + mpsc_routing_base + MPSC_TCRR, 0x00000100);
210
211 /* clear pending interrupts */
212 out_le32(mv64x60_base + MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);
213
214 out_le32(mv64x60_base + SDMA_SCRDP + sdma_base, (int)&rd[chan][0]);
215 out_le32(mv64x60_base + SDMA_SCTDP + sdma_base,
216 (int)&td[chan][TX_NUM_DESC - 1]);
217 out_le32(mv64x60_base + SDMA_SFTDP + sdma_base,
218 (int)&td[chan][TX_NUM_DESC - 1]);
219
220 out_le32(mv64x60_base + SDMA_SDC + sdma_base,
221 SDMA_SDC_RFT | SDMA_SDC_SFM | SDMA_SDC_BLMR | SDMA_SDC_BLMT |
222 (3 << 12));
223
224 cdv = ((mv64x60_mpsc_clk_freq/(32*mv64x60_console_baud))-1);
225 out_le32(mv64x60_base + brg_bcr,
226 ((mv64x60_mpsc_clk_src << 18) | (1 << 16) | cdv));
227
228 /* Put MPSC into UART mode, no null modem, 16x clock mode */
229 out_le32(mv64x60_base + MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
230 out_le32(mv64x60_base + MPSC_MMCRH + mpsc_base[chan], 0x04400400);
231
232 out_le32(mv64x60_base + MPSC_CHR_1 + mpsc_base[chan], 0);
233 out_le32(mv64x60_base + MPSC_CHR_9 + mpsc_base[chan], 0);
234 out_le32(mv64x60_base + MPSC_CHR_10 + mpsc_base[chan], 0);
235 out_le32(mv64x60_base + MPSC_CHR_3 + mpsc_base[chan], 4);
236 out_le32(mv64x60_base + MPSC_CHR_4 + mpsc_base[chan], 0);
237 out_le32(mv64x60_base + MPSC_CHR_5 + mpsc_base[chan], 0);
238 out_le32(mv64x60_base + MPSC_CHR_6 + mpsc_base[chan], 0);
239 out_le32(mv64x60_base + MPSC_CHR_7 + mpsc_base[chan], 0);
240 out_le32(mv64x60_base + MPSC_CHR_8 + mpsc_base[chan], 0);
241
242 /* 8 data bits, 1 stop bit */
243 out_le32(mv64x60_base + MPSC_MPCR + mpsc_base[chan], (3 << 12));
244 out_le32(mv64x60_base + SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
245 out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);
246
247 udelay(100);
248
249 return chan;
250}
251
252static void
253stop_dma(int chan)
254{
255 int i;
256
257 /* Abort MPSC Rx (aborting Tx messes things up) */
258 out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);
259
260 /* Abort SDMA Rx, Tx */
261 out_le32(mv64x60_base + sdma_regs[chan].sdcm,
262 SDMA_SDCM_AR | SDMA_SDCM_STD);
263
264 for (i=0; i<MAX_RESET_WAIT; i++) {
265 if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
266 (SDMA_SDCM_AR | SDMA_SDCM_AT)) == 0)
267 break;
268
269 udelay(100);
270 }
271}
272
273static int
274wait_for_ownership(int chan)
275{
276 int i;
277
278 for (i=0; i<MAX_TX_WAIT; i++) {
279 if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
280 SDMA_SDCM_TXD) == 0)
281 break;
282
283 udelay(1000);
284 }
285
286 return (i < MAX_TX_WAIT);
287}
288
289void
290serial_putc(unsigned long com_port, unsigned char c)
291{
292 struct mv64x60_tx_desc *tdp;
293
294 if (wait_for_ownership(com_port) == 0)
295 return;
296
297 tdp = &td[com_port][cur_td[com_port]];
298 if (++cur_td[com_port] >= TX_NUM_DESC)
299 cur_td[com_port] = 0;
300
301 *(unchar *)(tdp->buffer ^ 7) = c;
302 tdp->bytecnt = 1;
303 tdp->shadow = 1;
304 tdp->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F |
305 SDMA_DESC_CMDSTAT_O;
306
307 out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp);
308 out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp);
309 out_le32(mv64x60_base + sdma_regs[com_port].sdcm,
310 in_le32(mv64x60_base + sdma_regs[com_port].sdcm) |
311 SDMA_SDCM_TXD);
312}
313
314unsigned char
315serial_getc(unsigned long com_port)
316{
317 struct mv64x60_rx_desc *rdp;
318 unchar c = '\0';
319
320 rdp = &rd[com_port][cur_rd[com_port]];
321
322 if ((rdp->cmd_stat & (SDMA_DESC_CMDSTAT_O|SDMA_DESC_CMDSTAT_ES)) == 0) {
323 c = *(unchar *)(rdp->buffer ^ 7);
324 RX_INIT_RDP(rdp);
325 if (++cur_rd[com_port] >= RX_NUM_DESC)
326 cur_rd[com_port] = 0;
327 }
328
329 return c;
330}
331
332int
333serial_tstc(unsigned long com_port)
334{
335 struct mv64x60_rx_desc *rdp;
336 int loop_count = 0;
337 int rc = 0;
338
339 rdp = &rd[com_port][cur_rd[com_port]];
340
341 /* Go through rcv descs until empty looking for one with data (no error)*/
342 while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
343 (loop_count++ < RX_NUM_DESC)) {
344
345 /* If there was an error, reinit the desc & continue */
346 if ((rdp->cmd_stat & SDMA_DESC_CMDSTAT_ES) != 0) {
347 RX_INIT_RDP(rdp);
348 if (++cur_rd[com_port] >= RX_NUM_DESC)
349 cur_rd[com_port] = 0;
350 rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr;
351 } else {
352 rc = 1;
353 break;
354 }
355 }
356
357 return rc;
358}
359
360void
361serial_close(unsigned long com_port)
362{
363 stop_dma(com_port);
364}
diff --git a/arch/ppc/boot/simple/openbios.c b/arch/ppc/boot/simple/openbios.c
deleted file mode 100644
index 6ff2701598f2..000000000000
--- a/arch/ppc/boot/simple/openbios.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * Copyright (c) 2005 DENX Software Engineering
3 * Stefan Roese <sr@denx.de>
4 *
5 * Based on original work by
6 * 2005 (c) SYSGO AG - g.jaeger@sysgo.com
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without
10 * any warranty of any kind, whether express or implied.
11 *
12 */
13
14#include <linux/types.h>
15#include <linux/string.h>
16#include <asm/ppcboot.h>
17#include <asm/ibm4xx.h>
18#include <asm/reg.h>
19#ifdef CONFIG_40x
20#include <asm/io.h>
21#endif
22
23#if defined(CONFIG_BUBINGA)
24#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */
25#else
26#define BOARD_INFO_VECTOR 0xFFFE0B50
27#endif
28
29#ifdef CONFIG_40x
30/* Supply a default Ethernet address for those eval boards that don't
31 * ship with one. This is an address from the MBX board I have, so
32 * it is unlikely you will find it on your network.
33 */
34static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };
35
36extern unsigned long timebase_period_ns;
37#endif /* CONFIG_40x */
38
39extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
40 unsigned long cksum);
41
42/* We need to make sure that this is before the images to ensure
43 * that it's in a mapped location. */
44bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
45bd_t *hold_residual = &hold_resid_buf;
46
47typedef struct openbios_board_info {
48 unsigned char bi_s_version[4]; /* Version of this structure */
49 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
50 unsigned int bi_memsize; /* DRAM installed, in bytes */
51#ifdef CONFIG_405EP
52 unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */
53#else /* CONFIG_405EP */
54 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
55#endif /* CONFIG_405EP */
56 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
57 unsigned int bi_intfreq; /* Processor speed, in Hz */
58 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
59 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
60#ifdef CONFIG_405EP
61 unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
62 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
63#endif /* CONFIG_405EP */
64} openbios_bd_t;
65
66void *
67load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
68 void *ign1, void *ign2)
69{
70#ifdef CONFIG_40x
71 openbios_bd_t *openbios_bd = NULL;
72 openbios_bd_t *(*get_board_info)(void) =
73 (openbios_bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR);
74
75 /*
76 * On 40x platforms we not only need the MAC-addresses, but also the
77 * clocks and memsize. Now try to get all values using the OpenBIOS
78 * "get_board_info()" callback.
79 */
80 if ((openbios_bd = get_board_info()) != NULL) {
81 /*
82 * Copy bd_info from OpenBIOS struct into U-Boot struct
83 * used by kernel
84 */
85 hold_residual->bi_memsize = openbios_bd->bi_memsize;
86 hold_residual->bi_intfreq = openbios_bd->bi_intfreq;
87 hold_residual->bi_busfreq = openbios_bd->bi_busfreq;
88 hold_residual->bi_pci_busfreq = openbios_bd->bi_pci_busfreq;
89 memcpy(hold_residual->bi_pci_enetaddr, openbios_bd->bi_pci_enetaddr, 6);
90#ifdef CONFIG_405EP
91 memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr[0], 6);
92 memcpy(hold_residual->bi_enet1addr, openbios_bd->bi_enetaddr[1], 6);
93 hold_residual->bi_opbfreq = openbios_bd->bi_opb_busfreq;
94 hold_residual->bi_procfreq = openbios_bd->bi_pllouta_freq;
95#else /* CONFIG_405EP */
96 memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr, 6);
97#endif /* CONFIG_405EP */
98 } else {
99 /* Hmmm...better try to stuff some defaults.
100 */
101 hold_residual->bi_memsize = 16 * 1024 * 1024;
102 hold_residual->bi_intfreq = 200000000;
103 hold_residual->bi_busfreq = 100000000;
104 hold_residual->bi_pci_busfreq = 66666666;
105
106 /*
107 * Only supply one mac-address in this fallback
108 */
109 memcpy(hold_residual->bi_enetaddr, (void *)def_enet_addr, 6);
110#ifdef CONFIG_405EP
111 hold_residual->bi_opbfreq = 50000000;
112 hold_residual->bi_procfreq = 200000000;
113#endif /* CONFIG_405EP */
114 }
115
116 timebase_period_ns = 1000000000 / hold_residual->bi_intfreq;
117#endif /* CONFIG_40x */
118
119#ifdef CONFIG_440GP
120 /* simply copy the MAC addresses */
121 memcpy(hold_residual->bi_enetaddr, (char *)OPENBIOS_MAC_BASE, 6);
122 memcpy(hold_residual->bi_enet1addr, (char *)(OPENBIOS_MAC_BASE+OPENBIOS_MAC_OFFSET), 6);
123#endif /* CONFIG_440GP */
124
125 decompress_kernel(load_addr, num_words, cksum);
126
127 return (void *)hold_residual;
128}
diff --git a/arch/ppc/boot/simple/pci.c b/arch/ppc/boot/simple/pci.c
deleted file mode 100644
index b0f673c8b7d9..000000000000
--- a/arch/ppc/boot/simple/pci.c
+++ /dev/null
@@ -1,274 +0,0 @@
1/* Stand alone funtions for QSpan Tundra support.
2 */
3#include <linux/types.h>
4#include <linux/pci.h>
5#include <asm/mpc8xx.h>
6
7extern void puthex(unsigned long val);
8extern void puts(const char *);
9
10/* To map PCI devices, you first write 0xffffffff into the device
11 * base address registers. When the register is read back, the
12 * number of most significant '1' bits describes the amount of address
13 * space needed for mapping. If the most significant bit is not set,
14 * either the device does not use that address register, or it has
15 * a fixed address that we can't change. After the address is assigned,
16 * the command register has to be written to enable the card.
17 */
18typedef struct {
19 u_char pci_bus;
20 u_char pci_devfn;
21 ushort pci_command;
22 uint pci_addrs[6];
23} pci_map_t;
24
25/* We should probably dynamically allocate these structures.
26*/
27#define MAX_PCI_DEVS 32
28int pci_dev_cnt;
29pci_map_t pci_map[MAX_PCI_DEVS];
30
31void pci_conf_write(int bus, int device, int func, int reg, uint writeval);
32void pci_conf_read(int bus, int device, int func, int reg, void *readval);
33void probe_addresses(int bus, int devfn);
34void map_pci_addrs(void);
35
36extern int
37qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
38 unsigned char offset, unsigned char *val);
39extern int
40qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
41 unsigned char offset, unsigned short *val);
42extern int
43qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
44 unsigned char offset, unsigned int *val);
45extern int
46qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
47 unsigned char offset, unsigned char val);
48extern int
49qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
50 unsigned char offset, unsigned short val);
51extern int
52qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
53 unsigned char offset, unsigned int val);
54
55
56/* This is a really stripped version of PCI bus scan. All we are
57 * looking for are devices that exist.
58 */
59void
60pci_scanner(int addr_probe)
61{
62 unsigned int devfn, l, class, bus_number;
63 unsigned char hdr_type, is_multi;
64
65 is_multi = 0;
66 bus_number = 0;
67 for (devfn = 0; devfn < 0xff; ++devfn) {
68 /* The device numbers are comprised of upper 5 bits of
69 * device number and lower 3 bits of multi-function number.
70 */
71 if ((devfn & 7) && !is_multi) {
72 /* Don't scan multifunction addresses if this is
73 * not a multifunction device.
74 */
75 continue;
76 }
77
78 /* Read the header to determine card type.
79 */
80 qs_pci_read_config_byte(bus_number, devfn, PCI_HEADER_TYPE,
81 &hdr_type);
82
83 /* If this is a base device number, check the header to
84 * determine if it is mulifunction.
85 */
86 if ((devfn & 7) == 0)
87 is_multi = hdr_type & 0x80;
88
89 /* Check to see if the board is really in the slot.
90 */
91 qs_pci_read_config_dword(bus_number, devfn, PCI_VENDOR_ID, &l);
92 /* some broken boards return 0 if a slot is empty: */
93 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff ||
94 l == 0xffff0000) {
95 /* Nothing there.
96 */
97 is_multi = 0;
98 continue;
99 }
100
101 /* If we are not performing an address probe,
102 * just simply print out some information.
103 */
104 if (!addr_probe) {
105 qs_pci_read_config_dword(bus_number, devfn,
106 PCI_CLASS_REVISION, &class);
107
108 class >>= 8; /* upper 3 bytes */
109
110#if 0
111 printf("Found (%3d:%d): vendor 0x%04x, device 0x%04x, class 0x%06x\n",
112 (devfn >> 3), (devfn & 7),
113 (l & 0xffff), (l >> 16) & 0xffff, class);
114#else
115 puts("Found ("); puthex(devfn >> 3);
116 puts(":"); puthex(devfn & 7);
117 puts("): vendor "); puthex(l & 0xffff);
118 puts(", device "); puthex((l >> 16) & 0xffff);
119 puts(", class "); puthex(class); puts("\n");
120#endif
121 }
122 else {
123 /* If this is a "normal" device, build address list.
124 */
125 if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL)
126 probe_addresses(bus_number, devfn);
127 }
128 }
129
130 /* Now map the boards.
131 */
132 if (addr_probe)
133 map_pci_addrs();
134}
135
136/* Probe addresses for the specified device. This is a destructive
137 * operation because it writes the registers.
138 */
139void
140probe_addresses(bus, devfn)
141{
142 int i;
143 uint pciaddr;
144 ushort pcicmd;
145 pci_map_t *pm;
146
147 if (pci_dev_cnt >= MAX_PCI_DEVS) {
148 puts("Too many PCI devices\n");
149 return;
150 }
151
152 pm = &pci_map[pci_dev_cnt++];
153
154 pm->pci_bus = bus;
155 pm->pci_devfn = devfn;
156
157 for (i=0; i<6; i++) {
158 qs_pci_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4), -1);
159 qs_pci_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4),
160 &pciaddr);
161 pm->pci_addrs[i] = pciaddr;
162 qs_pci_read_config_word(bus, devfn, PCI_COMMAND, &pcicmd);
163 pm->pci_command = pcicmd;
164 }
165}
166
167/* Map the cards into the PCI space. The PCI has separate memory
168 * and I/O spaces. In addition, some memory devices require mapping
169 * below 1M. The least significant 4 bits of the address register
170 * provide information. If this is an I/O device, only the LS bit
171 * is used to indicate that, so I/O devices can be mapped to a two byte
172 * boundard. Memory addresses can be mapped to a 32 byte boundary.
173 * The QSpan implementations usually have a 1Gbyte space for each
174 * memory and I/O spaces.
175 *
176 * This isn't a terribly fancy algorithm. I just map the spaces from
177 * the top starting with the largest address space. When finished,
178 * the registers are written and the card enabled.
179 *
180 * While the Tundra can map a large address space on most boards, we
181 * need to be careful because it may overlap other devices (like IMMR).
182 */
183#define MEMORY_SPACE_SIZE 0x20000000
184#define IO_SPACE_SIZE 0x20000000
185
186void
187map_pci_addrs()
188{
189 uint pci_mem_top, pci_mem_low;
190 uint pci_io_top;
191 uint addr_mask, reg_addr, space;
192 int i, j;
193 pci_map_t *pm;
194
195 pci_mem_top = MEMORY_SPACE_SIZE;
196 pci_io_top = IO_SPACE_SIZE;
197 pci_mem_low = (1 * 1024 * 1024); /* Below one meg addresses */
198
199 /* We can't map anything more than the maximum space, but test
200 * for it anyway to catch devices out of range.
201 */
202 addr_mask = 0x80000000;
203
204 do {
205 space = (~addr_mask) + 1; /* Size of the space */
206 for (i=0; i<pci_dev_cnt; i++) {
207 pm = &pci_map[i];
208 for (j=0; j<6; j++) {
209 /* If the MS bit is not set, this has either
210 * already been mapped, or is not used.
211 */
212 reg_addr = pm->pci_addrs[j];
213 if ((reg_addr & 0x80000000) == 0)
214 continue;
215 if (reg_addr & PCI_BASE_ADDRESS_SPACE_IO) {
216 if ((reg_addr & PCI_BASE_ADDRESS_IO_MASK) != addr_mask)
217 continue;
218 if (pci_io_top < space) {
219 puts("Out of PCI I/O space\n");
220 }
221 else {
222 pci_io_top -= space;
223 pm->pci_addrs[j] = pci_io_top;
224 pm->pci_command |= PCI_COMMAND_IO;
225 }
226 }
227 else {
228 if ((reg_addr & PCI_BASE_ADDRESS_MEM_MASK) != addr_mask)
229 continue;
230
231 /* Memory space. Test if below 1M.
232 */
233 if (reg_addr & PCI_BASE_ADDRESS_MEM_TYPE_1M) {
234 if (pci_mem_low < space) {
235 puts("Out of PCI 1M space\n");
236 }
237 else {
238 pci_mem_low -= space;
239 pm->pci_addrs[j] = pci_mem_low;
240 }
241 }
242 else {
243 if (pci_mem_top < space) {
244 puts("Out of PCI Mem space\n");
245 }
246 else {
247 pci_mem_top -= space;
248 pm->pci_addrs[j] = pci_mem_top;
249 }
250 }
251 pm->pci_command |= PCI_COMMAND_MEMORY;
252 }
253 }
254 }
255 addr_mask >>= 1;
256 addr_mask |= 0x80000000;
257 } while (addr_mask != 0xfffffffe);
258
259 /* Now, run the list one more time and map everything.
260 */
261 for (i=0; i<pci_dev_cnt; i++) {
262 pm = &pci_map[i];
263 for (j=0; j<6; j++) {
264 qs_pci_write_config_dword(pm->pci_bus, pm->pci_devfn,
265 PCI_BASE_ADDRESS_0 + (j * 4), pm->pci_addrs[j]);
266 }
267
268 /* Enable memory or address mapping.
269 */
270 qs_pci_write_config_word(pm->pci_bus, pm->pci_devfn, PCI_COMMAND,
271 pm->pci_command);
272 }
273}
274
diff --git a/arch/ppc/boot/simple/pibs.c b/arch/ppc/boot/simple/pibs.c
deleted file mode 100644
index f39d01e0619d..000000000000
--- a/arch/ppc/boot/simple/pibs.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * 2004-2005 (c) MontaVista, Software, Inc. This file is licensed under
3 * the terms of the GNU General Public License version 2. This program
4 * is licensed "as is" without any warranty of any kind, whether express
5 * or implied.
6 */
7
8#include <linux/types.h>
9#include <linux/string.h>
10#include <linux/ctype.h>
11#include <asm/ppcboot.h>
12#include <asm/ibm4xx.h>
13
14extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
15 unsigned long cksum);
16
17/* We need to make sure that this is before the images to ensure
18 * that it's in a mapped location. - Tom */
19bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
20bd_t *hold_residual = &hold_resid_buf;
21
22/* String functions lifted from lib/vsprintf.c and lib/ctype.c */
23unsigned char _ctype[] = {
24_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
25_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
26_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
27_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */
28_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */
29_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */
30_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */
31_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */
32_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */
33_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */
34_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */
35_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */
36_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */
37_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */
38_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */
39_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */
400,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
410,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
42_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */
43_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */
44_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */
45_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */
46_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */
47_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */
48
49/**
50 * simple_strtoull - convert a string to an unsigned long long
51 * @cp: The start of the string
52 * @endp: A pointer to the end of the parsed string will be placed here
53 * @base: The number base to use
54 */
55unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base)
56{
57 unsigned long long result = 0,value;
58
59 if (!base) {
60 base = 10;
61 if (*cp == '0') {
62 base = 8;
63 cp++;
64 if ((toupper(*cp) == 'X') && isxdigit(cp[1])) {
65 cp++;
66 base = 16;
67 }
68 }
69 } else if (base == 16) {
70 if (cp[0] == '0' && toupper(cp[1]) == 'X')
71 cp += 2;
72 }
73 while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
74 ? toupper(*cp) : *cp)-'A'+10) < base) {
75 result = result*base + value;
76 cp++;
77 }
78 if (endp)
79 *endp = (char *)cp;
80 return result;
81}
82
83void *
84load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
85 void *ign1, void *ign2)
86{
87 unsigned long long mac64;
88
89 decompress_kernel(load_addr, num_words, cksum);
90
91 mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
92 memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
93#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
94 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
95 memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
96#endif
97#ifdef CONFIG_440GX
98 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
99 memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
100 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
101 memcpy(hold_residual->bi_enet3addr, (char *)&mac64+2, 6);
102#endif
103 return (void *)hold_residual;
104}
diff --git a/arch/ppc/boot/simple/prepmap.c b/arch/ppc/boot/simple/prepmap.c
deleted file mode 100644
index c871a4db6e8c..000000000000
--- a/arch/ppc/boot/simple/prepmap.c
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * 2004 (C) IBM. This file is licensed under the terms of the GNU General
3 * Public License version 2. This program is licensed "as is" without any
4 * warranty of any kind, whether express or implied.
5 */
6
7#include <nonstdio.h>
8
9void board_isa_init(void)
10{
11 ISA_init(0x80000000);
12}
diff --git a/arch/ppc/boot/simple/qspan_pci.c b/arch/ppc/boot/simple/qspan_pci.c
deleted file mode 100644
index d2966d032a4c..000000000000
--- a/arch/ppc/boot/simple/qspan_pci.c
+++ /dev/null
@@ -1,269 +0,0 @@
1/*
2 * LinuxPPC arch/ppc/kernel/qspan_pci.c Dan Malek (dmalek@jlc.net)
3 *
4 * QSpan Motorola bus to PCI bridge. The config address register
5 * is located 0x500 from the base of the bridge control/status registers.
6 * The data register is located at 0x504.
7 * This is a two step operation. First, the address register is written,
8 * then the data register is read/written as required.
9 * I don't know what to do about interrupts (yet).
10 */
11
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <asm/mpc8xx.h>
16
17/*
18 * When reading the configuration space, if something does not respond
19 * the bus times out and we get a machine check interrupt. So, the
20 * good ol' exception tables come to mind to trap it and return some
21 * value.
22 *
23 * On an error we just return a -1, since that is what the caller wants
24 * returned if nothing is present. I copied this from __get_user_asm,
25 * with the only difference of returning -1 instead of EFAULT.
26 * There is an associated hack in the machine check trap code.
27 *
28 * The QSPAN is also a big endian device, that is it makes the PCI
29 * look big endian to us. This presents a problem for the Linux PCI
30 * functions, which assume little endian. For example, we see the
31 * first 32-bit word like this:
32 * ------------------------
33 * | Device ID | Vendor ID |
34 * ------------------------
35 * If we read/write as a double word, that's OK. But in our world,
36 * when read as a word, device ID is at location 0, not location 2 as
37 * the little endian PCI would believe. We have to switch bits in
38 * the PCI addresses given to us to get the data to/from the correct
39 * byte lanes.
40 *
41 * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5.
42 * It always forces the MS bit to zero. Therefore, dev_fn values
43 * greater than 128 are returned as "no device found" errors.
44 *
45 * The QSPAN can only perform long word (32-bit) configuration cycles.
46 * The "offset" must have the two LS bits set to zero. Read operations
47 * require we read the entire word and then sort out what should be
48 * returned. Write operations other than long word require that we
49 * read the long word, update the proper word or byte, then write the
50 * entire long word back.
51 *
52 * PCI Bridge hack. We assume (correctly) that bus 0 is the primary
53 * PCI bus from the QSPAN. If we are called with a bus number other
54 * than zero, we create a Type 1 configuration access that a downstream
55 * PCI bridge will interpret.
56 */
57
58#define __get_pci_config(x, addr, op) \
59 __asm__ __volatile__( \
60 "1: "op" %0,0(%1)\n" \
61 " eieio\n" \
62 "2:\n" \
63 ".section .fixup,\"ax\"\n" \
64 "3: li %0,-1\n" \
65 " b 2b\n" \
66 ".section __ex_table,\"a\"\n" \
67 " .align 2\n" \
68 " .long 1b,3b\n" \
69 ".text" \
70 : "=r"(x) : "r"(addr))
71
72#define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500))
73#define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504))
74
75#define mk_config_addr(bus, dev, offset) \
76 (((bus)<<16) | ((dev)<<8) | (offset & 0xfc))
77
78#define mk_config_type1(bus, dev, offset) \
79 mk_config_addr(bus, dev, offset) | 1;
80
81/* Initialize the QSpan device registers after power up.
82*/
83void
84qspan_init(void)
85{
86 uint *qptr;
87
88
89
90 qptr = (uint *)PCI_CSR_ADDR;
91
92 /* PCI Configuration/status. Upper bits written to clear
93 * pending interrupt or status. Lower bits enable QSPAN as
94 * PCI master, enable memory and I/O cycles, and enable PCI
95 * parity error checking.
96 * IMPORTANT: The last two bits of this word enable PCI
97 * master cycles into the QBus. The QSpan is broken and can't
98 * meet the timing specs of the PQ bus for this to work. Therefore,
99 * if you don't have external bus arbitration, you can't use
100 * this function.
101 */
102#ifdef EXTERNAL_PQ_ARB
103 qptr[1] = 0xf9000147;
104#else
105 qptr[1] = 0xf9000144;
106#endif
107
108 /* PCI Misc configuration. Set PCI latency timer resolution
109 * of 8 cycles, set cache size to 4 x 32.
110 */
111 qptr[3] = 0;
112
113 /* Set up PCI Target address mapping. Enable, Posted writes,
114 * 2Gbyte space (processor memory controller determines actual size).
115 */
116 qptr[64] = 0x8f000080;
117
118 /* Map processor 0x80000000 to PCI 0x00000000.
119 * Processor address bit 1 determines I/O type access (0x80000000)
120 * or memory type access (0xc0000000).
121 */
122 qptr[65] = 0x80000000;
123
124 /* Enable error logging and clear any pending error status.
125 */
126 qptr[80] = 0x90000000;
127
128 qptr[512] = 0x000c0003;
129
130 /* Set up Qbus slave image.
131 */
132 qptr[960] = 0x01000000;
133 qptr[961] = 0x000000d1;
134 qptr[964] = 0x00000000;
135 qptr[965] = 0x000000d1;
136
137}
138
139/* Functions to support PCI bios-like features to read/write configuration
140 * space. If the function fails for any reason, a -1 (0xffffffff) value
141 * must be returned.
142 */
143#define DEVICE_NOT_FOUND (-1)
144#define SUCCESSFUL 0
145
146int qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
147 unsigned char offset, unsigned char *val)
148{
149 uint temp;
150 u_char *cp;
151
152 if ((bus > 7) || (dev_fn > 127)) {
153 *val = 0xff;
154 return DEVICE_NOT_FOUND;
155 }
156
157 if (bus == 0)
158 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
159 else
160 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
161 __get_pci_config(temp, QS_CONFIG_DATA, "lwz");
162
163 offset ^= 0x03;
164 cp = ((u_char *)&temp) + (offset & 0x03);
165 *val = *cp;
166 return SUCCESSFUL;
167}
168
169int qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
170 unsigned char offset, unsigned short *val)
171{
172 uint temp;
173 ushort *sp;
174
175 if ((bus > 7) || (dev_fn > 127)) {
176 *val = 0xffff;
177 return DEVICE_NOT_FOUND;
178 }
179
180 if (bus == 0)
181 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
182 else
183 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
184 __get_pci_config(temp, QS_CONFIG_DATA, "lwz");
185 offset ^= 0x02;
186
187 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
188 *val = *sp;
189 return SUCCESSFUL;
190}
191
192int qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
193 unsigned char offset, unsigned int *val)
194{
195 if ((bus > 7) || (dev_fn > 127)) {
196 *val = 0xffffffff;
197 return DEVICE_NOT_FOUND;
198 }
199 if (bus == 0)
200 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
201 else
202 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
203 __get_pci_config(*val, QS_CONFIG_DATA, "lwz");
204 return SUCCESSFUL;
205}
206
207int qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
208 unsigned char offset, unsigned char val)
209{
210 uint temp;
211 u_char *cp;
212
213 if ((bus > 7) || (dev_fn > 127))
214 return DEVICE_NOT_FOUND;
215
216 qs_pci_read_config_dword(bus, dev_fn, offset, &temp);
217
218 offset ^= 0x03;
219 cp = ((u_char *)&temp) + (offset & 0x03);
220 *cp = val;
221
222 if (bus == 0)
223 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
224 else
225 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
226 *QS_CONFIG_DATA = temp;
227
228 return SUCCESSFUL;
229}
230
231int qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
232 unsigned char offset, unsigned short val)
233{
234 uint temp;
235 ushort *sp;
236
237 if ((bus > 7) || (dev_fn > 127))
238 return DEVICE_NOT_FOUND;
239
240 qs_pci_read_config_dword(bus, dev_fn, offset, &temp);
241
242 offset ^= 0x02;
243 sp = ((ushort *)&temp) + ((offset >> 1) & 1);
244 *sp = val;
245
246 if (bus == 0)
247 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
248 else
249 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
250 *QS_CONFIG_DATA = temp;
251
252 return SUCCESSFUL;
253}
254
255int qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
256 unsigned char offset, unsigned int val)
257{
258 if ((bus > 7) || (dev_fn > 127))
259 return DEVICE_NOT_FOUND;
260
261 if (bus == 0)
262 *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset);
263 else
264 *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset);
265 *(unsigned int *)QS_CONFIG_DATA = val;
266
267 return SUCCESSFUL;
268}
269
diff --git a/arch/ppc/boot/simple/relocate.S b/arch/ppc/boot/simple/relocate.S
deleted file mode 100644
index 1bbbcd2f2bcb..000000000000
--- a/arch/ppc/boot/simple/relocate.S
+++ /dev/null
@@ -1,213 +0,0 @@
1/*
2 * This is the common part of the loader relocation and initialization
3 * process. All of the board/processor specific initialization is
4 * done before we get here.
5 *
6 * Author: Tom Rini
7 * trini@mvista.com
8 * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <asm/cache.h>
17#include <asm/ppc_asm.h>
18
19#define GETSYM(reg, sym) \
20 lis reg, sym@h; ori reg, reg, sym@l
21
22 .text
23 /* We get called from the early initialization code.
24 * Register 3 has the address where we were loaded,
25 * Register 4 contains any residual data passed from the
26 * boot rom.
27 */
28 .globl relocate
29relocate:
30 /* Save r3, r4 for later.
31 * The r8/r11 are legacy registers so I don't have to
32 * rewrite the code below :-).
33 */
34 mr r8, r3
35 mr r11, r4
36
37 /* compute the size of the whole image in words. */
38 GETSYM(r4,start)
39 GETSYM(r5,end)
40
41 addi r5,r5,3 /* round up */
42 sub r5,r5,r4 /* end - start */
43 srwi r5,r5,2
44 mr r7,r5 /* Save for later use. */
45
46 /*
47 * Check if we need to relocate ourselves to the link addr or were
48 * we loaded there to begin with.
49 */
50 cmpw cr0,r3,r4
51 beq start_ldr /* If 0, we don't need to relocate */
52
53 /* Move this code somewhere safe. This is max(load + size, end)
54 * r8 == load address
55 */
56 GETSYM(r4, start)
57 GETSYM(r5, end)
58
59 sub r6,r5,r4
60 add r6,r8,r6 /* r6 == phys(load + size) */
61
62 cmpw r5,r6
63 bgt 1f
64 b 2f
651:
66 mr r6, r5
672:
68 /* dest is in r6 */
69 /* Ensure alignment --- this code is precautionary */
70 addi r6,r6,4
71 li r5,0x0003
72 andc r6,r6,r5
73
74 /* Find physical address and size of do_relocate */
75 GETSYM(r5, __relocate_start)
76 GETSYM(r4, __relocate_end)
77 GETSYM(r3, start)
78
79 /* Size to copy */
80 sub r4,r4,r5
81 srwi r4,r4,2
82
83 /* Src addr to copy (= __relocate_start - start + where_loaded) */
84 sub r3,r5,r3
85 add r5,r8,r3
86
87 /* Save dest */
88 mr r3, r6
89
90 /* Do the copy */
91 mtctr r4
923: lwz r4,0(r5)
93 stw r4,0(r3)
94 addi r3,r3,4
95 addi r5,r5,4
96 bdnz 3b
97
98 GETSYM(r4, __relocate_start)
99 GETSYM(r5, do_relocate)
100
101 sub r4,r5,r4 /* Get entry point for do_relocate in */
102 add r6,r6,r4 /* relocated section */
103
104 /* This will return to the relocated do_relocate */
105 mtlr r6
106 b flush_instruction_cache
107
108 .section ".relocate_code","xa"
109
110do_relocate:
111 /* We have 2 cases --- start < load, or start > load
112 * This determines whether we copy from the end, or the start.
113 * Its easier to have 2 loops than to have paramaterised
114 * loops. Sigh.
115 */
116 li r6,0 /* Clear checksum */
117 mtctr r7 /* Setup for a loop */
118
119 GETSYM(r4, start)
120 mr r3,r8 /* Get the load addr */
121
122 cmpw cr0,r4,r3 /* If we need to copy from the end, do so */
123 bgt do_relocate_from_end
124
125do_relocate_from_start:
1261: lwz r5,0(r3) /* Load and decrement */
127 stw r5,0(r4) /* Store and decrement */
128 addi r3,r3,4
129 addi r4,r4,4
130 xor r6,r6,r5 /* Update checksum */
131 bdnz 1b /* Are we done? */
132 b do_relocate_out /* Finished */
133
134do_relocate_from_end:
135 GETSYM(r3, end)
136 slwi r4,r7,2
137 add r4,r8,r4 /* Get the physical end */
1381: lwzu r5,-4(r4)
139 stwu r5, -4(r3)
140 xor r6,r6,r5
141 bdnz 1b
142
143do_relocate_out:
144 GETSYM(r3,start_ldr)
145 mtlr r3 /* Easiest way to do an absolute jump */
146/* Some boards don't boot up with the I-cache enabled. Do that
147 * now because the decompress runs much faster that way.
148 * As a side effect, we have to ensure the data cache is not enabled
149 * so we can access the serial I/O without trouble.
150 */
151 b flush_instruction_cache
152
153 .previous
154
155start_ldr:
156/* Clear all of BSS and set up stack for C calls */
157 lis r3,__bss_start@h
158 ori r3,r3,__bss_start@l
159 lis r4,end@h
160 ori r4,r4,end@l
161 subi r3,r3,4
162 subi r4,r4,4
163 li r0,0
16450: stwu r0,4(r3)
165 cmpw cr0,r3,r4
166 blt 50b
16790: mr r9,r1 /* Save old stack pointer (in case it matters) */
168 lis r1,.stack@h
169 ori r1,r1,.stack@l
170 addi r1,r1,4096*2
171 subi r1,r1,256
172 li r2,0x000F /* Mask pointer to 16-byte boundary */
173 andc r1,r1,r2
174
175 /*
176 * Exec kernel loader
177 */
178 mr r3,r8 /* Load point */
179 mr r4,r7 /* Program length */
180 mr r5,r6 /* Checksum */
181 mr r6,r11 /* Residual data */
182 mr r7,r25 /* Validated OFW interface */
183 bl load_kernel
184
185 /*
186 * Make sure the kernel knows we don't have things set in
187 * registers. -- Tom
188 */
189 li r4,0
190 li r5,0
191 li r6,0
192
193 /*
194 * Start at the begining.
195 */
196#ifdef CONFIG_PPC_PREP
197 li r9,0xc
198 mtlr r9
199 /* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
200 * and tell the kernel to start on the 4th instruction since we
201 * overwrite the first 3 sometimes (which are 'nop').
202 */
203 lis r10,0xdeadc0de@h
204 ori r10,r10,0xdeadc0de@l
205 li r9,0
206 stw r10,0(r9)
207#else
208 li r9,0
209 mtlr r9
210#endif
211 blr
212
213 .comm .stack,4096*2,4
diff --git a/arch/ppc/boot/simple/rw4/ppc_40x.h b/arch/ppc/boot/simple/rw4/ppc_40x.h
deleted file mode 100644
index 561fb26f5a93..000000000000
--- a/arch/ppc/boot/simple/rw4/ppc_40x.h
+++ /dev/null
@@ -1,664 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1997
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Tony J. Cerreto
22| Component: Assembler include file.
23| File: ppc_40x.h
24| Purpose: Include file containing PPC DCR defines.
25|
26| Changes:
27| Date Author Comment
28| --------- ------ --------------------------------------------------------
29| 01-Mar-00 tjc Created
30+----------------------------------------------------------------------------*/
31/* added by linguohui*/
32#define MW
33/*----------------------------------------------------------------------------+
34| PPC Special purpose registers Numbers
35+----------------------------------------------------------------------------*/
36#define ccr0 0x3b3 /* core configuration reg */
37#define ctr 0x009 /* count register */
38#define ctrreg 0x009 /* count register */
39#define dbcr0 0x3f2 /* debug control register 0 */
40#define dbcr1 0x3bd /* debug control register 1 */
41#define dbsr 0x3f0 /* debug status register */
42#define dccr 0x3fa /* data cache control reg. */
43#define dcwr 0x3ba /* data cache write-thru reg */
44#define dear 0x3d5 /* data exception address reg */
45#define esr 0x3d4 /* exception syndrome register */
46#define evpr 0x3d6 /* exception vector prefix reg */
47#define iccr 0x3fb /* instruction cache cntrl re */
48#define icdbdr 0x3d3 /* instr cache dbug data reg */
49#define lrreg 0x008 /* link register */
50#define pid 0x3b1 /* process id reg */
51#define pit 0x3db /* programmable interval time */
52#define pvr 0x11f /* processor version register */
53#define sgr 0x3b9 /* storage guarded reg */
54#define sler 0x3bb /* storage little endian reg */
55#define sprg0 0x110 /* special general purpose 0 */
56#define sprg1 0x111 /* special general purpose 1 */
57#define sprg2 0x112 /* special general purpose 2 */
58#define sprg3 0x113 /* special general purpose 3 */
59#define sprg4 0x114 /* special general purpose 4 */
60#define sprg5 0x115 /* special general purpose 5 */
61#define sprg6 0x116 /* special general purpose 6 */
62#define sprg7 0x117 /* special general purpose 7 */
63#define srr0 0x01a /* save/restore register 0 */
64#define srr1 0x01b /* save/restore register 1 */
65#define srr2 0x3de /* save/restore register 2 */
66#define srr3 0x3df /* save/restore register 3 */
67#define tbhi 0x11D
68#define tblo 0x11C
69#define tcr 0x3da /* timer control register */
70#define tsr 0x3d8 /* timer status register */
71#define xerreg 0x001 /* fixed point exception */
72#define xer 0x001 /* fixed point exception */
73#define zpr 0x3b0 /* zone protection reg */
74
75/*----------------------------------------------------------------------------+
76| Decompression Controller
77+----------------------------------------------------------------------------*/
78#define kiar 0x014 /* Decompression cntl addr reg */
79#define kidr 0x015 /* Decompression cntl data reg */
80#define kitor0 0x00 /* index table origin Reg 0 */
81#define kitor1 0x01 /* index table origin Reg 1 */
82#define kitor2 0x02 /* index table origin Reg 2 */
83#define kitor3 0x03 /* index table origin Reg 3 */
84#define kaddr0 0x04 /* addr decode Definition Reg 0 */
85#define kaddr1 0x05 /* addr decode Definition Reg 1 */
86#define kconf 0x40 /* Decompression cntl config reg */
87#define kid 0x41 /* Decompression cntl id reg */
88#define kver 0x42 /* Decompression cntl ver number */
89#define kpear 0x50 /* bus error addr reg (PLB) */
90#define kbear 0x51 /* bus error addr reg (DCP-EBC) */
91#define kesr0 0x52 /* bus error status reg 0 */
92
93/*----------------------------------------------------------------------------+
94| Romeo Specific Device Control Register Numbers.
95+----------------------------------------------------------------------------*/
96#ifndef VESTA
97#define cdbcr 0x3d7 /* cache debug cntrl reg */
98
99#define a_latcnt 0x1a9 /* PLB Latency count */
100#define a_tgval 0x1ac /* tone generation value */
101#define a_plb_pr 0x1bf /* PLB priority */
102
103#define cic_sel1 0x031 /* select register 1 */
104#define cic_sel2 0x032 /* select register 2 */
105
106#define clkgcrst 0x122 /* chip reset register */
107
108#define cp_cpmsr 0x100 /*rstatus register */
109#define cp_cpmer 0x101 /* enable register */
110
111#define dcp_kiar 0x190 /* indirect address register */
112#define dcp_kidr 0x191 /* indirect data register */
113
114#define hsmc_mcgr 0x1c0 /* HSMC global register */
115#define hsmc_mcbesr 0x1c1 /* bus error status register */
116#define hsmc_mcbear 0x1c2 /* bus error address register*/
117#define hsmc_mcbr0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */
118#define hsmc_mccr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */
119#define hsmc_mcbr1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */
120#define hsmc_mccr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */
121#define hsmc_sysr 0x1d1 /* system register */
122#define hsmc_data 0x1d2 /* data register */
123#define hsmc_mccrr 0x1d3 /* refresh register */
124
125#define ocm_pbar 0x1E0 /* base address register */
126
127#define plb0_pacr0 0x057 /* PLB arbiter control reg */
128#define plb1_pacr1 0x067 /* PLB arbiter control reg */
129
130#define v_displb 0x157 /* set left border of display*/
131#define v_disptb 0x158 /* top border of display */
132#define v_osd_la 0x159 /* first link address for OSD*/
133#define v_ptsdlta 0x15E /* PTS delta register */
134#define v_v0base 0x16C /* base mem add for VBI-0 */
135#define v_v1base 0x16D /* base mem add for VBI-1 */
136#define v_osbase 0x16E /* base mem add for OSD data */
137#endif
138
139/*----------------------------------------------------------------------------+
140| Vesta Device Control Register Numbers.
141+----------------------------------------------------------------------------*/
142/*----------------------------------------------------------------------------+
143| Cross bar switch.
144+----------------------------------------------------------------------------*/
145#define cbs0_cr 0x010 /* CBS configuration register */
146
147/*----------------------------------------------------------------------------+
148| DCR external master (DCRX).
149+----------------------------------------------------------------------------*/
150#define dcrx0_icr 0x020 /* internal control register */
151#define dcrx0_isr 0x021 /* internal status register */
152#define dcrx0_ecr 0x022 /* external control register */
153#define dcrx0_esr 0x023 /* external status register */
154#define dcrx0_tar 0x024 /* target address register */
155#define dcrx0_tdr 0x025 /* target data register */
156#define dcrx0_igr 0x026 /* interrupt generation register */
157#define dcrx0_bcr 0x027 /* buffer control register */
158
159/*----------------------------------------------------------------------------+
160| Chip interconnect configuration.
161+----------------------------------------------------------------------------*/
162#define cic0_cr 0x030 /* CIC control register */
163#define cic0_vcr 0x033 /* video macro control reg */
164#define cic0_sel3 0x035 /* select register 3 */
165
166/*----------------------------------------------------------------------------+
167| Chip interconnect configuration.
168+----------------------------------------------------------------------------*/
169#define sgpo0_sgpO 0x036 /* simplified GPIO output */
170#define sgpo0_gpod 0x037 /* simplified GPIO open drain */
171#define sgpo0_gptc 0x038 /* simplified GPIO tristate cntl */
172#define sgpo0_gpi 0x039 /* simplified GPIO input */
173
174/*----------------------------------------------------------------------------+
175| Universal interrupt controller.
176+----------------------------------------------------------------------------*/
177#define uic0_sr 0x040 /* status register */
178#define uic0_srs 0x041 /* status register set */
179#define uic0_er 0x042 /* enable register */
180#define uic0_cr 0x043 /* critical register */
181#define uic0_pr 0x044 /* parity register */
182#define uic0_tr 0x045 /* triggering register */
183#define uic0_msr 0x046 /* masked status register */
184#define uic0_vr 0x047 /* vector register */
185#define uic0_vcr 0x048 /* enable config register */
186
187/*----------------------------------------------------------------------------+
188| PLB 0 and 1.
189+----------------------------------------------------------------------------*/
190#define pb0_pesr 0x054 /* PLB error status reg 0 */
191#define pb0_pesrs 0x055 /* PLB error status reg 0 set */
192#define pb0_pear 0x056 /* PLB error address reg */
193
194#define pb1_pesr 0x064 /* PLB error status reg 1 */
195#define pb1_pesrs 0x065 /* PLB error status reg 1 set */
196#define pb1_pear 0x066 /* PLB error address reg */
197
198/*----------------------------------------------------------------------------+
199| EBIU DCR registers.
200+----------------------------------------------------------------------------*/
201#define ebiu0_brcrh0 0x070 /* bus region register 0 high */
202#define ebiu0_brcrh1 0x071 /* bus region register 1 high */
203#define ebiu0_brcrh2 0x072 /* bus region register 2 high */
204#define ebiu0_brcrh3 0x073 /* bus region register 3 high */
205#define ebiu0_brcrh4 0x074 /* bus region register 4 high */
206#define ebiu0_brcrh5 0x075 /* bus region register 5 high */
207#define ebiu0_brcrh6 0x076 /* bus region register 6 high */
208#define ebiu0_brcrh7 0x077 /* bus region register 7 high */
209#define ebiu0_brcr0 0x080 /* bus region register 0 */
210#define ebiu0_brcr1 0x081 /* bus region register 1 */
211#define ebiu0_brcr2 0x082 /* bus region register 2 */
212#define ebiu0_brcr3 0x083 /* bus region register 3 */
213#define ebiu0_brcr4 0x084 /* bus region register 4 */
214#define ebiu0_brcr5 0x085 /* bus region register 5 */
215#define ebiu0_brcr6 0x086 /* bus region register 6 */
216#define ebiu0_brcr7 0x087 /* bus region register 7 */
217#define ebiu0_bear 0x090 /* bus error address register */
218#define ebiu0_besr 0x091 /* bus error syndrome reg */
219#define ebiu0_besr0s 0x093 /* bus error syndrome reg */
220#define ebiu0_biucr 0x09a /* bus interface control reg */
221
222/*----------------------------------------------------------------------------+
223| OPB bridge.
224+----------------------------------------------------------------------------*/
225#define opbw0_gesr 0x0b0 /* error status reg */
226#define opbw0_gesrs 0x0b1 /* error status reg */
227#define opbw0_gear 0x0b2 /* error address reg */
228
229/*----------------------------------------------------------------------------+
230| DMA.
231+----------------------------------------------------------------------------*/
232#define dma0_cr0 0x0c0 /* DMA channel control reg 0 */
233#define dma0_ct0 0x0c1 /* DMA count register 0 */
234#define dma0_da0 0x0c2 /* DMA destination addr reg 0 */
235#define dma0_sa0 0x0c3 /* DMA source addr register 0 */
236#define dma0_cc0 0x0c4 /* DMA chained count 0 */
237#define dma0_cr1 0x0c8 /* DMA channel control reg 1 */
238#define dma0_ct1 0x0c9 /* DMA count register 1 */
239#define dma0_da1 0x0ca /* DMA destination addr reg 1 */
240#define dma0_sa1 0x0cb /* DMA source addr register 1 */
241#define dma0_cc1 0x0cc /* DMA chained count 1 */
242#define dma0_cr2 0x0d0 /* DMA channel control reg 2 */
243#define dma0_ct2 0x0d1 /* DMA count register 2 */
244#define dma0_da2 0x0d2 /* DMA destination addr reg 2 */
245#define dma0_sa2 0x0d3 /* DMA source addr register 2 */
246#define dma0_cc2 0x0d4 /* DMA chained count 2 */
247#define dma0_cr3 0x0d8 /* DMA channel control reg 3 */
248#define dma0_ct3 0x0d9 /* DMA count register 3 */
249#define dma0_da3 0x0da /* DMA destination addr reg 3 */
250#define dma0_sa3 0x0db /* DMA source addr register 3 */
251#define dma0_cc3 0x0dc /* DMA chained count 3 */
252#define dma0_sr 0x0e0 /* DMA status register */
253#define dma0_srs 0x0e1 /* DMA status register */
254#define dma0_s1 0x031 /* DMA select1 register */
255#define dma0_s2 0x032 /* DMA select2 register */
256
257/*---------------------------------------------------------------------------+
258| Clock and power management.
259+----------------------------------------------------------------------------*/
260#define cpm0_fr 0x102 /* force register */
261
262/*----------------------------------------------------------------------------+
263| Serial Clock Control.
264+----------------------------------------------------------------------------*/
265#define ser0_ccr 0x120 /* serial clock control register */
266
267/*----------------------------------------------------------------------------+
268| Audio Clock Control.
269+----------------------------------------------------------------------------*/
270#define aud0_apcr 0x121 /* audio clock ctrl register */
271
272/*----------------------------------------------------------------------------+
273| DENC.
274+----------------------------------------------------------------------------*/
275#define denc0_idr 0x130 /* DENC ID register */
276#define denc0_cr1 0x131 /* control register 1 */
277#define denc0_rr1 0x132 /* microvision 1 (reserved 1) */
278#define denc0_cr2 0x133 /* control register 2 */
279#define denc0_rr2 0x134 /* microvision 2 (reserved 2) */
280#define denc0_rr3 0x135 /* microvision 3 (reserved 3) */
281#define denc0_rr4 0x136 /* microvision 4 (reserved 4) */
282#define denc0_rr5 0x137 /* microvision 5 (reserved 5) */
283#define denc0_ccdr 0x138 /* closed caption data */
284#define denc0_cccr 0x139 /* closed caption control */
285#define denc0_trr 0x13A /* teletext request register */
286#define denc0_tosr 0x13B /* teletext odd field line se */
287#define denc0_tesr 0x13C /* teletext even field line s */
288#define denc0_rlsr 0x13D /* RGB rhift left register */
289#define denc0_vlsr 0x13E /* video level shift register */
290#define denc0_vsr 0x13F /* video scaling register */
291
292/*----------------------------------------------------------------------------+
293| Video decoder. Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
294+----------------------------------------------------------------------------*/
295#define vid0_ccntl 0x140 /* control decoder operation */
296#define vid0_cmode 0x141 /* video operational mode */
297#define vid0_sstc0 0x142 /* STC high order bits 31:0 */
298#define vid0_sstc1 0x143 /* STC low order bit 32 */
299#define vid0_spts0 0x144 /* PTS high order bits 31:0 */
300#define vid0_spts1 0x145 /* PTS low order bit 32 */
301#define vid0_fifo 0x146 /* FIFO data port */
302#define vid0_fifos 0x147 /* FIFO status */
303#define vid0_cmd 0x148 /* send command to decoder */
304#define vid0_cmdd 0x149 /* port for command params */
305#define vid0_cmdst 0x14A /* command status */
306#define vid0_cmdad 0x14B /* command address */
307#define vid0_procia 0x14C /* instruction store */
308#define vid0_procid 0x14D /* data port for I_Store */
309#define vid0_osdm 0x151 /* OSD mode control */
310#define vid0_hosti 0x152 /* base interrupt register */
311#define vid0_mask 0x153 /* interrupt mask register */
312#define vid0_dispm 0x154 /* operational mode for Disp */
313#define vid0_dispd 0x155 /* setting for 'Sync' delay */
314#define vid0_vbctl 0x156 /* VBI */
315#define vid0_ttxctl 0x157 /* teletext control */
316#define vid0_disptb 0x158 /* display left/top border */
317#define vid0_osdgla 0x159 /* Graphics plane link addr */
318#define vid0_osdila 0x15A /* Image plane link addr */
319#define vid0_rbthr 0x15B /* rate buffer threshold */
320#define vid0_osdcla 0x15C /* Cursor link addr */
321#define vid0_stcca 0x15D /* STC common address */
322#define vid0_ptsctl 0x15F /* PTS Control */
323#define vid0_wprot 0x165 /* write protect for I_Store */
324#define vid0_vcqa 0x167 /* video clip queued block Ad */
325#define vid0_vcql 0x168 /* video clip queued block Le */
326#define vid0_blksz 0x169 /* block size bytes for copy op */
327#define vid0_srcad 0x16a /* copy source address bits 6-31 */
328#define vid0_udbas 0x16B /* base mem add for user data */
329#define vid0_vbibas 0x16C /* base mem add for VBI 0/1 */
330#define vid0_osdibas 0x16D /* Image plane base address */
331#define vid0_osdgbas 0x16E /* Graphic plane base address */
332#define vid0_rbbase 0x16F /* base mem add for video buf */
333#define vid0_dramad 0x170 /* DRAM address */
334#define vid0_dramdt 0x171 /* data port for DRAM access */
335#define vid0_dramcs 0x172 /* DRAM command and statusa */
336#define vid0_vcwa 0x173 /* v clip work address */
337#define vid0_vcwl 0x174 /* v clip work length */
338#define vid0_mseg0 0x175 /* segment address 0 */
339#define vid0_mseg1 0x176 /* segment address 1 */
340#define vid0_mseg2 0x177 /* segment address 2 */
341#define vid0_mseg3 0x178 /* segment address 3 */
342#define vid0_fbbase 0x179 /* frame buffer base memory */
343#define vid0_osdcbas 0x17A /* Cursor base addr */
344#define vid0_lboxtb 0x17B /* top left border */
345#define vid0_trdly 0x17C /* transparency gate delay */
346#define vid0_sbord 0x17D /* left/top small pict. bord. */
347#define vid0_zoffs 0x17E /* hor/ver zoom window */
348#define vid0_rbsz 0x17F /* rate buffer size read */
349
350/*----------------------------------------------------------------------------+
351| Transport demultiplexer.
352+----------------------------------------------------------------------------*/
353#define xpt0_lr 0x180 /* demux location register */
354#define xpt0_data 0x181 /* demux data register */
355#define xpt0_ir 0x182 /* demux interrupt register */
356
357#define xpt0_config1 0x0000 /* configuration 1 */
358#define xpt0_control1 0x0001 /* control 1 */
359#define xpt0_festat 0x0002 /* Front-end status */
360#define xpt0_feimask 0x0003 /* Front_end interrupt Mask */
361#define xpt0_ocmcnfg 0x0004 /* OCM Address */
362#define xpt0_settapi 0x0005 /* Set TAP Interrupt */
363
364#define xpt0_pcrhi 0x0010 /* PCR High */
365#define xpt0_pcrlow 0x0011 /* PCR Low */
366#define xpt0_lstchi 0x0012 /* Latched STC High */
367#define xpt0_lstclow 0x0013 /* Latched STC Low */
368#define xpt0_stchi 0x0014 /* STC High */
369#define xpt0_stclow 0x0015 /* STC Low */
370#define xpt0_pwm 0x0016 /* PWM */
371#define xpt0_pcrstct 0x0017 /* PCR-STC Threshold */
372#define xpt0_pcrstcd 0x0018 /* PCR-STC Delta */
373#define xpt0_stccomp 0x0019 /* STC Compare */
374#define xpt0_stccmpd 0x001a /* STC Compare Disarm */
375
376#define xpt0_dsstat 0x0048 /* Descrambler Status */
377#define xpt0_dsimask 0x0049 /* Descrambler Interrupt Mask */
378
379#define xpt0_vcchng 0x01f0 /* Video Channel Change */
380#define xpt0_acchng 0x01f1 /* Audio Channel Change */
381#define xpt0_axenable 0x01fe /* Aux PID Enables */
382#define xpt0_pcrpid 0x01ff /* PCR PID */
383
384#define xpt0_config2 0x1000 /* Configuration 2 */
385#define xpt0_pbuflvl 0x1002 /* Packet Buffer Level */
386#define xpt0_intmask 0x1003 /* Interrupt Mask */
387#define xpt0_plbcnfg 0x1004 /* PLB Configuration */
388
389#define xpt0_qint 0x1010 /* Queues Interrupts */
390#define xpt0_qintmsk 0x1011 /* Queues Interrupts Mask */
391#define xpt0_astatus 0x1012 /* Audio Status */
392#define xpt0_aintmask 0x1013 /* Audio Interrupt Mask */
393#define xpt0_vstatus 0x1014 /* Video Status */
394#define xpt0_vintmask 0x1015 /* Video Interrupt Mask */
395
396#define xpt0_qbase 0x1020 /* Queue Base */
397#define xpt0_bucketq 0x1021 /* Bucket Queue */
398#define xpt0_qstops 0x1024 /* Queue Stops */
399#define xpt0_qresets 0x1025 /* Queue Resets */
400#define xpt0_sfchng 0x1026 /* Section Filter Change */
401
402/*----------------------------------------------------------------------------+
403| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status)
404+----------------------------------------------------------------------------*/
405#define aud0_ctrl0 0x1a0 /* control 0 */
406#define aud0_ctrl1 0x1a1 /* control 1 */
407#define aud0_ctrl2 0x1a2 /* control 2 */
408#define aud0_cmd 0x1a3 /* command register */
409#define aud0_isr 0x1a4 /* interrupt status register */
410#define aud0_imr 0x1a5 /* interrupt mask register */
411#define aud0_dsr 0x1a6 /* decoder status register */
412#define aud0_stc 0x1a7 /* system time clock */
413#define aud0_csr 0x1a8 /* channel status register */
414#define aud0_lcnt 0x1a9 /* queued address register 2 */
415#define aud0_pts 0x1aa /* presentation time stamp */
416#define aud0_tgctrl 0x1ab /* tone generation control */
417#define aud0_qlr2 0x1ac /* queued length register 2 */
418#define aud0_auxd 0x1ad /* aux data */
419#define aud0_strmid 0x1ae /* stream ID */
420#define aud0_qar 0x1af /* queued address register */
421#define aud0_dsps 0x1b0 /* DSP status */
422#define aud0_qlr 0x1b1 /* queued len address */
423#define aud0_dspc 0x1b2 /* DSP control */
424#define aud0_wlr2 0x1b3 /* working length register 2 */
425#define aud0_instd 0x1b4 /* instruction download */
426#define aud0_war 0x1b5 /* working address register */
427#define aud0_seg1 0x1b6 /* segment 1 base register */
428#define aud0_seg2 0x1b7 /* segment 2 base register */
429#define aud0_avf 0x1b9 /* audio att value front */
430#define aud0_avr 0x1ba /* audio att value rear */
431#define aud0_avc 0x1bb /* audio att value center */
432#define aud0_seg3 0x1bc /* segment 3 base register */
433#define aud0_offset 0x1bd /* offset address */
434#define aud0_wrl 0x1be /* working length register */
435#define aud0_war2 0x1bf /* working address register 2 */
436
437/*----------------------------------------------------------------------------+
438| High speed memory controller 0 and 1.
439+----------------------------------------------------------------------------*/
440#define hsmc0_gr 0x1e0 /* HSMC global register */
441#define hsmc0_besr 0x1e1 /* bus error status register */
442#define hsmc0_bear 0x1e2 /* bus error address register */
443#define hsmc0_br0 0x1e4 /* SDRAM sub-ctrl bank reg 0 */
444#define hsmc0_cr0 0x1e5 /* SDRAM sub-ctrl ctrl reg 0 */
445#define hsmc0_br1 0x1e7 /* SDRAM sub-ctrl bank reg 1 */
446#define hsmc0_cr1 0x1e8 /* SDRAM sub-ctrl ctrl reg 1 */
447#define hsmc0_sysr 0x1f1 /* system register */
448#define hsmc0_data 0x1f2 /* data register */
449#define hsmc0_crr 0x1f3 /* refresh register */
450
451#define hsmc1_gr 0x1c0 /* HSMC global register */
452#define hsmc1_besr 0x1c1 /* bus error status register */
453#define hsmc1_bear 0x1c2 /* bus error address register */
454#define hsmc1_br0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */
455#define hsmc1_cr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */
456#define hsmc1_br1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */
457#define hsmc1_cr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */
458#define hsmc1_sysr 0x1d1 /* system register */
459#define hsmc1_data 0x1d2 /* data register */
460#define hsmc1_crr 0x1d3 /* refresh register */
461
462/*----------------------------------------------------------------------------+
463| Machine State Register bit definitions.
464+----------------------------------------------------------------------------*/
465#define msr_ape 0x00100000
466#define msr_apa 0x00080000
467#define msr_we 0x00040000
468#define msr_ce 0x00020000
469#define msr_ile 0x00010000
470#define msr_ee 0x00008000
471#define msr_pr 0x00004000
472#define msr_me 0x00001000
473#define msr_de 0x00000200
474#define msr_ir 0x00000020
475#define msr_dr 0x00000010
476#define msr_le 0x00000001
477
478/*----------------------------------------------------------------------------+
479| Used during interrupt processing.
480+----------------------------------------------------------------------------*/
481#define stack_reg_image_size 160
482
483/*----------------------------------------------------------------------------+
484| Function prolog definition and other Metaware (EABI) defines.
485+----------------------------------------------------------------------------*/
486#ifdef MW
487
488#define r0 0
489#define r1 1
490#define r2 2
491#define r3 3
492#define r4 4
493#define r5 5
494#define r6 6
495#define r7 7
496#define r8 8
497#define r9 9
498#define r10 10
499#define r11 11
500#define r12 12
501#define r13 13
502#define r14 14
503#define r15 15
504#define r16 16
505#define r17 17
506#define r18 18
507#define r19 19
508#define r20 20
509#define r21 21
510#define r22 22
511#define r23 23
512#define r24 24
513#define r25 25
514#define r26 26
515#define r27 27
516#define r28 28
517#define r29 29
518#define r30 30
519#define r31 31
520
521#define cr0 0
522#define cr1 1
523#define cr2 2
524#define cr3 3
525#define cr4 4
526#define cr5 5
527#define cr6 6
528#define cr7 7
529
530#define function_prolog(func_name) .text; \
531 .align 2; \
532 .globl func_name; \
533 func_name:
534#define function_epilog(func_name) .type func_name,@function; \
535 .size func_name,.-func_name
536
537#define function_call(func_name) bl func_name
538
539#define stack_frame_min 8
540#define stack_frame_bc 0
541#define stack_frame_lr 4
542#define stack_neg_off 0
543
544#endif
545
546/*----------------------------------------------------------------------------+
547| Function prolog definition and other DIAB (Elf) defines.
548+----------------------------------------------------------------------------*/
549#ifdef ELF_DIAB
550
551fprolog: macro f_name
552 .text
553 .align 2
554 .globl f_name
555f_name:
556 endm
557
558fepilog: macro f_name
559 .type f_name,@function
560 .size f_name,.-f_name
561 endm
562
563#define function_prolog(func_name) fprolog func_name
564#define function_epilog(func_name) fepilog func_name
565#define function_call(func_name) bl func_name
566
567#define stack_frame_min 8
568#define stack_frame_bc 0
569#define stack_frame_lr 4
570#define stack_neg_off 0
571
572#endif
573
574/*----------------------------------------------------------------------------+
575| Function prolog definition and other Xlc (XCOFF) defines.
576+----------------------------------------------------------------------------*/
577#ifdef XCOFF
578
579.machine "403ga"
580
581#define r0 0
582#define r1 1
583#define r2 2
584#define r3 3
585#define r4 4
586#define r5 5
587#define r6 6
588#define r7 7
589#define r8 8
590#define r9 9
591#define r10 10
592#define r11 11
593#define r12 12
594#define r13 13
595#define r14 14
596#define r15 15
597#define r16 16
598#define r17 17
599#define r18 18
600#define r19 19
601#define r20 20
602#define r21 21
603#define r22 22
604#define r23 23
605#define r24 24
606#define r25 25
607#define r26 26
608#define r27 27
609#define r28 28
610#define r29 29
611#define r30 30
612#define r31 31
613
614#define cr0 0
615#define cr1 1
616#define cr2 2
617#define cr3 3
618#define cr4 4
619#define cr5 5
620#define cr6 6
621#define cr7 7
622
623#define function_prolog(func_name) .csect .func_name[PR]; \
624 .globl .func_name[PR]; \
625 func_name:
626
627#define function_epilog(func_name) .toc; \
628 .csect func_name[DS]; \
629 .globl func_name[DS]; \
630 .long .func_name[PR]; \
631 .long TOC[tc0]
632
633#define function_call(func_name) .extern .func_name[PR]; \
634 stw r2,stack_frame_toc(r1); \
635 mfspr r2,sprg0; \
636 bl .func_name[PR]; \
637 lwz r2,stack_frame_toc(r1)
638
639#define stack_frame_min 56
640#define stack_frame_bc 0
641#define stack_frame_lr 8
642#define stack_frame_toc 20
643#define stack_neg_off 276
644
645#endif
646#define function_prolog(func_name) .text; \
647 .align 2; \
648 .globl func_name; \
649 func_name:
650#define function_epilog(func_name) .type func_name,@function; \
651 .size func_name,.-func_name
652
653#define function_call(func_name) bl func_name
654
655/*----------------------------------------------------------------------------+
656| Function prolog definition for GNU
657+----------------------------------------------------------------------------*/
658#ifdef _GNU_TOOL
659
660#define function_prolog(func_name) .globl func_name; \
661 func_name:
662#define function_epilog(func_name)
663
664#endif
diff --git a/arch/ppc/boot/simple/rw4/rw4_init.S b/arch/ppc/boot/simple/rw4/rw4_init.S
deleted file mode 100644
index b1061962e46b..000000000000
--- a/arch/ppc/boot/simple/rw4/rw4_init.S
+++ /dev/null
@@ -1,78 +0,0 @@
1#define VESTA
2#include "ppc_40x.h"
3#
4 .align 2
5 .text
6#
7# added by linguohui
8 .extern initb_ebiu0, initb_config, hdw_init_finish
9 .extern initb_hsmc0, initb_hsmc1, initb_cache
10# end added
11 .globl HdwInit
12#
13HdwInit:
14#
15#-----------------------------------------------------------------------*
16# If we are not executing from the FLASH get out *
17#-----------------------------------------------------------------------*
18# SAW keep this or comment out a la Hawthorne?
19# r3 contains NIP when used with Linux
20# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address
21# cmpwi r28, 0xff
22# bne locn01
23#
24#
25#------------------------------------------------------------------------
26# Init_cpu. Bank registers are setup for the IBM STB.
27#------------------------------------------------------------------------
28#
29# Setup processor core clock to be driven off chip. This is GPI4 bit
30# twenty. Setup Open Drain, Output Select, Three-State Control, and
31# Three-State Select registers.
32#
33
34
35 pb0pesr = 0x054
36 pb0pear = 0x056
37
38 mflr r30
39
40#-----------------------------------------------------------------------------
41# Vectors will be at 0x1F000000
42# Dummy Machine check handler just does RFI before true handler gets installed
43#-----------------------------------------------------------------------------
44#if 1 /* xuwentao added*/
45#ifdef SDRAM16MB
46 lis r10,0x0000
47 addi r10,r10,0x0000
48#else
49 lis r10,0x1F00
50 addi r10,r10,0x0000
51#endif
52
53 mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending
54 isync # on SDRAM memory model used.
55
56 lis r10,0xFFFF # clear PB0_PESR because some
57 ori r10,r10,0xFFFF # transitions from flash,changed by linguohui
58 mtdcr pb0pesr,r10 # to load RAM image via RiscWatch
59 lis r10,0x0000 # cause PB0_PESR machine checks
60 mtdcr pb0pear,r10
61 addis r10,r10,0x0000 # clear the
62 mtxer r10 # XER just in case...
63#endif /* xuwentao*/
64
65 bl initb_ebiu0 # init EBIU
66
67 bl initb_config # config PPC and board
68
69
70
71
72#------------------------------------------------------------------------
73# EVPR setup moved to top of this function.
74#------------------------------------------------------------------------
75#
76 mtlr r30
77 blr
78 .end
diff --git a/arch/ppc/boot/simple/rw4/rw4_init_brd.S b/arch/ppc/boot/simple/rw4/rw4_init_brd.S
deleted file mode 100644
index 386afdaad6c7..000000000000
--- a/arch/ppc/boot/simple/rw4/rw4_init_brd.S
+++ /dev/null
@@ -1,1125 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1997
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Tony J. Cerreto
22| Component: BSPS
23| File: init_brd.s
24| Purpose: Vesta Evaluation Board initialization subroutines. The following
25| routines are available:
26| 1. INITB_EBIU0: Initialize EBIU0.
27| 2. INITB_CONFIG: Configure board.
28| 3. INITB_HSMC0: Initialize HSMC0 (SDRAM).
29| 4. INITB_HSMC1: Initialize HSMC1 (SDRAM).
30| 5. INITB_CACHE: Initialize Data and Instruction Cache.
31| 6. INITB_DCACHE: Initialize Data Cache.
32| 7. INITB_ICACHE: Initialize Instruction Cache.
33| 8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed)
34|
35| Changes:
36| Date: Author Comment:
37| --------- ------ --------
38| 01-Mar-00 tjc Created
39| 04-Mar-00 jfh Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28)
40| 04-Mar-00 jfh Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28)
41| 04-Mar-00 jfh Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28)
42| 04-Mar-00 jfh Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28)
43| 19-May-00 rlb Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous
44| SDRAM space. Changed cache ctl regs to reflect this.
45| 22-May-00 tjc Changed initb_get_cspd interface and eliminated
46| initb_get_bspd routines.
47| 26-May-00 tjc Added two nop instructions after all mtxxx/mfxxx
48| instructions due to PPC405 bug.
49+----------------------------------------------------------------------------*/
50#define VESTA
51#include "ppc_40x.h"
52#include "stb.h"
53
54/*----------------------------------------------------------------------------+
55| BOARD CONFIGURATION DEFINES
56+----------------------------------------------------------------------------*/
57#define CBS0_CR_VAL 0x00000002 /* CBS control reg value */
58#define CIC0_CR_VAL 0xD0800448 /* CIC control reg value */
59#define CIC0_SEL3_VAL 0x11500000 /* CIC select 3 reg value */
60#define CIC0_VCR_VAL 0x00631700 /* CIC video cntl reg value */
61
62/*----------------------------------------------------------------------------+
63| EBIU0 BANK REGISTERS DEFINES
64+----------------------------------------------------------------------------*/
65#define EBIU0_BRCRH0_VAL 0x00000000 /* BR High 0 (Extension Reg)*/
66#define EBIU0_BRCRH1_VAL 0x00000000 /* BR High 1 (Extension Reg)*/
67#define EBIU0_BRCRH2_VAL 0x40000000 /* BR High 2 (Extension Reg)*/
68#define EBIU0_BRCRH3_VAL 0x40000000 /* BR High 3 (Extension Reg)*/
69#define EBIU0_BRCRH4_VAL 0x00000000 /* BR High 4 (Extension Reg)*/
70#define EBIU0_BRCRH5_VAL 0x00000000 /* BR High 5 (Extension Reg)*/
71#define EBIU0_BRCRH6_VAL 0x00000000 /* BR High 6 (Extension Reg)*/
72#define EBIU0_BRCRH7_VAL 0x40000000 /* BR High 7 (Extension Reg)*/
73
74#define EBIU0_BRCR0_VAL 0xFC58BFFE /* BR 0: 16 bit Flash 4 MB */
75#define EBIU0_BRCR1_VAL 0xFF00BFFE /* BR 1: Ext Connector 1 MB */
76#if 1
77#define EBIU0_BRCR2_VAL 0x207CFFBE /* BR 2: Xilinx 8 MB */
78 /* twt == 0x3f */
79#else
80#define EBIU0_BRCR2_VAL 0x207CCFBE /* BR 2: Xilinx 8 MB */
81 /* twt == 0x0f */
82#endif
83#define EBIU0_BRCR3_VAL 0x407CBFBE /* BR 3: IDE Drive 8 MB */
84#define EBIU0_BRCR4_VAL 0xFF00BFFF /* BR 4: Disabled. 0 MB */
85#define EBIU0_BRCR5_VAL 0xFF00BFFF /* BR 5: Disabled. 0 MB */
86#define EBIU0_BRCR6_VAL 0xFF00BFFF /* BR 6: Disabled. 0 MB */
87#define EBIU0_BRCR7_VAL 0xCE3F0003 /* BR 7: Line Mode DMA 2 MB */
88
89/*----------------------------------------------------------------------------+
90| GPIO DEFINES
91+----------------------------------------------------------------------------*/
92#define STB_GPIO0_OUTPUT (STB_GPIO0_BASE_ADDRESS+ 0x00)
93#define STB_GPIO0_TC (STB_GPIO0_BASE_ADDRESS+ 0x04)
94#define STB_GPIO0_OS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x08)
95#define STB_GPIO0_OS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x0C)
96#define STB_GPIO0_TS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x10)
97#define STB_GPIO0_TS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x14)
98#define STB_GPIO0_OD (STB_GPIO0_BASE_ADDRESS+ 0x18)
99#define STB_GPIO0_INPUT (STB_GPIO0_BASE_ADDRESS+ 0x1C)
100#define STB_GPIO0_R1 (STB_GPIO0_BASE_ADDRESS+ 0x20)
101#define STB_GPIO0_R2 (STB_GPIO0_BASE_ADDRESS+ 0x24)
102#define STB_GPIO0_R3 (STB_GPIO0_BASE_ADDRESS+ 0x28)
103#define STB_GPIO0_IS_1_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x30)
104#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34)
105#define STB_GPIO0_IS_2_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x38)
106#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C)
107#define STB_GPIO0_IS_3_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x40)
108#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44)
109#define STB_GPIO0_SS_1 (STB_GPIO0_BASE_ADDRESS+ 0x50)
110#define STB_GPIO0_SS_2 (STB_GPIO0_BASE_ADDRESS+ 0x54)
111#define STB_GPIO0_SS_3 (STB_GPIO0_BASE_ADDRESS+ 0x58)
112
113#define GPIO0_TC_VAL 0x0C020004 /* three-state control val */
114#define GPIO0_OS_0_31_VAL 0x51A00004 /* output select 0-31 val */
115#define GPIO0_OS_32_63_VAL 0x0000002F /* output select 32-63 val */
116#define GPIO0_TS_0_31_VAL 0x51A00000 /* three-state sel 0-31 val*/
117#define GPIO0_TS_32_63_VAL 0x0000000F /* three-state sel 32-63 val*/
118#define GPIO0_OD_VAL 0xC0000004 /* open drain val */
119#define GPIO0_IS_1_0_31_VAL 0x50000151 /* input select 1 0-31 val */
120#define GPIO0_IS_1_32_63_VAL 0x00000000 /* input select 1 32-63 val */
121#define GPIO0_IS_2_0_31_VAL 0x00000000 /* input select 2 0-31 val */
122#define GPIO0_IS_2_32_63_VAL 0x00000000 /* input select 2 32-63 val */
123#define GPIO0_IS_3_0_31_VAL 0x00000440 /* input select 3 0-31 val */
124#define GPIO0_IS_3_32_63_VAL 0x00000000 /* input select 3 32-63 val */
125#define GPIO0_SS_1_VAL 0x00000000 /* sync select 1 val */
126#define GPIO0_SS_2_VAL 0x00000000 /* sync select 2 val */
127#define GPIO0_SS_3_VAL 0x00000000 /* sync select 3 val */
128
129/*----------------------------------------------------------------------------+
130| XILINX DEFINES
131+----------------------------------------------------------------------------*/
132#define STB_XILINX_LED (STB_FPGA_BASE_ADDRESS+ 0x0100)
133#define STB_XILINX1_REG0 (STB_FPGA_BASE_ADDRESS+ 0x40000)
134#define STB_XILINX1_REG1 (STB_FPGA_BASE_ADDRESS+ 0x40002)
135#define STB_XILINX1_REG2 (STB_FPGA_BASE_ADDRESS+ 0x40004)
136#define STB_XILINX1_REG3 (STB_FPGA_BASE_ADDRESS+ 0x40006)
137#define STB_XILINX1_REG4 (STB_FPGA_BASE_ADDRESS+ 0x40008)
138#define STB_XILINX1_REG5 (STB_FPGA_BASE_ADDRESS+ 0x4000A)
139#define STB_XILINX1_REG6 (STB_FPGA_BASE_ADDRESS+ 0x4000C)
140#define STB_XILINX1_ID (STB_FPGA_BASE_ADDRESS+ 0x4000E)
141#define STB_XILINX1_FLUSH (STB_FPGA_BASE_ADDRESS+ 0x4000E)
142#define STB_XILINX2_REG0 (STB_FPGA_BASE_ADDRESS+ 0x80000)
143#define STB_XILINX2_REG1 (STB_FPGA_BASE_ADDRESS+ 0x80002)
144#define STB_XILINX2_REG2 (STB_FPGA_BASE_ADDRESS+ 0x80004)
145
146#define XILINX1_R0_VAL 0x2440 /* Xilinx 1 Register 0 Val */
147#define XILINX1_R1_VAL 0x0025 /* Xilinx 1 Register 1 Val */
148#define XILINX1_R2_VAL 0x0441 /* Xilinx 1 Register 2 Val */
149#define XILINX1_R3_VAL 0x0008 /* Xilinx 1 Register 3 Val */
150#define XILINX1_R4_VAL 0x0100 /* Xilinx 1 Register 4 Val */
151#define XILINX1_R5_VAL 0x6810 /* Xilinx 1 Register 5 Val */
152#define XILINX1_R6_VAL 0x0000 /* Xilinx 1 Register 6 Val */
153#if 0
154#define XILINX2_R0_VAL 0x0008 /* Xilinx 2 Register 0 Val */
155#define XILINX2_R1_VAL 0x0000 /* Xilinx 2 Register 1 Val */
156#else
157#define XILINX2_R0_VAL 0x0018 /* disable IBM IrDA RxD */
158#define XILINX2_R1_VAL 0x0008 /* enable SICC MAX chip */
159#endif
160#define XILINX2_R2_VAL 0x0000 /* Xilinx 2 Register 2 Val */
161
162/*----------------------------------------------------------------------------+
163| HSMC BANK REGISTERS DEFINES
164+----------------------------------------------------------------------------*/
165#ifdef SDRAM16MB
166#define HSMC0_BR0_VAL 0x000D2D55 /* 0x1F000000-007FFFFF R/W */
167#define HSMC0_BR1_VAL 0x008D2D55 /* 0x1F800000-1FFFFFFF R/W */
168#else
169#define HSMC0_BR0_VAL 0x1F0D2D55 /* 0x1F000000-007FFFFF R/W */
170#define HSMC0_BR1_VAL 0x1F8D2D55 /* 0x1F800000-1FFFFFFF R/W */
171#endif
172#define HSMC1_BR0_VAL 0xA00D2D55 /* 0xA0000000-A07FFFFF R/W */
173#define HSMC1_BR1_VAL 0xA08D2D55 /* 0xA0800000-A0FFFFFF R/W */
174
175/*----------------------------------------------------------------------------+
176| CACHE DEFINES
177+----------------------------------------------------------------------------*/
178#define DCACHE_NLINES 128 /* no. D-cache lines */
179#define DCACHE_NBYTES 32 /* no. bytes/ D-cache line */
180#define ICACHE_NLINES 256 /* no. I-cache lines */
181#define ICACHE_NBYTES 32 /* no. bytes/ I-cache line */
182#ifdef SDRAM16MB
183#define DCACHE_ENABLE 0x80000000 /* D-cache regions to enable*/
184#define ICACHE_ENABLE 0x80000001 /* I-cache regions to enable*/
185#else
186#define DCACHE_ENABLE 0x18000000 /* D-cache regions to enable*/
187#define ICACHE_ENABLE 0x18000001 /* I-cache regions to enable*/
188#endif
189
190/*----------------------------------------------------------------------------+
191| CPU CORE SPEED CALCULATION DEFINES
192+----------------------------------------------------------------------------*/
193#define GCS_LCNT 500000 /* CPU speed loop count */
194#define GCS_TROW_BYTES 8 /* no. bytes in table row */
195#define GCS_CTICK_TOL 100 /* allowable clock tick tol */
196#define GCS_NMULT 4 /* no. of core speed mults */
197
198 /*--------------------------------------------------------------------+
199 | No. 13.5Mhz
200 | Clock Ticks
201 | based on a
202 | loop count Bus
203 | of 100,000 Speed
204 +--------------------------------------------------------------------*/
205gcs_lookup_table:
206 .int 50000, 54000000 /* 54.0 Mhz */
207 .int 66667, 40500000 /* 40.5 Mhz */
208 .int 54545, 49500000 /* 49.5 Mhz */
209 .int 46154, 58500000 /* 58.5 Mhz */
210 .int 0, 0 /* end of table flag */
211
212
213/*****************************************************************************+
214| XXXXXXX XXX XXX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX
215| XX X XX XX X XX X XX X XX XX XXX XX XXXX XX
216| XX X XXX XX XX X XX XX XXXX XX XX XX XX
217| XXXX X XX XXXX XXXXX XX XXXX XX XX XX
218| XX X XXX XX XX X XX XX XX XXX XXXXXX XX
219| XX X XX XX XX XX X XX XX XX XX XX XX XX XX
220| XXXXXXX XXX XXX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX
221+*****************************************************************************/
222/******************************************************************************
223|
224| Routine: INITB_EBIU0.
225|
226| Purpose: Initialize all the EBIU0 Bank Registers
227| Parameters: None.
228| Returns: None.
229|
230******************************************************************************/
231 function_prolog(initb_ebiu0)
232 /*--------------------------------------------------------------------+
233 | Set EBIU0 Bank 0
234 +--------------------------------------------------------------------*/
235 lis r10,EBIU0_BRCR0_VAL@h
236 ori r10,r10,EBIU0_BRCR0_VAL@l
237 mtdcr ebiu0_brcr0,r10
238 lis r10,EBIU0_BRCRH0_VAL@h
239 ori r10,r10,EBIU0_BRCRH0_VAL@l
240 mtdcr ebiu0_brcrh0,r10
241
242 /*--------------------------------------------------------------------+
243 | Set EBIU0 Bank 1
244 +--------------------------------------------------------------------*/
245 lis r10,EBIU0_BRCR1_VAL@h
246 ori r10,r10,EBIU0_BRCR1_VAL@l
247 mtdcr ebiu0_brcr1,r10
248 lis r10,EBIU0_BRCRH1_VAL@h
249 ori r10,r10,EBIU0_BRCRH1_VAL@l
250 mtdcr ebiu0_brcrh1,r10
251
252 /*--------------------------------------------------------------------+
253 | Set EBIU0 Bank 2
254 +--------------------------------------------------------------------*/
255 lis r10,EBIU0_BRCR2_VAL@h
256 ori r10,r10,EBIU0_BRCR2_VAL@l
257 mtdcr ebiu0_brcr2,r10
258 lis r10,EBIU0_BRCRH2_VAL@h
259 ori r10,r10,EBIU0_BRCRH2_VAL@l
260 mtdcr ebiu0_brcrh2,r10
261
262 /*--------------------------------------------------------------------+
263 | Set EBIU0 Bank 3
264 +--------------------------------------------------------------------*/
265 lis r10,EBIU0_BRCR3_VAL@h
266 ori r10,r10,EBIU0_BRCR3_VAL@l
267 mtdcr ebiu0_brcr3,r10
268 lis r10,EBIU0_BRCRH3_VAL@h
269 ori r10,r10,EBIU0_BRCRH3_VAL@l
270 mtdcr ebiu0_brcrh3,r10
271
272 /*--------------------------------------------------------------------+
273 | Set EBIU0 Bank 4
274 +--------------------------------------------------------------------*/
275 lis r10,EBIU0_BRCR4_VAL@h
276 ori r10,r10,EBIU0_BRCR4_VAL@l
277 mtdcr ebiu0_brcr4,r10
278 lis r10,EBIU0_BRCRH4_VAL@h
279 ori r10,r10,EBIU0_BRCRH4_VAL@l
280 mtdcr ebiu0_brcrh4,r10
281
282 /*--------------------------------------------------------------------+
283 | Set EBIU0 Bank 5
284 +--------------------------------------------------------------------*/
285 lis r10,EBIU0_BRCR5_VAL@h
286 ori r10,r10,EBIU0_BRCR5_VAL@l
287 mtdcr ebiu0_brcr5,r10
288 lis r10,EBIU0_BRCRH5_VAL@h
289 ori r10,r10,EBIU0_BRCRH5_VAL@l
290 mtdcr ebiu0_brcrh5,r10
291
292 /*--------------------------------------------------------------------+
293 | Set EBIU0 Bank 6
294 +--------------------------------------------------------------------*/
295 lis r10,EBIU0_BRCR6_VAL@h
296 ori r10,r10,EBIU0_BRCR6_VAL@l
297 mtdcr ebiu0_brcr6,r10
298 lis r10,EBIU0_BRCRH6_VAL@h
299 ori r10,r10,EBIU0_BRCRH6_VAL@l
300 mtdcr ebiu0_brcrh6,r10
301
302 /*--------------------------------------------------------------------+
303 | Set EBIU0 Bank 7
304 +--------------------------------------------------------------------*/
305 lis r10,EBIU0_BRCR7_VAL@h
306 ori r10,r10,EBIU0_BRCR7_VAL@l
307 mtdcr ebiu0_brcr7,r10
308 lis r10,EBIU0_BRCRH7_VAL@h
309 ori r10,r10,EBIU0_BRCRH7_VAL@l
310 mtdcr ebiu0_brcrh7,r10
311
312 blr
313 function_epilog(initb_ebiu0)
314
315
316/******************************************************************************
317|
318| Routine: INITB_CONFIG
319|
320| Purpose: Configure the Vesta Evaluation Board. The following items
321| will be configured:
322| 1. Cross-Bar Switch.
323| 2. Chip Interconnect.
324| 3. Clear/reset key PPC registers.
325| 4. Xilinx and GPIO Registers.
326|
327| Returns: None.
328|
329******************************************************************************/
330 function_prolog(initb_config)
331 /*--------------------------------------------------------------------+
332 | Init CROSS-BAR SWITCH
333 +--------------------------------------------------------------------*/
334 lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */
335 ori r10,r10,CBS0_CR_VAL@l
336 mtdcr cbs0_cr,r10
337
338 /*--------------------------------------------------------------------+
339 | Init Chip-Interconnect (CIC) Registers
340 +--------------------------------------------------------------------*/
341 lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */
342 ori r10,r10,CIC0_CR_VAL@l
343 mtdcr cic0_cr,r10
344
345 lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */
346 ori r10,r10,CIC0_SEL3_VAL@l
347 mtdcr cic0_sel3,r10
348
349 lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */
350 ori r10,r10,CIC0_VCR_VAL@l
351 mtdcr cic0_vcr,r10
352
353 /*--------------------------------------------------------------------+
354 | Clear SGR and DCWR
355 +--------------------------------------------------------------------*/
356 li r10,0x0000
357 mtspr sgr,r10
358 mtspr dcwr,r10
359
360 /*--------------------------------------------------------------------+
361 | Clear/set up some machine state registers.
362 +--------------------------------------------------------------------*/
363 li r10,0x0000 /* r10 <- 0 */
364 mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */
365 mtspr esr,r10 /* clr Exceptn Syndrome Reg */
366 mttcr r10 /* timer control register */
367
368 mtdcr uic0_er,r10 /* disable all interrupts */
369
370 /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */
371 lis r10, 0x00600e00@h
372 ori r10,r10,0x00600e00@l
373 mtdcr uic0_pr,r10
374
375 li r10,0x00000020 /* UIC_EIR1 */
376 mtdcr uic0_tr,r10
377
378 lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */
379 ori r10,r10,0xFFFF /* */
380 mtdbsr r10 /* clear/reset the dbsr */
381 mtdcr uic0_sr,r10 /* clear pending interrupts */
382
383 li r10,0x1000 /* set Machine Exception bit*/
384 oris r10,r10,0x2 /* set Criticl Exception bit*/
385 mtmsr r10 /* change MSR */
386
387 /*--------------------------------------------------------------------+
388 | Clear XER.
389 +--------------------------------------------------------------------*/
390 li r10,0x0000
391 mtxer r10
392
393 /*--------------------------------------------------------------------+
394 | Init GPIO0 Registers
395 +--------------------------------------------------------------------*/
396 lis r10, STB_GPIO0_TC@h /* Three-state control */
397 ori r10,r10,STB_GPIO0_TC@l
398 lis r11, GPIO0_TC_VAL@h
399 ori r11,r11,GPIO0_TC_VAL@l
400 stw r11,0(r10)
401
402 lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */
403 ori r10,r10,STB_GPIO0_OS_0_31@l
404 lis r11, GPIO0_OS_0_31_VAL@h
405 ori r11,r11,GPIO0_OS_0_31_VAL@l
406 stw r11,0(r10)
407
408 lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */
409 ori r10,r10,STB_GPIO0_OS_32_63@l
410 lis r11, GPIO0_OS_32_63_VAL@h
411 ori r11,r11,GPIO0_OS_32_63_VAL@l
412 stw r11,0(r10)
413
414 lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */
415 ori r10,r10,STB_GPIO0_TS_0_31@l
416 lis r11, GPIO0_TS_0_31_VAL@h
417 ori r11,r11,GPIO0_TS_0_31_VAL@l
418 stw r11,0(r10)
419
420 lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */
421 ori r10,r10,STB_GPIO0_TS_32_63@l
422 lis r11, GPIO0_TS_32_63_VAL@h
423 ori r11,r11,GPIO0_TS_32_63_VAL@l
424 stw r11,0(r10)
425
426 lis r10, STB_GPIO0_OD@h /* open drain */
427 ori r10,r10,STB_GPIO0_OD@l
428 lis r11, GPIO0_OD_VAL@h
429 ori r11,r11,GPIO0_OD_VAL@l
430 stw r11,0(r10)
431
432 lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */
433 ori r10,r10,STB_GPIO0_IS_1_0_31@l
434 lis r11, GPIO0_IS_1_0_31_VAL@h
435 ori r11,r11,GPIO0_IS_1_0_31_VAL@l
436 stw r11,0(r10)
437
438 lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */
439 ori r10,r10,STB_GPIO0_IS_1_32_63@l
440 lis r11, GPIO0_IS_1_32_63_VAL@h
441 ori r11,r11,GPIO0_IS_1_32_63_VAL@l
442 stw r11,0(r10)
443
444 lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */
445 ori r10,r10,STB_GPIO0_IS_2_0_31@l
446 lis r11, GPIO0_IS_2_0_31_VAL@h
447 ori r11,r11,GPIO0_IS_2_0_31_VAL@l
448 stw r11,0(r10)
449
450 lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */
451 ori r10,r10,STB_GPIO0_IS_2_32_63@l
452 lis r11, GPIO0_IS_2_32_63_VAL@h
453 ori r11,r11,GPIO0_IS_2_32_63_VAL@l
454 stw r11,0(r10)
455
456 lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */
457 ori r10,r10,STB_GPIO0_IS_3_0_31@l
458 lis r11, GPIO0_IS_3_0_31_VAL@h
459 ori r11,r11,GPIO0_IS_3_0_31_VAL@l
460 stw r11,0(r10)
461
462 lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */
463 ori r10,r10,STB_GPIO0_IS_3_32_63@l
464 lis r11, GPIO0_IS_3_32_63_VAL@h
465 ori r11,r11,GPIO0_IS_3_32_63_VAL@l
466 stw r11,0(r10)
467
468 lis r10, STB_GPIO0_SS_1@h /* sync select 1 */
469 ori r10,r10,STB_GPIO0_SS_1@l
470 lis r11, GPIO0_SS_1_VAL@h
471 ori r11,r11,GPIO0_SS_1_VAL@l
472 stw r11,0(r10)
473
474 lis r10, STB_GPIO0_SS_2@h /* sync select 2 */
475 ori r10,r10,STB_GPIO0_SS_2@l
476 lis r11, GPIO0_SS_2_VAL@h
477 ori r11,r11,GPIO0_SS_2_VAL@l
478 stw r11,0(r10)
479
480 lis r10, STB_GPIO0_SS_3@h /* sync select 3 */
481 ori r10,r10,STB_GPIO0_SS_3@l
482 lis r11, GPIO0_SS_3_VAL@h
483 ori r11,r11,GPIO0_SS_3_VAL@l
484 stw r11,0(r10)
485
486 /*--------------------------------------------------------------------+
487 | Init Xilinx #1 Registers
488 +--------------------------------------------------------------------*/
489 lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */
490 ori r10,r10,STB_XILINX1_REG0@l
491 li r11,XILINX1_R0_VAL
492 sth r11,0(r10)
493
494 lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */
495 ori r10,r10,STB_XILINX1_REG1@l
496 li r11,XILINX1_R1_VAL
497 sth r11,0(r10)
498
499 lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */
500 ori r10,r10,STB_XILINX1_REG2@l
501 li r11,XILINX1_R2_VAL
502 sth r11,0(r10)
503
504 lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */
505 ori r10,r10,STB_XILINX1_REG3@l
506 li r11,XILINX1_R3_VAL
507 sth r11,0(r10)
508
509 lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */
510 ori r10,r10,STB_XILINX1_REG4@l
511 li r11,XILINX1_R4_VAL
512 sth r11,0(r10)
513
514 lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */
515 ori r10,r10,STB_XILINX1_REG5@l
516 li r11,XILINX1_R5_VAL
517 sth r11,0(r10)
518
519 lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */
520 ori r10,r10,STB_XILINX1_REG6@l
521 li r11,XILINX1_R6_VAL
522 sth r11,0(r10)
523
524 lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/
525 ori r10,r10,STB_XILINX1_FLUSH@l
526 li r11,0x0000
527 sth r11,0(r10)
528
529 /*--------------------------------------------------------------------+
530 | Init Xilinx #2 Registers
531 +--------------------------------------------------------------------*/
532 lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */
533 ori r10,r10,STB_XILINX2_REG0@l
534 li r11,XILINX2_R0_VAL
535 sth r11,0(r10)
536
537 lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */
538 ori r10,r10,STB_XILINX2_REG1@l
539 li r11,XILINX2_R1_VAL
540 sth r11,0(r10)
541
542 lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */
543 ori r10,r10,STB_XILINX2_REG2@l
544 li r11,XILINX2_R2_VAL
545 sth r11,0(r10)
546
547 blr
548 function_epilog(initb_config)
549
550
551/******************************************************************************
552|
553| Routine: INITB_HSMC0.
554|
555| Purpose: Initialize the HSMC0 Registers for SDRAM
556| Parameters: None.
557| Returns: R3 = 0: Successful
558| = -1: Unsuccessful, SDRAM did not reset properly.
559|
560******************************************************************************/
561 function_prolog(initb_hsmc0)
562 mflr r0 /* Save return addr */
563
564 /*--------------------------------------------------------------------+
565 | Set Global SDRAM Controller to recommended default
566 +--------------------------------------------------------------------*/
567 lis r10,0x6C00
568 ori r10,r10,0x0000
569 mtdcr hsmc0_gr,r10
570
571 /*--------------------------------------------------------------------+
572 | Set HSMC0 Data Register to recommended default
573 +--------------------------------------------------------------------*/
574 lis r10,0x0037
575 ori r10,r10,0x0000
576 mtdcr hsmc0_data,r10
577
578 /*--------------------------------------------------------------------+
579 | Init HSMC0 Bank Register 0
580 +--------------------------------------------------------------------*/
581 lis r10,HSMC0_BR0_VAL@h
582 ori r10,r10,HSMC0_BR0_VAL@l
583 mtdcr hsmc0_br0,r10
584
585 /*--------------------------------------------------------------------+
586 | Init HSMC0 Bank Register 1
587 +--------------------------------------------------------------------*/
588 lis r10,HSMC0_BR1_VAL@h
589 ori r10,r10,HSMC0_BR1_VAL@l
590 mtdcr hsmc0_br1,r10
591
592 /*--------------------------------------------------------------------+
593 | Set HSMC0 Control Reg 0
594 +--------------------------------------------------------------------*/
595 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
596 ori r10,r10,0x0000
597 mtdcr hsmc0_cr0,r10
598 li r3,0x0000
599 bl hsmc_cr_wait /* wait for op completion */
600 cmpwi cr0,r3,0x0000
601 bne cr0,hsmc0_err
602
603 lis r10,0x8078 /* AUTO-REFRESH */
604 ori r10,r10,0x0000
605 mtdcr hsmc0_cr0,r10
606 li r3,0x0000
607 bl hsmc_cr_wait /* wait for op completion */
608 cmpwi cr0,r3,0x0000
609 bne cr0,hsmc0_err
610
611 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
612 ori r10,r10,0x8000
613 mtdcr hsmc0_cr0,r10
614 li r3,0x0000
615 bl hsmc_cr_wait /* wait for op completion */
616 cmpwi cr0,r3,0x0000
617 bne hsmc0_err
618
619 /*--------------------------------------------------------------------+
620 | Set HSMC0 Control Reg 1
621 +--------------------------------------------------------------------*/
622 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
623 ori r10,r10,0x0000
624 mtdcr hsmc0_cr1,r10
625 li r3,0x0001
626 bl hsmc_cr_wait /* wait for op completion */
627 cmpwi cr0,r3,0x0000
628 bne cr0,hsmc0_err
629
630 lis r10,0x8078 /* AUTO-REFRESH */
631 ori r10,r10,0x0000
632 mtdcr hsmc0_cr1,r10
633 li r3,0x0001
634 bl hsmc_cr_wait /* wait for op completion */
635 cmpwi cr0,r3,0x0000
636 bne cr0,hsmc0_err
637
638 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
639 ori r10,r10,0x8000
640 mtdcr hsmc0_cr1,r10
641 li r3,0x0001
642 bl hsmc_cr_wait /* wait for op completion */
643 cmpwi cr0,r3,0x0000
644 bne cr0,hsmc0_err
645
646 /*--------------------------------------------------------------------+
647 | Set HSMC0 Refresh Register
648 +--------------------------------------------------------------------*/
649 lis r10,0x0FE1
650 ori r10,r10,0x0000
651 mtdcr hsmc0_crr,r10
652 li r3,0
653
654hsmc0_err:
655 mtlr r0
656 blr
657 function_epilog(initb_hsmc0)
658
659
660/******************************************************************************
661|
662| Routine: INITB_HSMC1.
663|
664| Purpose: Initialize the HSMC1 Registers for SDRAM
665| Parameters: None.
666| Returns: R3 = 0: Successful
667| = -1: Unsuccessful, SDRAM did not reset properly.
668|
669******************************************************************************/
670 function_prolog(initb_hsmc1)
671 mflr r0 /* Save return addr */
672
673 /*--------------------------------------------------------------------+
674 | Set Global SDRAM Controller to recommended default
675 +--------------------------------------------------------------------*/
676 lis r10,0x6C00
677 ori r10,r10,0x0000
678 mtdcr hsmc1_gr,r10
679
680 /*--------------------------------------------------------------------+
681 | Set HSMC1 Data Register to recommended default
682 +--------------------------------------------------------------------*/
683 lis r10,0x0037
684 ori r10,r10,0x0000
685 mtdcr hsmc1_data,r10
686
687 /*--------------------------------------------------------------------+
688 | Init HSMC1 Bank Register 0
689 +--------------------------------------------------------------------*/
690 lis r10,HSMC1_BR0_VAL@h
691 ori r10,r10,HSMC1_BR0_VAL@l
692 mtdcr hsmc1_br0,r10
693
694 /*--------------------------------------------------------------------+
695 | Init HSMC1 Bank Register 1
696 +--------------------------------------------------------------------*/
697 lis r10,HSMC1_BR1_VAL@h
698 ori r10,r10,HSMC1_BR1_VAL@l
699 mtdcr hsmc1_br1,r10
700
701 /*--------------------------------------------------------------------+
702 | Set HSMC1 Control Reg 0
703 +--------------------------------------------------------------------*/
704 lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */
705 ori r10,r10,0x0000
706 mtdcr hsmc1_cr0,r10
707 li r3,0x0002
708 bl hsmc_cr_wait /* wait for operation completion */
709 cmpwi cr0,r3,0x0000
710 bne hsmc1_err
711
712 lis r10,0x8078 /* AUTO-REFRESH */
713 ori r10,r10,0x0000
714 mtdcr hsmc1_cr0,r10
715 li r3,0x0002
716 bl hsmc_cr_wait /* wait for operation completion */
717 cmpwi cr0,r3,0x0000
718 bne hsmc1_err
719
720 lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */
721 ori r10,r10,0x8000
722 mtdcr hsmc1_cr0,r10
723 li r3,0x0002
724 bl hsmc_cr_wait /* wait for operation completion */
725 cmpwi cr0,r3,0x0000
726 bne hsmc1_err
727
728 /*--------------------------------------------------------------------+
729 | Set HSMC1 Control Reg 1
730 +--------------------------------------------------------------------*/
731 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
732 ori r10,r10,0x0000
733 mtdcr hsmc1_cr1,r10
734 li r3,0x0003
735 bl hsmc_cr_wait /* wait for op completion */
736 cmpwi cr0,r3,0x0000
737 bne hsmc1_err
738
739 lis r10,0x8078 /* AUTO-REFRESH */
740 ori r10,r10,0x0000
741 mtdcr hsmc1_cr1,r10
742 li r3,0x0003
743 bl hsmc_cr_wait /* wait for op completion */
744 cmpwi cr0,r3,0x0000
745 bne hsmc1_err
746
747 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
748 ori r10,r10,0x8000
749 mtdcr hsmc1_cr1,r10
750 li r3,0x0003
751 bl hsmc_cr_wait /* wait for op completion */
752 cmpwi cr0,r3,0x0000
753 bne hsmc1_err
754
755 /*--------------------------------------------------------------------+
756 | Set HSMC1 Refresh Register
757 +--------------------------------------------------------------------*/
758 lis r10,0x0FE1
759 ori r10,r10,0x0000
760 mtdcr hsmc1_crr,r10
761 xor r3,r3,r3
762
763hsmc1_err:
764 mtlr r0
765 blr
766 function_epilog(initb_hsmc1)
767
768
769/******************************************************************************
770|
771| Routine: INITB_CACHE
772|
773| Purpose: This routine will enable Data and Instruction Cache.
774| The Data Cache is an 8K two-way set associative and the
775| Instruction Cache is an 16K two-way set associative cache.
776|
777| Parameters: None.
778|
779| Returns: None.
780|
781******************************************************************************/
782 function_prolog(initb_cache)
783 mflr r0 /* Save return addr */
784
785 bl initb_Dcache /* enable D-Cache */
786 bl initb_Icache /* enable I-Cache */
787
788 mtlr r0
789 blr
790 function_epilog(initb_cache)
791
792
793/******************************************************************************
794|
795| Routine: INITB_DCACHE
796|
797| Purpose: This routine will invalidate all data in the Data Cache and
798| then enable D-Cache. If cache is enabled already, the D-Cache
799| will be flushed before the data is invalidated.
800|
801| Parameters: None.
802|
803| Returns: None.
804|
805******************************************************************************/
806 function_prolog(initb_Dcache)
807 /*--------------------------------------------------------------------+
808 | Flush Data Cache if enabled
809 +--------------------------------------------------------------------*/
810 mfdccr r10 /* r10 <- DCCR */
811 isync /* ensure prev insts done */
812 cmpwi r10,0x00
813 beq ic_dcinv /* D-cache off, invalidate */
814
815 /*--------------------------------------------------------------------+
816 | Data Cache enabled, force known memory addresses to be Cached
817 +--------------------------------------------------------------------*/
818 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
819 andis. r10,r10,0xFFF0
820 li r11,DCACHE_NLINES /* r11 <- # A-way addresses */
821 addi r11,r11,DCACHE_NLINES /* r11 <- # B-way addresses */
822 mtctr r11 /* set loop counter */
823
824ic_dcload:
825 lwz r12,0(r10) /* force cache of address */
826 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
827 bdnz ic_dcload
828 sync /* ensure prev insts done */
829 isync
830
831 /*--------------------------------------------------------------------+
832 | Flush the known memory addresses from Cache
833 +--------------------------------------------------------------------*/
834 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
835 andis. r10,r10,0xFFF0
836 mtctr r11 /* set loop counter */
837
838ic_dcflush:
839 dcbf 0,r10 /* flush D-cache line */
840 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
841 bdnz ic_dcflush
842 sync /* ensure prev insts done */
843 isync
844
845 /*--------------------------------------------------------------------+
846 | Disable then invalidate Data Cache
847 +--------------------------------------------------------------------*/
848 li r10,0 /* r10 <- 0 */
849 mtdccr r10 /* disable the D-Cache */
850 isync /* ensure prev insts done */
851
852ic_dcinv:
853 li r10,0 /* r10 <- line address */
854 li r11,DCACHE_NLINES /* r11 <- # lines in cache */
855 mtctr r11 /* set loop counter */
856
857ic_dcloop:
858 dccci 0,r10 /* invalidate A/B cache lns */
859 addi r10,r10,DCACHE_NBYTES /* bump to next line */
860 bdnz ic_dcloop
861 sync /* ensure prev insts done */
862 isync
863
864 /*--------------------------------------------------------------------+
865 | Enable Data Cache
866 +--------------------------------------------------------------------*/
867 lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/
868 ori r10,r10,DCACHE_ENABLE@l
869 mtdccr r10
870 sync /* ensure prev insts done */
871 isync
872
873 blr
874 function_epilog(initb_Dcache)
875
876
877/******************************************************************************
878|
879| Routine: INITB_ICACHE
880|
881| Purpose: This routine will invalidate all data in the Instruction
882| Cache then enable I-Cache.
883|
884| Parameters: None.
885|
886| Returns: None.
887|
888******************************************************************************/
889 function_prolog(initb_Icache)
890 /*--------------------------------------------------------------------+
891 | Invalidate Instruction Cache
892 +--------------------------------------------------------------------*/
893 li r10,0 /* r10 <- lines address */
894 iccci 0,r10 /* invalidate all I-cache */
895 sync /* ensure prev insts done */
896 isync
897
898 /*--------------------------------------------------------------------+
899 | Enable Instruction Cache
900 +--------------------------------------------------------------------*/
901 lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/
902 ori r10,r10,ICACHE_ENABLE@l
903 mticcr r10
904 sync /* ensure prev insts done */
905 isync
906
907 blr
908 function_epilog(initb_Icache)
909
910#if 0
911/******************************************************************************
912|
913| Routine: INITB_GET_CSPD
914|
915| Purpose: Determine the CPU Core Speed. The 13.5 Mhz Time Base
916| Counter (TBC) is used to measure a conditional branch
917| instruction.
918|
919| Parameters: R3 = Address of Bus Speed
920| R4 = Address of Core Speed
921|
922| Returns: (R3) = >0: Bus Speed.
923| 0: Bus Speed not found in Look-Up Table.
924| (R4) = >0: Core Speed.
925| 0: Core Speed not found in Look-Up Table.
926|
927| Note: 1. This routine assumes the bdnz branch instruction takes
928| two instruction cycles to complete.
929| 2. This routine must be called before interrupts are enabled.
930|
931******************************************************************************/
932 function_prolog(initb_get_cspd)
933 mflr r0 /* Save return address */
934 /*--------------------------------------------------------------------+
935 | Set-up timed loop
936 +--------------------------------------------------------------------*/
937 lis r9,gcs_time_loop@h /* r9 <- addr loop instr */
938 ori r9,r9,gcs_time_loop@l
939 lis r10,GCS_LCNT@h /* r10 <- loop count */
940 ori r10,r10,GCS_LCNT@l
941 mtctr r10 /* ctr <- loop count */
942 lis r11,STB_TIMERS_TBC@h /* r11 <- TBC register addr */
943 ori r11,r11,STB_TIMERS_TBC@l
944 li r12,0 /* r12 <- 0 */
945
946 /*--------------------------------------------------------------------+
947 | Cache timed-loop instruction
948 +--------------------------------------------------------------------*/
949 icbt 0,r9
950 sync
951 isync
952
953 /*--------------------------------------------------------------------+
954 | Get number of 13.5 Mhz cycles to execute time-loop
955 +--------------------------------------------------------------------*/
956 stw r12,0(r11) /* reset TBC */
957gcs_time_loop:
958 bdnz+ gcs_time_loop /* force branch pred taken */
959 lwz r5,0(r11) /* r5 <- num 13.5 Mhz ticks */
960 li r6,5 /* LUT based on 1/5th the...*/
961 divw r5,r5,r6 /*..loop count used */
962 sync
963 isync
964
965 /*--------------------------------------------------------------------+
966 | Look-up core speed based on TBC value
967 +--------------------------------------------------------------------*/
968 lis r6,gcs_lookup_table@h /* r6 <- pts at core spd LUT*/
969 ori r6,r6,gcs_lookup_table@l
970 bl gcs_cspd_lookup /* find core speed in LUT */
971
972 mtlr r0 /* set return address */
973 blr
974 function_epilog(initb_get_cspd)
975
976#endif
977/*****************************************************************************+
978| XXXX XX XX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX
979| XX XXX XX X XX X XX X XX XX XXX XX XXXX XX
980| XX XXXX XX XX XX X XX XX XXXX XX XX XX XX
981| XX XX XXXX XX XXXX XXXXX XX XXXX XX XX XX
982| XX XX XXX XX XX X XX XX XX XXX XXXXXX XX
983| XX XX XX XX XX X XX XX XX XX XX XX XX XX
984| XXXX XX XX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX
985+*****************************************************************************/
986/******************************************************************************
987|
988| Routine: HSMC_CR_WAIT
989|
990| Purpose: Wait for the HSMC Control Register (bits 12-16) to be reset
991| after an auto-refresh, pre-charge or program mode register
992| command execution.
993|
994| Parameters: R3 = HSMC Control Register ID.
995| 0: HSMC0 CR0
996| 1: HSMC0 CR1
997| 2: HSMC1 CR0
998| 3: HSMC1 CR1
999|
1000| Returns: R3 = 0: Successful
1001| -1: Unsuccessful
1002|
1003******************************************************************************/
1004hsmc_cr_wait:
1005
1006 li r11,10 /* r11 <- retry counter */
1007 mtctr r11 /* set retry counter */
1008 mr r11,r3 /* r11 <- HSMC CR reg id */
1009
1010hsmc_cr_rep:
1011 bdz hsmc_cr_err /* branch if max retries hit*/
1012
1013 /*--------------------------------------------------------------------+
1014 | GET HSMCx_CRx value based on HSMC Control Register ID
1015 +--------------------------------------------------------------------*/
1016try_hsmc0_cr0: /* CHECK IF ID=HSMC0 CR0 REG*/
1017 cmpwi cr0,r11,0x0000
1018 bne cr0,try_hsmc0_cr1
1019 mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */
1020 b hsmc_cr_read
1021
1022try_hsmc0_cr1: /* CHECK IF ID=HSMC0 CR1 REG*/
1023 cmpwi cr0,r11,0x0001
1024 bne cr0,try_hsmc1_cr0
1025 mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */
1026 b hsmc_cr_read
1027
1028try_hsmc1_cr0: /* CHECK IF ID=HSMC1 CR0 REG*/
1029 cmpwi cr0,r11,0x0002
1030 bne cr0,try_hsmc1_cr1
1031 mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */
1032 b hsmc_cr_read
1033
1034try_hsmc1_cr1: /* CHECK IF ID=HSMC1 CR1 REG*/
1035 cmpwi cr0,r11,0x0003
1036 bne cr0,hsmc_cr_err
1037 mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */
1038
1039 /*--------------------------------------------------------------------+
1040 | Check if HSMC CR register was reset after command execution
1041 +--------------------------------------------------------------------*/
1042hsmc_cr_read:
1043 lis r12,0x000F /* create "AND" mask */
1044 ori r12,r12,0x8000
1045 and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/
1046 bne cr0,hsmc_cr_rep /* wait for bits to reset */
1047 li r3,0 /* set return code = success*/
1048 b hsmc_cr_done
1049
1050hsmc_cr_err: /* ERROR: SDRAM didn't reset*/
1051 li r3,-1 /* set RC=unsuccessful */
1052
1053hsmc_cr_done:
1054 blr
1055
1056#if 0
1057/******************************************************************************
1058|
1059| Routine: GCS_CSPD_LOOKUP
1060|
1061| Purpose: Uses the number of 13.5 Mhz clock ticks found after executing
1062| the branch instruction time loop to look-up the CPU Core Speed
1063| in the Core Speed Look-up Table.
1064|
1065| Parameters: R3 = Address of Bus Speed
1066| R4 = Address of Core Speed
1067| R5 = Number of 13.5 Mhz clock ticks found in time loop.
1068| R6 = Pointer to Core-Speed Look-Up Table
1069|
1070| Returns: (R3) = >0: Bus Speed.
1071| 0: Bus Speed not found in Look-Up Table.
1072| (R4) = >0: Core Speed.
1073| 0: Core Speed not found in Look-Up Table.
1074|
1075| Note: Core Speed = Bus Speed * Mult Factor (1-4x).
1076|
1077******************************************************************************/
1078gcs_cspd_lookup:
1079
1080 li r9,1 /* r9 <- core speed mult */
1081 /*--------------------------------------------------------------------+
1082 | Get theoritical number 13.5 Mhz ticks for a given Bus Speed from
1083 | Look-up Table. Check all mult factors to determine if calculated
1084 | value matches theoretical value (within a tolerance).
1085 +--------------------------------------------------------------------*/
1086gcs_cspd_loop:
1087 lwz r10,0(r6) /* r10 <- no. ticks from LUT*/
1088 divw r10,r10,r9 /* r10 <- div mult (1-4x) */
1089 subi r11,r10,GCS_CTICK_TOL /* r11 <- no. tks low range */
1090 addi r12,r10,GCS_CTICK_TOL /* r12 <- no. tks high range*/
1091
1092 cmpw cr0,r5,r11 /* calc value within range? */
1093 blt gcs_cspd_retry /* less than low range */
1094 cmpw cr0,r5,r12
1095 bgt gcs_cspd_retry /* greater than high range */
1096 b gcs_cspd_fnd /* calc value within range */
1097
1098 /*--------------------------------------------------------------------+
1099 | SO FAR CORE SPEED NOT FOUND: Check next mult factor
1100 +--------------------------------------------------------------------*/
1101gcs_cspd_retry:
1102 addi r9,r9,1 /* bump mult factor (1-4x) */
1103 cmpwi cr0,r9,GCS_NMULT
1104 ble gcs_cspd_loop
1105
1106 /*--------------------------------------------------------------------+
1107 | SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT
1108 +--------------------------------------------------------------------*/
1109 li r9,1 /* reset mult factor */
1110 addi r6,r6,GCS_TROW_BYTES /* point at next table entry*/
1111 lwz r10,0(r6)
1112 cmpwi cr0,r10,0 /* check for EOT flag */
1113 bne gcs_cspd_loop
1114
1115 /*--------------------------------------------------------------------+
1116 | COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE
1117 +--------------------------------------------------------------------*/
1118gcs_cspd_fnd:
1119 lwz r5,4(r6) /* r5 <- Bus Speed in LUT */
1120 mullw r6,r5,r9 /* r6 <- Core speed */
1121 stw r5,0(r3) /* (r3) <- Bus Speed */
1122 stw r6,0(r4) /* (r4) <- Core Speed */
1123
1124 blr
1125#endif
diff --git a/arch/ppc/boot/simple/rw4/stb.h b/arch/ppc/boot/simple/rw4/stb.h
deleted file mode 100644
index 9afa5ab24d26..000000000000
--- a/arch/ppc/boot/simple/rw4/stb.h
+++ /dev/null
@@ -1,239 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1999
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Maciej P. Tyrlik
22| Component: Include file.
23| File: stb.h
24| Purpose: Common Set-tob-box definitions.
25| Changes:
26| Date: Comment:
27| ----- --------
28| 14-Jan-97 Created for ElPaso pass 1 MPT
29| 13-May-97 Added function prototype and global variables MPT
30| 08-Dec-98 Added RAW IR task information MPT
31| 19-Jan-99 Port to Romeo MPT
32| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB
33+----------------------------------------------------------------------------*/
34
35#ifndef _stb_h_
36#define _stb_h_
37
38/*----------------------------------------------------------------------------+
39| Read/write from I/O macros.
40+----------------------------------------------------------------------------*/
41#define inbyte(port) (*((unsigned char volatile *)(port)))
42#define outbyte(port,data) *(unsigned char volatile *)(port)=\
43 (unsigned char)(data)
44
45#define inshort(port) (*((unsigned short volatile *)(port)))
46#define outshort(port,data) *(unsigned short volatile *)(port)=\
47 (unsigned short)(data)
48
49#define inword(port) (*((unsigned long volatile *)(port)))
50#define outword(port,data) *(unsigned long volatile *)(port)=\
51 (unsigned long)(data)
52
53/*----------------------------------------------------------------------------+
54| STB interrupts.
55+----------------------------------------------------------------------------*/
56#define STB_XP_TP_INT 0
57#define STB_XP_APP_INT 1
58#define STB_AUD_INT 2
59#define STB_VID_INT 3
60#define STB_DMA0_INT 4
61#define STB_DMA1_INT 5
62#define STB_DMA2_INT 6
63#define STB_DMA3_INT 7
64#define STB_SCI_INT 8
65#define STB_I2C1_INT 9
66#define STB_I2C2_INT 10
67#define STB_GPT_PWM0 11
68#define STB_GPT_PWM1 12
69#define STB_SCP_INT 13
70#define STB_SSP_INT 14
71#define STB_GPT_PWM2 15
72#define STB_EXT5_INT 16
73#define STB_EXT6_INT 17
74#define STB_EXT7_INT 18
75#define STB_EXT8_INT 19
76#define STB_SCC_INT 20
77#define STB_SICC_RECV_INT 21
78#define STB_SICC_TRAN_INT 22
79#define STB_PPU_INT 23
80#define STB_DCRX_INT 24
81#define STB_EXT0_INT 25
82#define STB_EXT1_INT 26
83#define STB_EXT2_INT 27
84#define STB_EXT3_INT 28
85#define STB_EXT4_INT 29
86#define STB_REDWOOD_ENET_INT STB_EXT1_INT
87
88/*----------------------------------------------------------------------------+
89| STB tasks, task stack sizes, and task priorities. The actual task priority
90| is 1 more than the specified number since priority 0 is reserved (system
91| internally adds 1 to supplied priority number).
92+----------------------------------------------------------------------------*/
93#define STB_IDLE_TASK_SS (5* 1024)
94#define STB_IDLE_TASK_PRIO 0
95#define STB_LEDTEST_SS (2* 1024)
96#define STB_LEDTEST_PRIO 0
97#define STB_CURSOR_TASK_SS (10* 1024)
98#define STB_CURSOR_TASK_PRIO 7
99#define STB_MPEG_TASK_SS (10* 1024)
100#define STB_MPEG_TASK_PRIO 9
101#define STB_DEMUX_TASK_SS (10* 1024)
102#define STB_DEMUX_TASK_PRIO 20
103#define RAW_STB_IR_TASK_SS (10* 1024)
104#define RAW_STB_IR_TASK_PRIO 20
105
106#define STB_SERIAL_ER_TASK_SS (10* 1024)
107#define STB_SERIAL_ER_TASK_PRIO 1
108#define STB_CA_TASK_SS (10* 1024)
109#define STB_CA_TASK_PRIO 8
110
111#define INIT_DEFAULT_VIDEO_SS (10* 1024)
112#define INIT_DEFAULT_VIDEO_PRIO 8
113#define INIT_DEFAULT_SERVI_SS (10* 1024)
114#define INIT_DEFAULT_SERVI_PRIO 8
115#define INIT_DEFAULT_POST_SS (10* 1024)
116#define INIT_DEFAULT_POST_PRIO 8
117#define INIT_DEFAULT_INTER_SS (10* 1024)
118#define INIT_DEFAULT_INTER_PRIO 8
119#define INIT_DEFAULT_BR_SS (10* 1024)
120#define INIT_DEFAULT_BR_PRIO 8
121#define INITIAL_TASK_STACK_SIZE (32* 1024)
122
123#ifdef VESTA
124/*----------------------------------------------------------------------------+
125| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the
126| address is not decoded. Numbers below are dependent on board configuration.
127| FLASH, SDRAM, DRAM numbers can be affected by actual board setup.
128|
129| FFE0,0000 - FFFF,FFFF FLASH
130| F200,0000 - F210,FFFF FPGA logic
131| Ethernet = F200,0000
132| LED Display = F200,0100
133| Xilinx #1 Regs = F204,0000
134| Xilinx #2 Regs = F208,0000
135| Spare = F20C,0000
136| IDE CS0 = F210,0000
137| F410,0000 - F410,FFFF IDE CS1
138| C000,0000 - C7FF,FFFF OBP
139| C000,0000 - C000,0014 SICC (16550 + infra red)
140| C001,0000 - C001,0018 PPU (Parallel Port)
141| C002,0000 - C002,001B SC0 (Smart Card 0)
142| C003,0000 - C003,000F I2C0
143| C004,0000 - C004,0009 SCC (16550 UART)
144| C005,0000 - C005,0124 GPT (Timers)
145| C006,0000 - C006,0058 GPIO0
146| C007,0000 - C007,001b SC1 (Smart Card 1)
147| C008,0000 - C008,FFFF Unused
148| C009,0000 - C009,FFFF Unused
149| C00A,0000 - C00A,FFFF Unused
150| C00B,0000 - C00B,000F I2C1
151| C00C,0000 - C00C,0006 SCP
152| C00D,0000 - C00D,0010 SSP
153| A000,0000 - A0FF,FFFF SDRAM1 (16M)
154| 0000,0000 - 00FF,FFFF SDRAM0 (16M)
155+----------------------------------------------------------------------------*/
156#define STB_FLASH_BASE_ADDRESS 0xFFE00000
157#define STB_FPGA_BASE_ADDRESS 0xF2000000
158#define STB_SICC_BASE_ADDRESS 0xC0000000
159#define STB_PPU_BASE_ADDR 0xC0010000
160#define STB_SC0_BASE_ADDRESS 0xC0020000
161#define STB_I2C1_BASE_ADDRESS 0xC0030000
162#define STB_SCC_BASE_ADDRESS 0xC0040000
163#define STB_TIMERS_BASE_ADDRESS 0xC0050000
164#define STB_GPIO0_BASE_ADDRESS 0xC0060000
165#define STB_SC1_BASE_ADDRESS 0xC0070000
166#define STB_I2C2_BASE_ADDRESS 0xC00B0000
167#define STB_SCP_BASE_ADDRESS 0xC00C0000
168#define STB_SSP_BASE_ADDRESS 0xC00D0000
169/*----------------------------------------------------------------------------+
170|The following are used by the IBM RTOS SW.
171|15-May-00 Changed these values to reflect movement of base addresses in
172|order to support 32MB of contiguous SDRAM space.
173|Points to the cacheable region since these values are used in IBM RTOS
174|to establish the vector address.
175+----------------------------------------------------------------------------*/
176#define STB_SDRAM1_BASE_ADDRESS 0x20000000
177#define STB_SDRAM1_SIZE 0x01000000
178#define STB_SDRAM0_BASE_ADDRESS 0x1F000000
179#define STB_SDRAM0_SIZE 0x01000000
180
181#else
182/*----------------------------------------------------------------------------+
183| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the
184| address is not decoded. Numbers below are dependent on board configuration.
185| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB
186| devices are inside the ElPaso chip.
187| FFE0,0000 - FFFF,FFFF FLASH
188| F144,0000 - F104,FFFF FPGA logic
189| F140,0000 - F100,0000 ethernet (through FPGA logic)
190| C000,0000 - C7FF,FFFF OBP
191| C000,0000 - C000,0014 SICC (16550+ infra red)
192| C001,0000 - C001,0016 PPU (parallel port)
193| C002,0000 - C002,001B SC (smart card)
194| C003,0000 - C003,000F I2C 1
195| C004,0000 - C004,0009 SCC (16550 UART)
196| C005,0000 - C005,0124 Timers
197| C006,0000 - C006,0058 GPIO0
198| C007,0000 - C007,0058 GPIO1
199| C008,0000 - C008,0058 GPIO2
200| C009,0000 - C009,0058 GPIO3
201| C00A,0000 - C00A,0058 GPIO4
202| C00B,0000 - C00B,000F I2C 2
203| C00C,0000 - C00C,0006 SCP
204| C00D,0000 - C00D,0006 SSP
205| A000,0000 - A0FF,FFFF SDRAM 16M
206| 0000,0000 - 00FF,FFFF DRAM 16M
207+----------------------------------------------------------------------------*/
208#define STB_FLASH_BASE_ADDRESS 0xFFE00000
209#define STB_FPGA_BASE_ADDRESS 0xF1440000
210#define STB_ENET_BASE_ADDRESS 0xF1400000
211#define STB_SICC_BASE_ADDRESS 0xC0000000
212#define STB_PPU_BASE_ADDR 0xC0010000
213#define STB_SC_BASE_ADDRESS 0xC0020000
214#define STB_I2C1_BASE_ADDRESS 0xC0030000
215#define STB_SCC_BASE_ADDRESS 0xC0040000
216#define STB_TIMERS_BASE_ADDRESS 0xC0050000
217#define STB_GPIO0_BASE_ADDRESS 0xC0060000
218#define STB_GPIO1_BASE_ADDRESS 0xC0070000
219#define STB_GPIO2_BASE_ADDRESS 0xC0080000
220#define STB_GPIO3_BASE_ADDRESS 0xC0090000
221#define STB_GPIO4_BASE_ADDRESS 0xC00A0000
222#define STB_I2C2_BASE_ADDRESS 0xC00B0000
223#define STB_SCP_BASE_ADDRESS 0xC00C0000
224#define STB_SSP_BASE_ADDRESS 0xC00D0000
225#define STB_SDRAM_BASE_ADDRESS 0xA0000000
226#endif
227
228/*----------------------------------------------------------------------------+
229| Other common defines.
230+----------------------------------------------------------------------------*/
231#ifndef TRUE
232#define TRUE 1
233#endif
234
235#ifndef FALSE
236#define FALSE 0
237#endif
238
239#endif /* _stb_h_ */
diff --git a/arch/ppc/boot/simple/uartlite_tty.c b/arch/ppc/boot/simple/uartlite_tty.c
deleted file mode 100644
index ca1743e3e912..000000000000
--- a/arch/ppc/boot/simple/uartlite_tty.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * Xilinx UARTLITE bootloader driver
3 *
4 * Copyright (c) 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/types.h>
13#include <asm/serial.h>
14#include <asm/io.h>
15#include <platforms/4xx/xparameters/xparameters.h>
16
17#define UARTLITE_BASEADDR ((void*)(XPAR_UARTLITE_0_BASEADDR))
18
19unsigned long
20serial_init(int chan, void *ignored)
21{
22 /* Clear the RX FIFO */
23 out_be32(UARTLITE_BASEADDR + 0x0C, 0x2);
24 return 0;
25}
26
27void
28serial_putc(unsigned long com_port, unsigned char c)
29{
30 while ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x08) != 0); /* spin */
31 out_be32(UARTLITE_BASEADDR + 0x4, c);
32}
33
34unsigned char
35serial_getc(unsigned long com_port)
36{
37 while ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x01) == 0); /* spin */
38 return in_be32(UARTLITE_BASEADDR);
39}
40
41int
42serial_tstc(unsigned long com_port)
43{
44 return ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x01) != 0);
45}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 10:52:23 -0500