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Diffstat (limited to 'arch/ppc/boot/simple/head.S')
-rw-r--r-- | arch/ppc/boot/simple/head.S | 137 |
1 files changed, 0 insertions, 137 deletions
diff --git a/arch/ppc/boot/simple/head.S b/arch/ppc/boot/simple/head.S deleted file mode 100644 index 1b4d7b1d4ec1..000000000000 --- a/arch/ppc/boot/simple/head.S +++ /dev/null | |||
@@ -1,137 +0,0 @@ | |||
1 | /* | ||
2 | * Initial board bringup code for many different boards. | ||
3 | * | ||
4 | * Author: Tom Rini | ||
5 | * trini@mvista.com | ||
6 | * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others). | ||
7 | * | ||
8 | * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | |||
14 | #include <asm/reg.h> | ||
15 | #include <asm/cache.h> | ||
16 | #include <asm/ppc_asm.h> | ||
17 | |||
18 | .text | ||
19 | |||
20 | /* | ||
21 | * Begin at some arbitrary location in RAM or Flash | ||
22 | * Initialize core registers | ||
23 | * Configure memory controller (Not executing from RAM) | ||
24 | * Move the boot code to the link address (8M) | ||
25 | * Setup C stack | ||
26 | * Initialize UART | ||
27 | * Decompress the kernel to 0x0 | ||
28 | * Jump to the kernel entry | ||
29 | * | ||
30 | */ | ||
31 | |||
32 | .globl start | ||
33 | start: | ||
34 | bl start_ | ||
35 | #ifdef CONFIG_IBM_OPENBIOS | ||
36 | /* The IBM "Tree" bootrom knows that the address of the bootrom | ||
37 | * read only structure is 4 bytes after _start. | ||
38 | */ | ||
39 | .long 0x62726f6d # structure ID - "brom" | ||
40 | .long 0x5f726f00 # - "_ro\0" | ||
41 | .long 1 # structure version | ||
42 | .long bootrom_cmdline # address of *bootrom_cmdline | ||
43 | #endif | ||
44 | |||
45 | start_: | ||
46 | #ifdef CONFIG_FORCE | ||
47 | /* We have some really bad firmware. We must disable the L1 | ||
48 | * icache/dcache now or the board won't boot. | ||
49 | */ | ||
50 | li r4,0x0000 | ||
51 | isync | ||
52 | mtspr SPRN_HID0,r4 | ||
53 | sync | ||
54 | isync | ||
55 | #endif | ||
56 | |||
57 | #if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP) | ||
58 | mr r29,r3 /* On the MBX860, r3 is the board info pointer. | ||
59 | * On the RPXSUPER, r3 points to the NVRAM | ||
60 | * configuration keys. | ||
61 | * On PReP, r3 is the pointer to the residual data. | ||
62 | */ | ||
63 | #endif | ||
64 | |||
65 | #if defined(CONFIG_XILINX_VIRTEX_4_FX) | ||
66 | /* PPC errata 213: only for Virtex-4 FX */ | ||
67 | mfccr0 0 | ||
68 | oris 0,0,0x50000000@h | ||
69 | mtccr0 0 | ||
70 | #endif | ||
71 | |||
72 | mflr r3 /* Save our actual starting address. */ | ||
73 | |||
74 | /* The following functions we call must not modify r3 or r4..... | ||
75 | */ | ||
76 | #ifdef CONFIG_6xx | ||
77 | /* On PReP we must look at the OpenFirmware pointer and sanity | ||
78 | * test it. On other platforms, we disable the MMU right now | ||
79 | * and other bits. | ||
80 | */ | ||
81 | #ifdef CONFIG_PPC_PREP | ||
82 | /* | ||
83 | * Save the OF pointer to r25, but only if the entry point is in a sane | ||
84 | * location; if not we store 0. If there is no entry point, or it is | ||
85 | * invalid, we establish the default MSR value immediately. Otherwise, | ||
86 | * we defer doing that, to allow OF functions to be called, until we | ||
87 | * begin uncompressing the kernel. | ||
88 | */ | ||
89 | lis r8,0x0fff /* r8 = 0x0fffffff */ | ||
90 | ori r8,r8,0xffff | ||
91 | |||
92 | subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */ | ||
93 | subfe r8,r8,r8 | ||
94 | nand r8,r8,r8 | ||
95 | |||
96 | and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */ | ||
97 | bne+ haveOF | ||
98 | |||
99 | li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */ | ||
100 | mtmsr r8 | ||
101 | isync | ||
102 | haveOF: | ||
103 | mr r25,r5 | ||
104 | #else | ||
105 | bl disable_6xx_mmu | ||
106 | #endif | ||
107 | bl disable_6xx_l1cache | ||
108 | |||
109 | CLEAR_CACHES | ||
110 | #endif | ||
111 | |||
112 | #ifdef CONFIG_8xx | ||
113 | mfmsr r8 /* Turn off interrupts */ | ||
114 | li r9,0 | ||
115 | ori r9,r9,MSR_EE | ||
116 | andc r8,r8,r9 | ||
117 | mtmsr r8 | ||
118 | |||
119 | /* We do this because some boot roms don't initialize the | ||
120 | * processor correctly. Don't do this if you want to debug | ||
121 | * using a BDM device. | ||
122 | */ | ||
123 | li r4,0 /* Zero DER to prevent FRZ */ | ||
124 | mtspr SPRN_DER,r4 | ||
125 | #endif | ||
126 | |||
127 | #if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP) | ||
128 | mr r4,r29 /* put the board info pointer where the relocate | ||
129 | * routine will find it | ||
130 | */ | ||
131 | #endif | ||
132 | |||
133 | /* Get the load address. | ||
134 | */ | ||
135 | subi r3, r3, 4 /* Get the actual IP, not NIP */ | ||
136 | b relocate | ||
137 | |||