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-rw-r--r--arch/ppc/boot/simple/embed_config.c938
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diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c
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1/* Board specific functions for those embedded 8xx boards that do
2 * not have boot monitor support for board information.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/types.h>
11#include <linux/string.h>
12#include <asm/reg.h>
13#ifdef CONFIG_8xx
14#include <asm/mpc8xx.h>
15#endif
16#ifdef CONFIG_8260
17#include <asm/mpc8260.h>
18#include <asm/immap_cpm2.h>
19#endif
20#ifdef CONFIG_40x
21#include <asm/io.h>
22#endif
23#ifdef CONFIG_XILINX_VIRTEX
24#include <platforms/4xx/xparameters/xparameters.h>
25#endif
26extern unsigned long timebase_period_ns;
27
28/* For those boards that don't provide one.
29*/
30#if !defined(CONFIG_MBX)
31static bd_t bdinfo;
32#endif
33
34/* IIC functions.
35 * These are just the basic master read/write operations so we can
36 * examine serial EEPROM.
37 */
38extern void iic_read(uint devaddr, u_char *buf, uint offset, uint count);
39
40/* Supply a default Ethernet address for those eval boards that don't
41 * ship with one. This is an address from the MBX board I have, so
42 * it is unlikely you will find it on your network.
43 */
44static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };
45
46#if defined(CONFIG_MBX)
47
48/* The MBX hands us a pretty much ready to go board descriptor. This
49 * is where the idea started in the first place.
50 */
51void
52embed_config(bd_t **bdp)
53{
54 u_char *mp;
55 u_char eebuf[128];
56 int i = 8;
57 bd_t *bd;
58
59 bd = *bdp;
60
61 /* Read the first 128 bytes of the EEPROM. There is more,
62 * but this is all we need.
63 */
64 iic_read(0xa4, eebuf, 0, 128);
65
66 /* All we are looking for is the Ethernet MAC address. The
67 * first 8 bytes are 'MOTOROLA', so check for part of that.
68 * Next, the VPD describes a MAC 'packet' as being of type 08
69 * and size 06. So we look for that and the MAC must follow.
70 * If there are more than one, we still only care about the first.
71 * If it's there, assume we have a valid MAC address. If not,
72 * grab our default one.
73 */
74 if ((*(uint *)eebuf) == 0x4d4f544f) {
75 while (i < 127 && !(eebuf[i] == 0x08 && eebuf[i + 1] == 0x06))
76 i += eebuf[i + 1] + 2; /* skip this packet */
77
78 if (i == 127) /* Couldn't find. */
79 mp = (u_char *)def_enet_addr;
80 else
81 mp = &eebuf[i + 2];
82 }
83 else
84 mp = (u_char *)def_enet_addr;
85
86 for (i=0; i<6; i++)
87 bd->bi_enetaddr[i] = *mp++;
88
89 /* The boot rom passes these to us in MHz. Linux now expects
90 * them to be in Hz.
91 */
92 bd->bi_intfreq *= 1000000;
93 bd->bi_busfreq *= 1000000;
94
95 /* Stuff a baud rate here as well.
96 */
97 bd->bi_baudrate = 9600;
98}
99#endif /* CONFIG_MBX */
100
101#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || \
102 defined(CONFIG_RPX8260) || defined(CONFIG_EP405)
103/* Helper functions for Embedded Planet boards.
104*/
105/* Because I didn't find anything that would do this.......
106*/
107u_char
108aschex_to_byte(u_char *cp)
109{
110 u_char byte, c;
111
112 c = *cp++;
113
114 if ((c >= 'A') && (c <= 'F')) {
115 c -= 'A';
116 c += 10;
117 } else if ((c >= 'a') && (c <= 'f')) {
118 c -= 'a';
119 c += 10;
120 } else
121 c -= '0';
122
123 byte = c * 16;
124
125 c = *cp;
126
127 if ((c >= 'A') && (c <= 'F')) {
128 c -= 'A';
129 c += 10;
130 } else if ((c >= 'a') && (c <= 'f')) {
131 c -= 'a';
132 c += 10;
133 } else
134 c -= '0';
135
136 byte += c;
137
138 return(byte);
139}
140
141static void
142rpx_eth(bd_t *bd, u_char *cp)
143{
144 int i;
145
146 for (i=0; i<6; i++) {
147 bd->bi_enetaddr[i] = aschex_to_byte(cp);
148 cp += 2;
149 }
150}
151
152#ifdef CONFIG_RPX8260
153static uint
154rpx_baseten(u_char *cp)
155{
156 uint retval;
157
158 retval = 0;
159
160 while (*cp != '\n') {
161 retval *= 10;
162 retval += (*cp) - '0';
163 cp++;
164 }
165 return(retval);
166}
167#endif
168
169#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
170static void
171rpx_brate(bd_t *bd, u_char *cp)
172{
173 uint rate;
174
175 rate = 0;
176
177 while (*cp != '\n') {
178 rate *= 10;
179 rate += (*cp) - '0';
180 cp++;
181 }
182
183 bd->bi_baudrate = rate * 100;
184}
185
186static void
187rpx_cpuspeed(bd_t *bd, u_char *cp)
188{
189 uint num, den;
190
191 num = den = 0;
192
193 while (*cp != '\n') {
194 num *= 10;
195 num += (*cp) - '0';
196 cp++;
197 if (*cp == '/') {
198 cp++;
199 den = (*cp) - '0';
200 break;
201 }
202 }
203
204 /* I don't know why the RPX just can't state the actual
205 * CPU speed.....
206 */
207 if (den) {
208 num /= den;
209 num *= den;
210 }
211 bd->bi_intfreq = bd->bi_busfreq = num * 1000000;
212
213 /* The 8xx can only run a maximum 50 MHz bus speed (until
214 * Motorola changes this :-). Greater than 50 MHz parts
215 * run internal/2 for bus speed.
216 */
217 if (num > 50)
218 bd->bi_busfreq /= 2;
219}
220#endif
221
222#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405)
223static void
224rpx_memsize(bd_t *bd, u_char *cp)
225{
226 uint size;
227
228 size = 0;
229
230 while (*cp != '\n') {
231 size *= 10;
232 size += (*cp) - '0';
233 cp++;
234 }
235
236 bd->bi_memsize = size * 1024 * 1024;
237}
238#endif /* LITE || CLASSIC || EP405 */
239#if defined(CONFIG_EP405)
240static void
241rpx_nvramsize(bd_t *bd, u_char *cp)
242{
243 uint size;
244
245 size = 0;
246
247 while (*cp != '\n') {
248 size *= 10;
249 size += (*cp) - '0';
250 cp++;
251 }
252
253 bd->bi_nvramsize = size * 1024;
254}
255#endif /* CONFIG_EP405 */
256
257#endif /* Embedded Planet boards */
258
259#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
260
261/* Read the EEPROM on the RPX-Lite board.
262*/
263void
264embed_config(bd_t **bdp)
265{
266 u_char eebuf[256], *cp;
267 bd_t *bd;
268
269 /* Read the first 256 bytes of the EEPROM. I think this
270 * is really all there is, and I hope if it gets bigger the
271 * info we want is still up front.
272 */
273 bd = &bdinfo;
274 *bdp = bd;
275
276#if 1
277 iic_read(0xa8, eebuf, 0, 128);
278 iic_read(0xa8, &eebuf[128], 128, 128);
279
280 /* We look for two things, the Ethernet address and the
281 * serial baud rate. The records are separated by
282 * newlines.
283 */
284 cp = eebuf;
285 for (;;) {
286 if (*cp == 'E') {
287 cp++;
288 if (*cp == 'A') {
289 cp += 2;
290 rpx_eth(bd, cp);
291 }
292 }
293 if (*cp == 'S') {
294 cp++;
295 if (*cp == 'B') {
296 cp += 2;
297 rpx_brate(bd, cp);
298 }
299 }
300 if (*cp == 'D') {
301 cp++;
302 if (*cp == '1') {
303 cp += 2;
304 rpx_memsize(bd, cp);
305 }
306 }
307 if (*cp == 'H') {
308 cp++;
309 if (*cp == 'Z') {
310 cp += 2;
311 rpx_cpuspeed(bd, cp);
312 }
313 }
314
315 /* Scan to the end of the record.
316 */
317 while ((*cp != '\n') && (*cp != 0xff))
318 cp++;
319
320 /* If the next character is a 0 or ff, we are done.
321 */
322 cp++;
323 if ((*cp == 0) || (*cp == 0xff))
324 break;
325 }
326 bd->bi_memstart = 0;
327#else
328 /* For boards without initialized EEPROM.
329 */
330 bd->bi_memstart = 0;
331 bd->bi_memsize = (8 * 1024 * 1024);
332 bd->bi_intfreq = 48000000;
333 bd->bi_busfreq = 48000000;
334 bd->bi_baudrate = 9600;
335#endif
336}
337#endif /* RPXLITE || RPXCLASSIC */
338
339#ifdef CONFIG_BSEIP
340/* Build a board information structure for the BSE ip-Engine.
341 * There is more to come since we will add some environment
342 * variables and a function to read them.
343 */
344void
345embed_config(bd_t **bdp)
346{
347 u_char *cp;
348 int i;
349 bd_t *bd;
350
351 bd = &bdinfo;
352 *bdp = bd;
353
354 /* Baud rate and processor speed will eventually come
355 * from the environment variables.
356 */
357 bd->bi_baudrate = 9600;
358
359 /* Get the Ethernet station address from the Flash ROM.
360 */
361 cp = (u_char *)0xfe003ffa;
362 for (i=0; i<6; i++) {
363 bd->bi_enetaddr[i] = *cp++;
364 }
365
366 /* The rest of this should come from the environment as well.
367 */
368 bd->bi_memstart = 0;
369 bd->bi_memsize = (16 * 1024 * 1024);
370 bd->bi_intfreq = 48000000;
371 bd->bi_busfreq = 48000000;
372}
373#endif /* BSEIP */
374
375#ifdef CONFIG_FADS
376/* Build a board information structure for the FADS.
377 */
378void
379embed_config(bd_t **bdp)
380{
381 u_char *cp;
382 int i;
383 bd_t *bd;
384
385 bd = &bdinfo;
386 *bdp = bd;
387
388 /* Just fill in some known values.
389 */
390 bd->bi_baudrate = 9600;
391
392 /* Use default enet.
393 */
394 cp = (u_char *)def_enet_addr;
395 for (i=0; i<6; i++) {
396 bd->bi_enetaddr[i] = *cp++;
397 }
398
399 bd->bi_memstart = 0;
400 bd->bi_memsize = (8 * 1024 * 1024);
401 bd->bi_intfreq = 40000000;
402 bd->bi_busfreq = 40000000;
403}
404#endif /* FADS */
405
406#ifdef CONFIG_8260
407/* Compute 8260 clock values if the rom doesn't provide them.
408 */
409static unsigned char bus2core_8260[] = {
410/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
411 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2,
412 6, 5, 13, 2, 14, 4, 15, 2, 3, 11, 8, 10, 16, 12, 7, 2,
413};
414
415static void
416clk_8260(bd_t *bd)
417{
418 uint scmr, vco_out, clkin;
419 uint plldf, pllmf, corecnf;
420 volatile cpm2_map_t *ip;
421
422 ip = (cpm2_map_t *)CPM_MAP_ADDR;
423 scmr = ip->im_clkrst.car_scmr;
424
425 /* The clkin is always bus frequency.
426 */
427 clkin = bd->bi_busfreq;
428
429 /* Collect the bits from the scmr.
430 */
431 plldf = (scmr >> 12) & 1;
432 pllmf = scmr & 0xfff;
433 corecnf = (scmr >> 24) &0x1f;
434
435 /* This is arithmetic from the 8260 manual.
436 */
437 vco_out = clkin / (plldf + 1);
438 vco_out *= 2 * (pllmf + 1);
439 bd->bi_vco = vco_out; /* Save for later */
440
441 bd->bi_cpmfreq = vco_out / 2; /* CPM Freq, in MHz */
442 bd->bi_intfreq = bd->bi_busfreq * bus2core_8260[corecnf] / 2;
443
444 /* Set Baud rate divisor. The power up default is divide by 16,
445 * but we set it again here in case it was changed.
446 */
447 ip->im_clkrst.car_sccr = 1; /* DIV 16 BRG */
448 bd->bi_brgfreq = vco_out / 16;
449}
450
451static unsigned char bus2core_8280[] = {
452/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
453 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2,
454 6, 5, 13, 2, 14, 2, 15, 2, 3, 2, 2, 2, 16, 2, 2, 2,
455};
456
457static void
458clk_8280(bd_t *bd)
459{
460 uint scmr, main_clk, clkin;
461 uint pllmf, corecnf;
462 volatile cpm2_map_t *ip;
463
464 ip = (cpm2_map_t *)CPM_MAP_ADDR;
465 scmr = ip->im_clkrst.car_scmr;
466
467 /* The clkin is always bus frequency.
468 */
469 clkin = bd->bi_busfreq;
470
471 /* Collect the bits from the scmr.
472 */
473 pllmf = scmr & 0xf;
474 corecnf = (scmr >> 24) & 0x1f;
475
476 /* This is arithmetic from the 8280 manual.
477 */
478 main_clk = clkin * (pllmf + 1);
479
480 bd->bi_cpmfreq = main_clk / 2; /* CPM Freq, in MHz */
481 bd->bi_intfreq = bd->bi_busfreq * bus2core_8280[corecnf] / 2;
482
483 /* Set Baud rate divisor. The power up default is divide by 16,
484 * but we set it again here in case it was changed.
485 */
486 ip->im_clkrst.car_sccr = (ip->im_clkrst.car_sccr & 0x3) | 0x1;
487 bd->bi_brgfreq = main_clk / 16;
488}
489#endif
490
491#ifdef CONFIG_SBC82xx
492void
493embed_config(bd_t **bdp)
494{
495 u_char *cp;
496 int i;
497 bd_t *bd;
498 unsigned long pvr;
499
500 bd = *bdp;
501
502 bd = &bdinfo;
503 *bdp = bd;
504 bd->bi_baudrate = 9600;
505 bd->bi_memsize = 256 * 1024 * 1024; /* just a guess */
506
507 cp = (void*)SBC82xx_MACADDR_NVRAM_SCC1;
508 memcpy(bd->bi_enetaddr, cp, 6);
509
510 /* can busfreq be calculated? */
511 pvr = mfspr(SPRN_PVR);
512 if ((pvr & 0xffff0000) == 0x80820000) {
513 bd->bi_busfreq = 100000000;
514 clk_8280(bd);
515 } else {
516 bd->bi_busfreq = 66000000;
517 clk_8260(bd);
518 }
519
520}
521#endif /* SBC82xx */
522
523#if defined(CONFIG_EST8260) || defined(CONFIG_TQM8260)
524void
525embed_config(bd_t **bdp)
526{
527 u_char *cp;
528 int i;
529 bd_t *bd;
530
531 bd = *bdp;
532#if 0
533 /* This is actually provided by my boot rom. I have it
534 * here for those people that may load the kernel with
535 * a JTAG/COP tool and not the rom monitor.
536 */
537 bd->bi_baudrate = 115200;
538 bd->bi_intfreq = 200000000;
539 bd->bi_busfreq = 66666666;
540 bd->bi_cpmfreq = 66666666;
541 bd->bi_brgfreq = 33333333;
542 bd->bi_memsize = 16 * 1024 * 1024;
543#else
544 /* The boot rom passes these to us in MHz. Linux now expects
545 * them to be in Hz.
546 */
547 bd->bi_intfreq *= 1000000;
548 bd->bi_busfreq *= 1000000;
549 bd->bi_cpmfreq *= 1000000;
550 bd->bi_brgfreq *= 1000000;
551#endif
552
553 cp = (u_char *)def_enet_addr;
554 for (i=0; i<6; i++) {
555 bd->bi_enetaddr[i] = *cp++;
556 }
557}
558#endif /* EST8260 */
559
560#ifdef CONFIG_SBS8260
561void
562embed_config(bd_t **bdp)
563{
564 u_char *cp;
565 int i;
566 bd_t *bd;
567
568 /* This should provided by the boot rom.
569 */
570 bd = &bdinfo;
571 *bdp = bd;
572 bd->bi_baudrate = 9600;
573 bd->bi_memsize = 64 * 1024 * 1024;
574
575 /* Set all of the clocks. We have to know the speed of the
576 * external clock. The development board had 66 MHz.
577 */
578 bd->bi_busfreq = 66666666;
579 clk_8260(bd);
580
581 /* I don't know how to compute this yet.
582 */
583 bd->bi_intfreq = 133000000;
584
585
586 cp = (u_char *)def_enet_addr;
587 for (i=0; i<6; i++) {
588 bd->bi_enetaddr[i] = *cp++;
589 }
590}
591#endif /* SBS8260 */
592
593#ifdef CONFIG_RPX8260
594void
595embed_config(bd_t **bdp)
596{
597 u_char *cp, *keyvals;
598 int i;
599 bd_t *bd;
600
601 keyvals = (u_char *)*bdp;
602
603 bd = &bdinfo;
604 *bdp = bd;
605
606 /* This is almost identical to the RPX-Lite/Classic functions
607 * on the 8xx boards. It would be nice to have a key lookup
608 * function in a string, but the format of all of the fields
609 * is slightly different.
610 */
611 cp = keyvals;
612 for (;;) {
613 if (*cp == 'E') {
614 cp++;
615 if (*cp == 'A') {
616 cp += 2;
617 rpx_eth(bd, cp);
618 }
619 }
620 if (*cp == 'S') {
621 cp++;
622 if (*cp == 'B') {
623 cp += 2;
624 bd->bi_baudrate = rpx_baseten(cp);
625 }
626 }
627 if (*cp == 'D') {
628 cp++;
629 if (*cp == '1') {
630 cp += 2;
631 bd->bi_memsize = rpx_baseten(cp) * 1024 * 1024;
632 }
633 }
634 if (*cp == 'X') {
635 cp++;
636 if (*cp == 'T') {
637 cp += 2;
638 bd->bi_busfreq = rpx_baseten(cp);
639 }
640 }
641 if (*cp == 'N') {
642 cp++;
643 if (*cp == 'V') {
644 cp += 2;
645 bd->bi_nvsize = rpx_baseten(cp) * 1024 * 1024;
646 }
647 }
648
649 /* Scan to the end of the record.
650 */
651 while ((*cp != '\n') && (*cp != 0xff))
652 cp++;
653
654 /* If the next character is a 0 or ff, we are done.
655 */
656 cp++;
657 if ((*cp == 0) || (*cp == 0xff))
658 break;
659 }
660 bd->bi_memstart = 0;
661
662 /* The memory size includes both the 60x and local bus DRAM.
663 * I don't want to use the local bus DRAM for real memory,
664 * so subtract it out. It would be nice if they were separate
665 * keys.
666 */
667 bd->bi_memsize -= 32 * 1024 * 1024;
668
669 /* Set all of the clocks. We have to know the speed of the
670 * external clock.
671 */
672 clk_8260(bd);
673
674 /* I don't know how to compute this yet.
675 */
676 bd->bi_intfreq = 200000000;
677}
678#endif /* RPX6 for testing */
679
680#ifdef CONFIG_ADS8260
681void
682embed_config(bd_t **bdp)
683{
684 u_char *cp;
685 int i;
686 bd_t *bd;
687
688 /* This should provided by the boot rom.
689 */
690 bd = &bdinfo;
691 *bdp = bd;
692 bd->bi_baudrate = 9600;
693 bd->bi_memsize = 16 * 1024 * 1024;
694
695 /* Set all of the clocks. We have to know the speed of the
696 * external clock. The development board had 66 MHz.
697 */
698 bd->bi_busfreq = 66666666;
699 clk_8260(bd);
700
701 /* I don't know how to compute this yet.
702 */
703 bd->bi_intfreq = 200000000;
704
705
706 cp = (u_char *)def_enet_addr;
707 for (i=0; i<6; i++) {
708 bd->bi_enetaddr[i] = *cp++;
709 }
710}
711#endif /* ADS8260 */
712
713#ifdef CONFIG_WILLOW
714void
715embed_config(bd_t **bdp)
716{
717 u_char *cp;
718 int i;
719 bd_t *bd;
720
721 /* Willow has Open Firmware....I should learn how to get this
722 * information from it.
723 */
724 bd = &bdinfo;
725 *bdp = bd;
726 bd->bi_baudrate = 9600;
727 bd->bi_memsize = 32 * 1024 * 1024;
728
729 /* Set all of the clocks. We have to know the speed of the
730 * external clock. The development board had 66 MHz.
731 */
732 bd->bi_busfreq = 66666666;
733 clk_8260(bd);
734
735 /* I don't know how to compute this yet.
736 */
737 bd->bi_intfreq = 200000000;
738
739
740 cp = (u_char *)def_enet_addr;
741 for (i=0; i<6; i++) {
742 bd->bi_enetaddr[i] = *cp++;
743 }
744}
745#endif /* WILLOW */
746
747#if defined(CONFIG_XILINX_ML300) || defined(CONFIG_XILINX_ML403)
748void
749embed_config(bd_t ** bdp)
750{
751 static const unsigned long line_size = 32;
752 static const unsigned long congruence_classes = 256;
753 unsigned long addr;
754 unsigned long dccr;
755 uint8_t* cp;
756 bd_t *bd;
757 int i;
758
759 /*
760 * Invalidate the data cache if the data cache is turned off.
761 * - The 405 core does not invalidate the data cache on power-up
762 * or reset but does turn off the data cache. We cannot assume
763 * that the cache contents are valid.
764 * - If the data cache is turned on this must have been done by
765 * a bootloader and we assume that the cache contents are
766 * valid.
767 */
768 __asm__("mfdccr %0": "=r" (dccr));
769 if (dccr == 0) {
770 for (addr = 0;
771 addr < (congruence_classes * line_size);
772 addr += line_size) {
773 __asm__("dccci 0,%0": :"b"(addr));
774 }
775 }
776
777 bd = &bdinfo;
778 *bdp = bd;
779 bd->bi_memsize = XPAR_DDR_0_SIZE;
780 bd->bi_intfreq = XPAR_CORE_CLOCK_FREQ_HZ;
781 bd->bi_busfreq = XPAR_PLB_CLOCK_FREQ_HZ;
782 bd->bi_pci_busfreq = XPAR_PCI_0_CLOCK_FREQ_HZ;
783
784 /* Copy the default ethernet address */
785 cp = (u_char *)def_enet_addr;
786 for (i=0; i<6; i++)
787 bd->bi_enetaddr[i] = *cp++;
788
789 timebase_period_ns = 1000000000 / bd->bi_tbfreq;
790 /* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */
791}
792#endif /* CONFIG_XILINX_ML300 || CONFIG_XILINX_ML403 */
793
794#ifdef CONFIG_IBM_OPENBIOS
795/* This could possibly work for all treeboot roms.
796*/
797#if defined(CONFIG_BUBINGA)
798#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */
799#else
800#define BOARD_INFO_VECTOR 0xFFFE0B50
801#endif
802
803void
804embed_config(bd_t **bdp)
805{
806 u_char *cp;
807 int i;
808 bd_t *bd, *treeboot_bd;
809 bd_t *(*get_board_info)(void) =
810 (bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR);
811#if !defined(CONFIG_STB03xxx)
812
813 /* shut down the Ethernet controller that the boot rom
814 * sometimes leaves running.
815 */
816 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
817 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
818 out_be32((volatile u32*)EMAC0_BASE,0x20000000); /* then reset EMAC */
819#endif
820
821 bd = &bdinfo;
822 *bdp = bd;
823 if ((treeboot_bd = get_board_info()) != NULL) {
824 memcpy(bd, treeboot_bd, sizeof(bd_t));
825 }
826 else {
827 /* Hmmm...better try to stuff some defaults.
828 */
829 bd->bi_memsize = 16 * 1024 * 1024;
830 cp = (u_char *)def_enet_addr;
831 for (i=0; i<6; i++) {
832 /* I should probably put different ones here,
833 * hopefully only one is used.
834 */
835 bd->BD_EMAC_ADDR(0,i) = *cp;
836
837#ifdef CONFIG_PCI
838 bd->bi_pci_enetaddr[i] = *cp++;
839#endif
840 }
841 bd->bi_tbfreq = 200 * 1000 * 1000;
842 bd->bi_intfreq = 200000000;
843 bd->bi_busfreq = 100000000;
844#ifdef CONFIG_PCI
845 bd->bi_pci_busfreq = 66666666;
846#endif
847 }
848 /* Yeah, this look weird, but on Redwood 4 they are
849 * different object in the structure. Sincr Redwwood 5
850 * and Redwood 6 use OpenBIOS, it requires a special value.
851 */
852#if defined(CONFIG_REDWOOD_5) || defined (CONFIG_REDWOOD_6)
853 bd->bi_tbfreq = 27 * 1000 * 1000;
854#endif
855 timebase_period_ns = 1000000000 / bd->bi_tbfreq;
856}
857#endif /* CONFIG_IBM_OPENBIOS */
858
859#ifdef CONFIG_EP405
860#include <linux/serial_reg.h>
861
862void
863embed_config(bd_t **bdp)
864{
865 u32 chcr0;
866 u_char *cp;
867 bd_t *bd;
868
869 /* Different versions of the PlanetCore firmware vary in how
870 they set up the serial port - in particular whether they
871 use the internal or external serial clock for UART0. Make
872 sure the UART is in a known state. */
873 /* FIXME: We should use the board's 11.0592MHz external serial
874 clock - it will be more accurate for serial rates. For
875 now, however the baud rates in ep405.h are for the internal
876 clock. */
877 chcr0 = mfdcr(DCRN_CHCR0);
878 if ( (chcr0 & 0x1fff) != 0x103e ) {
879 mtdcr(DCRN_CHCR0, (chcr0 & 0xffffe000) | 0x103e);
880 /* The following tricks serial_init() into resetting the baud rate */
881 writeb(0, UART0_IO_BASE + UART_LCR);
882 }
883
884 /* We haven't seen actual problems with the EP405 leaving the
885 * EMAC running (as we have on Walnut). But the registers
886 * suggest it may not be left completely quiescent. Reset it
887 * just to be sure. */
888 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
889 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
890 out_be32((unsigned *)EMAC0_BASE,0x20000000); /* then reset EMAC */
891
892 bd = &bdinfo;
893 *bdp = bd;
894#if 1
895 cp = (u_char *)0xF0000EE0;
896 for (;;) {
897 if (*cp == 'E') {
898 cp++;
899 if (*cp == 'A') {
900 cp += 2;
901 rpx_eth(bd, cp);
902 }
903 }
904
905 if (*cp == 'D') {
906 cp++;
907 if (*cp == '1') {
908 cp += 2;
909 rpx_memsize(bd, cp);
910 }
911 }
912
913 if (*cp == 'N') {
914 cp++;
915 if (*cp == 'V') {
916 cp += 2;
917 rpx_nvramsize(bd, cp);
918 }
919 }
920 while ((*cp != '\n') && (*cp != 0xff))
921 cp++;
922
923 cp++;
924 if ((*cp == 0) || (*cp == 0xff))
925 break;
926 }
927 bd->bi_intfreq = 200000000;
928 bd->bi_busfreq = 100000000;
929 bd->bi_pci_busfreq= 33000000 ;
930#else
931
932 bd->bi_memsize = 64000000;
933 bd->bi_intfreq = 200000000;
934 bd->bi_busfreq = 100000000;
935 bd->bi_pci_busfreq= 33000000 ;
936#endif
937}
938#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 16:23:13 -0500