2 files changed, 6 insertions, 4 deletions

diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.c
index 9017c547a6f6..26818bbb6cff 100644
--- a/arch/ppc/boot/common/ns16550.c
+++ b/arch/ppc/boot/common/ns16550.c
@@ -23,7 +23,7 @@ static int shift;
 
 unsigned long serial_init(int chan, void *ignored)
 {
-        unsigned long com_port;
+        unsigned long com_port, base_baud;
         unsigned char lcr, dlm;
 
         /* We need to find out which type io we're expecting.  If it's
@@ -43,6 +43,8 @@ unsigned long serial_init(int chan, void *ignored)
 
         /* How far apart the registers are. */
         shift = rs_table[chan].iomem_reg_shift;
+        /* Base baud.. */
+        base_baud = rs_table[chan].baud_base;
         
         /* save the LCR */
         lcr = inb(com_port + (UART_LCR << shift));
@@ -62,9 +64,9 @@ unsigned long serial_init(int chan, void *ignored)
         else {
                 /* Input clock. */
                 outb(com_port + (UART_DLL << shift),
-                     (BASE_BAUD / SERIAL_BAUD) & 0xFF);
+                     (base_baud / SERIAL_BAUD) & 0xFF);
                 outb(com_port + (UART_DLM << shift),
-                     (BASE_BAUD / SERIAL_BAUD) >> 8);
+                     (base_baud / SERIAL_BAUD) >> 8);
                 /* 8 data, 1 stop, no parity */
                 outb(com_port + (UART_LCR << shift), 0x03);
                 /* RTS/DTR */
diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S
index 47e641455bc5..c96c9f80521e 100644
--- a/arch/ppc/boot/common/util.S
+++ b/arch/ppc/boot/common/util.S
@@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache)
 1:      dcbf    r0,r3                   # Flush the data cache
         icbi    r0,r3                   # Invalidate the instruction cache
         addi    r3,r3,0x10              # Increment by one cache line
-        cmplwi  cr0,r3,r4               # Are we at the end yet?
+        cmplw   cr0,r3,r4               # Are we at the end yet?
         blt     1b                      # No, keep flushing and invalidating
 #else
         /* Enable, invalidate and then disable the L1 icache/dcache. */