diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/math-emu/mtfsf.c | 58 |
1 files changed, 23 insertions, 35 deletions
diff --git a/arch/powerpc/math-emu/mtfsf.c b/arch/powerpc/math-emu/mtfsf.c index dbce92e4f046..44b0fc8214f4 100644 --- a/arch/powerpc/math-emu/mtfsf.c +++ b/arch/powerpc/math-emu/mtfsf.c | |||
| @@ -11,48 +11,36 @@ mtfsf(unsigned int FM, u32 *frB) | |||
| 11 | u32 mask; | 11 | u32 mask; |
| 12 | u32 fpscr; | 12 | u32 fpscr; |
| 13 | 13 | ||
| 14 | if (FM == 0) | 14 | if (likely(FM == 1)) |
| 15 | return 0; | 15 | mask = 0x0f; |
| 16 | 16 | else if (likely(FM == 0xff)) | |
| 17 | if (FM == 0xff) | 17 | mask = ~0; |
| 18 | mask = 0x9fffffff; | ||
| 19 | else { | 18 | else { |
| 20 | mask = 0; | 19 | mask = ((FM & 1) | |
| 21 | if (FM & (1 << 0)) | 20 | ((FM << 3) & 0x10) | |
| 22 | mask |= 0x90000000; | 21 | ((FM << 6) & 0x100) | |
| 23 | if (FM & (1 << 1)) | 22 | ((FM << 9) & 0x1000) | |
| 24 | mask |= 0x0f000000; | 23 | ((FM << 12) & 0x10000) | |
| 25 | if (FM & (1 << 2)) | 24 | ((FM << 15) & 0x100000) | |
| 26 | mask |= 0x00f00000; | 25 | ((FM << 18) & 0x1000000) | |
| 27 | if (FM & (1 << 3)) | 26 | ((FM << 21) & 0x10000000)) * 15; |
| 28 | mask |= 0x000f0000; | ||
| 29 | if (FM & (1 << 4)) | ||
| 30 | mask |= 0x0000f000; | ||
| 31 | if (FM & (1 << 5)) | ||
| 32 | mask |= 0x00000f00; | ||
| 33 | if (FM & (1 << 6)) | ||
| 34 | mask |= 0x000000f0; | ||
| 35 | if (FM & (1 << 7)) | ||
| 36 | mask |= 0x0000000f; | ||
| 37 | } | 27 | } |
| 38 | 28 | ||
| 39 | __FPU_FPSCR &= ~(mask); | 29 | fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) & |
| 40 | __FPU_FPSCR |= (frB[1] & mask); | 30 | ~(FPSCR_VX | FPSCR_FEX | 0x800); |
| 41 | 31 | ||
| 42 | __FPU_FPSCR &= ~(FPSCR_VX); | 32 | if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | |
| 43 | if (__FPU_FPSCR & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | | ||
| 44 | FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC | | 33 | FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC | |
| 45 | FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI)) | 34 | FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI)) |
| 46 | __FPU_FPSCR |= FPSCR_VX; | 35 | fpscr |= FPSCR_VX; |
| 47 | 36 | ||
| 48 | fpscr = __FPU_FPSCR; | 37 | /* The bit order of exception enables and exception status |
| 49 | fpscr &= ~(FPSCR_FEX); | 38 | * is the same. Simply shift and mask to check for enabled |
| 50 | if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) || | 39 | * exceptions. |
| 51 | ((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) || | 40 | */ |
| 52 | ((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) || | 41 | if (fpscr & (fpscr >> 22) & 0xf8) |
| 53 | ((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) || | ||
| 54 | ((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE))) | ||
| 55 | fpscr |= FPSCR_FEX; | 42 | fpscr |= FPSCR_FEX; |
| 43 | |||
| 56 | __FPU_FPSCR = fpscr; | 44 | __FPU_FPSCR = fpscr; |
| 57 | 45 | ||
| 58 | #ifdef DEBUG | 46 | #ifdef DEBUG |